illustrate
The WM9705 is a high-quality stereo audio codec with an integrated touchscreen controller.
The audio part complies with the Intel AC'97 version 2.2 specification. It performs full-duplex 18-bit codec functions, supports variable sampling rates from 8 to 48k samples/sec, and has a high signal-to-noise ratio. Optional AC 97 features include 3D sound enhancement, line level output, stereo buffered headphone output, hardware sample rate conversion, master/secondary mode operation and S/PDIF output. Includes headphone auto-detection, I2S output, and headphone buffer on mono output.
In addition, WM9705 integrates a complete 4-wire touch screen controller, including on-chip screen driver, pen detection function and pressure measurement capability.
A 5-pin digital bidirectional AC link serial interface allows transfer of control data, DAC and ADC words between AC 97 controllers. The WM9705 operates fully on 3V or 5V or mixed 3/5V supplies and is packaged in an industry standard 48-pin TQFP package with a 7mm or smaller 7x7x0.9mm QFN.
Features

AC 97 rev2.2 compatible codec with digital pen, 18-bit stereo audio codec, on-chip sample rate conversion, multi-channel input mixer, S/PDIF digital audio output, AUX and mono output on Headphone driver, 4-wire touchscreen interface with coordinate and pressure measurement, and pen drop detection, wake-up pen drop from sleep mode, 3V to 5V operation, extensive power management features including hardware power drop options, standard AC'97 pinout in 48-pin TQFP package or 48-pin QFN package. applications, personal digital assistants and "smartphones", PocketPC systems

Device Description Introduction This specification describes the WM9705 audio codec whose hardware and software design is compatible with the Intel AC 97 rev2.2 component specification. The device is a derivative of the basic AC'97 codec with added support for resistive touchscreen pen input. Supports Variable Rate Audio (VRA) at the rates defined in the Intel v2.1 or v2.2 specification, and provides a SPDIF output port that can optionally be used to output PCM DAC information to an external processor. A key feature of digital pen functional operation is that screen drive activity ceases when the pen is lifted from the screen, minimizing audio performance degradation and power consumption.
WM9705 provides the following functions:
Supports Intel-specified VRA stereo audio codec with different audio sampling rates Pen digitizer function with 4-wire pen interface, supports pen drop detection, pen pressure measurement and wake-up pen drop.
Auxiliary ADC input for temperature, power and battery monitoring.
Pen flag and ADC busy flag, output to pin, and provide mask input pin to delay pen conversion while LCD is active Optional SPDIF and I2S audio output (SPDIF output may be hardware enabled, so no driver support is required )
The headphone driver feature and optional headphone or headphone plug-in auto-detection are strongly recommended to study the Intel AC 97 rev2.2 specification concurrently with this document: this specification can be downloaded from the Intel website.
The WM9705 is fully operable on 3V or 5V or mixed 3/5V supplies and is housed in an industry standard 48-pin TQFP package with a 7mm body size.
AC'97 Features
The WM9705 implements the basic functions of AC'97 rev2.2, as well as some enhancements:
Supports all 2.2-specified variable audio sample rate 3D stereo enhancements.
Headphone support on aux outputs (pins 39, 41)
Use the pin programming of CID0-pin to realize the main/auxiliary codec
SPDIF audio output with control settings compatible with version 2.2.

Non-AC'97 Functions In addition to providing AC'97 functions, WM9705 also supports:
4-line pen digitizer with integrated screen driver, with highly flexible operating modes, supporting autonomous screen transitions, as well as assisted transitions. Screen X and Y driven by the AUX and VID stereo input pins are connected and they are still connected.
Headphone driver capability for the mono output, with an additional signal routing switch PSEL that allows routing of the phone input to the mono output An additional switch HPND after the mixer allows a DAC-free mix to be output to the headphone output, thus allowing The unmixed DAC output goes to the line output.
The I2S audio output capability, in addition to the SPDIF output, allows multi-channel solutions to support additional external audio DACs. SPDIF output may be hardware enabled.
Option to route stereo audio ADC output to SPDIF and/or I2S digital output automatically detects headphone or headphone plugged into the AUX headphone output, and the mic signal is routed internally from the headphone pin to the MIC1 input.
Battery monitoring input BMON, supports direct connection to battery voltages up to 6.5V.
The MPM switch allows the DAC+ mixer output to be mixed to a single output, and the DAC+ phone and/or PCBEEP to be independently mixed to the line output or HPOUT.
Reset Power-Down Override – Hold the mask override PR bit high in reset, forcing the WM9705 into low power mode

Pen Digitizer and Auxiliary ADC A 4-wire input pen digitizer function is included on the WM9705. The circuit consists of the driver circuit that drives a typical resistive touch screen used on a PDA, and a 12-bit resolution ADC that converts pen input values. This ADC can also be used to perform additional auxiliary ADC conversions of levels present on AUXADC, BMON, PCBEEP or phone pins. A control bit (PHIZ in register 78h) is provided to make the PCBEEP and phone inputs high impedance (disconnected internally to cut off the signal path) when needed.
The operation of the pen digitizer function is controlled by the digitizer control registers 76h and 78h. When the result is sent back in AC's 97-slot data format, the ADC conversion result is obtained by reading from the contents of Bits[11-0] in register 7Ah or by enabling the AC link timeslot transmission method (optional). Pen-type digital converter ADC is a 12bit successive approximation converter with good differential nonlinear performance.
Pen-to-digital converter ADCs can be used to convert pen input data or voltages on AUXADC, BMON, PCBEEP, or phone pins. Thus, functions such as battery monitoring or temperature measurement can be implemented.
The following digital pen functions are provided:
Supports wake-up pen off, pen detection, pressure measurement, auxiliary transition, mask transition delay override or synchronous operation options, slot or R/W register data transfer, programmable screen drive sampling delay, programmable pen drop detection threshold related to pen digital pen For operation details, please refer to the "Pen Digital Pen Instructions" section. Note that the pins assigned to the X/Y screen connections are typically used for the AUX and VID stereo inputs in legacy AC'97 codecs. In the WM9705, these pins remain connected to the mixer and ADC inputs and can be used as analog inputs, the gain through the mixer input is fixed at 0dB. Use bit 15 in the appropriate register to provide normal mute functionality. When the screen is driven, it is recommended to leave these mute bits as "mute". Reading back the registers will report 0dB gain and programmed mute values. The ADC gain controls on the auxiliary and video inputs work correctly.
3D Stereo Enhancement This device contains stereo enhancement circuitry designed to optimize the listening experience of the device when used in a typical PC operating environment. That said, place a pair of speakers on either side of the display with little space between them. This circuit creates a differential signal by differential left and right channel playback data and then filters this differential signal using low pass and high pass filters, the time constants of the low pass and high pass filters are determined using the time constants connected to CX3D pin 33 and 34 external capacitors to set. Typically, values of 100nF and 47nF set the high-pass and low-pass poles at about 100Hz and 1kHz, respectively. This frequency band corresponds to the range where the ear is most sensitive to directional effects.
The filtered differential signal is gain adjusted by the amount set using the 4-bit value written to bits 3 to 0 of register 22h. A value of 0h is disabled, and a value of Fh is the maximum effect. Usually 8 hours is the best value. User interfaces typically use a sliding control that allows the user to adjust the level of enhancement to suit the program material. Bit D13 3D in register 20h is the overall 3D enable bit. Reset register 00h reads the value 11000 from bit D14 back to D10. This corresponds to decimal 24, which is registered with Intel as Wolfson Stereo Enhancement.
Note that the external capacitors that set the filter poles applied to differential signals can be adjusted in value or even replaced with direct connections between pins. If such adjustments are made, the amount of differential signal fed back into the main signal path may be significant and may result in large signals that may limit, distort, or overdrive the signal path or speakers. Adjust these values carefully to choose your preferred acoustics. There is no provision for pseudo-stereoscopic effects. No enhancement is applied to mono signals (if the signals are in phase and the same amplitude). The signal from the PCM DAC channel can have stereo enhancement application. It can also be bypassed if desired. This function is enabled by setting bit pop register 20h.
Variable Sample Rate Support The DACs and ADCs on this device support all recommended sample rates specified in the Intel AC 97 rev2.1 and rev2.2 Audio Rate Specifications. The default rate is 48ks/s. If Selectable Rate is selected and Variable Rate Audio is enabled (Register 2Ah, Bit 0), the AC'97 interface will continue to operate at 48k words per second, but data will be transmitted across the link in bursts, thus Achieves the selected net sampling rate. It depends on the AC'97 version 2.1/2 compliant controller to ensure that data is provided to and received from the AC link at the appropriate rate.
Variable rate is selected by writing to registers 2Ch (DAC) and 32h (ADC). The ADC and DAC rates can be set independently, and the rates for the left and right channels are always the same. Note that register 2Ch should only be written when the DAC is powered up, similarly, register 32h should only be written when the ADC is powered up (see register 26h for power control) The device supports sampling on demand. That is, when the DAC signal processing circuit needs another sample, a sample request is sent to the controller, and the controller must respond with a data sample in the next frame it sends. For example, if you choose a rate of 24ks/s, the device will request samples from the controller for each stereo DAC every other frame on average. Note that if an unsupported rate is written to one of the rate registers, the rate will default to the closest supported rate. Then, when asked, the register will respond at the device's default supported rate.
The WM9705 clock will be automatically scaled according to the MCLK frequency, where MCLK is not equal to 24.576MHz. Under the 24MHz clock, the BCLK frequency is expected to be 12MHz, and the sampling frequency (SYNC0 is expected to be BCLK/256=46.875kHz).
Audio sample rate control value D15-D0 8000 1F40 11025 2B11 16000 3E80 22050 5622 32000 7D000 44100 AC44 48000 BB80 Table 1 Supported variable sample rate SPDIF or I2S digital audio data output via hold pin 44 ( SPEN) high, or by writing to the SPDIF control bit in register 2Ah, the WM9705 SPDIF output can be enabled in hardware. If SPDIF pin 48 is pulled high by a weak pull-up (eg 100k) at startup, the SPDIF capability bit in register 28h is set to '0', ie no SPDIF capability. This allows options to be populated so that when no SPDIF external components are provided, the driver will see the "No SPDIF Capable" and "Grayed Out" relevant boxes in the control panel.
Alternatively, digital audio can be output in I2S format using pin 44 (SPEN) as the data output, and the frame clock or LRCLK is output to pin 43. Data is recorded onto pin 44 via the regular BITCLK at 256fs, which will also be used as MCLK if the data is brought to an external DAC. Operation in this mode is selected by setting bit I2S in register 5Ch. 64fs bitclk is also available and can be output on SPDIF by setting bit I2S64 in register 74h. Note that I2S operations only support 48ks/s operations. Hardware that selects SPDIF operation by pulling pin SPEN 'hi' is compatible with I2S operation, provided that a weak pull-up (~100k) is used to keep SPEN high at boot. When I2S is enabled, the SPEN pin becomes the I2S data output pin and the weak pull-up on this pin is too large.
For SPDIF and I2S modes, the output data can be sent from the WM9705 via the AC link in the same slot as the normal DAC data, or it can be sent in a different slot. The output slot containing SPDIF/I2S data is selected by Bits SPSA[1:0] in Register 2Ah. The WM9705 is compliant with the AC'97 rev2.2 specification in terms of slot mapping; therefore, the default operating mode is to output SPDIF or I2S data from the next available data slot after the currently used audio data slot. Alternatively, if desired, data can be mapped from any available time slot by selection using the SPSA bits. The following table shows the default slot mapping for audio DAC and SPDIF/I2S data: (more details later in the register description section).

Headphone driver and headphone auto-detection The headphone driver function is provided on HPOUT output pins 39 and 41 (referred to as AUXOUT in the AC'97 rev2.2 specification) and MONOOUT output pin 37. Headphones with impedance typically above 16Ω can be connected to these pins. AC coupling with appropriately sized capacitors is recommended to remove the mid-rail DC pedestal on these outputs. The AC'97 rev2.2 specification recommends the use of 32Ω headphones; if headphones are connected for use as headphones, with the stereo earbuds driven in parallel, the impedance of each diaphragm must be at least 32Ω. In many applications, it is desirable to be able to connect stereo headphones to the headphone output pins, or to be able to connect mono headphones, including earbuds and microphones. The microphone signal is sent through the tip of a typical 3-wire jack. In this case, you need to be able to automatically detect the connection of a headset or headset (with a microphone). The main characteristic of headphones and microphones compared to headphones is that the microphone impedance is usually much higher than the headphone diaphragm (assuming a typical dynamic headphone). So a weak pull-up can be connected to the tip connection of the headphone jack.
When headphones are connected, the low impedance of the headphones to ground pulls the DC level down close to ground. If a headset with a microphone is plugged in, the high impedance of the microphone will not pull down the DC level of the tip connection, the DC on that pin now rises to near positive supply. This change in DC level is detected, thus allowing detection of changes from headphones to microphone (of course also unplugged). When this event is detected, the headphone amplifier connected to the driver tip will shut down and the signal on this pin will be routed to the MIC1 input as a microphone input. This auto-detection comparator is enabled by setting bit HSCMP. The pull-up current is enabled by setting bit MPUEN in register 5Ch and toggles the interrupt signal on the PENDET pin. When bit HSDT is set, the mic1 input is connected to a comparator whose threshold is set on the mid rail. When the comparator output is low, the headphone driver is enabled. When the comparator output goes high (i.e. the pull-up current times the external impedance to ground on the mic1 pin is greater than the mid rail), the headphone amplifier is turned off and the mic1 signal is taken internally from the headphone output pin (39).
Headphone auto-detection

The output signal of the comparator can be accessed by reading bit HSCP in register 5Ch. Automatic detection can be used by setting the HSEN bit, or external control can be used by using the HSDT bit, which is an overtravel that forces the earphone tri-state and microphone path switching functions to occur. For example, this feature allows the use of a stereo headset with a microphone and a switch in the cable. The switch converts the headphone to a mono headphone, connecting the microphone via the prompt connection on the jack. If used in a product, such as a mobile phone that supports MP3, the user only needs to toggle a switch in the headset cable to switch from headset use to headset use, so that phone calls can be answered or started at the same time. A pull-up current can also be used to provide so-called "phantom power" to dynamic microphones with proper microphone selection.

AC-LINK Audio Output Frame (SDATAOUT) The audio output frame data stream corresponds to a multiplexed bundle of all digital output data for the WM9705's DAC input and control registers. As previously mentioned, each audio output frame supports up to 12 slots of 20-bit output data. Slot 0 is a special reserved slot containing 16 bits for the AC link protocol infrastructure.
In slot 0, the first bit is the global bit (SDATAOUT slot 0, bit 15) that marks the validity of the entire audio frame. If the valid frame bit is 1, it means that the current audio frame contains at least one time slot with valid data. The next 12-bit position sampled by the WM9705 indicates which of the corresponding 12 time slots contains valid data.
In this way, data streams of different sampling rates can be transmitted over the AC link at their fixed 48kHz audio frame rate.
Start of Audio Output Frame A new audio output frame begins with a synchronized low-to-high transition, as shown in Figure 13. Synchronized to the rising edge of BITCLK. The SYNC assertion is sampled by the WM9705 immediately following the falling edge of BITCLK. This falling edge marks the beginning of both sides of the AC link becoming aware of a new audio frame. On the next rising edge of BITCLK, AC'97 transitions SDATAOUT to the first bit position of slot 0 (valid frame bit). Each new bit position is presented to the AC link on the rising edge of BITCLK and then sampled by the WM9705 on the next falling edge of BITCLK. This sequence ensures that data transitions and subsequent sample points of incoming and outgoing data streams are time-aligned.
Baseline AC'97 specified audio functions must always convert the sample rate to the fixed 48ks/s on AC'97 controllers. This requirement is necessary to ensure interoperability between the AC'97 controller and the WM9705, which can be ensured, among other things, by defining specified AC'97 baseline characteristics.
The composite stream of SDATAOUT is MSB justified (MSB first), and the AC'97 controller fills all invalid slot positions with zeros.
If there are less than 20 valid bits in the allocated valid time slot, the AC'97 controller always fills all subsequent invalid bit positions of the 20-bit time slot with 0s.
As an example, consider an 8-bit sample stream that is being played to a WM9705 DAC. The first 8 bit positions are shown to the DAC (MSB justified) and the last 12 bit positions are filled with 0s by the AC'97 controller. This ensures that no DC offset is introduced by the least significant bits, regardless of the resolution of the DAC (16, 18 or 20 bits) implemented.
When a stream of mono audio samples is output from an AC'97 controller, both the left and right sample stream time slots must be filled with the same data.

Digital Pen Operation The pen digitizer features include a 12-bit successive approximation ADC with a multi-channel input multiplexer to select the signal to convert, and a switch matrix to control the drive of the signal to the resistive touch screen panel. For control and sequence transition operations, a finite state machine is provided.
A pen down detection scheme is provided to allow detection of when the pen is in contact with the screen. This allows the touchscreen to be driven only when the pen is down, saving unnecessary power consumption. This minimizes audio degradation due to the significant current flowing through the on-chip screen drive switches.

Recommended external components,