Features: Provides auxiliary switch activation Complementary to main power switch driver: Programmable dead time (turn-on delay) between each switch activation. Voltage Mode Control with Feedforward Operation: Transformer Volts-Second Product and Programmable Limits for PWM Duty Cycle. Auxiliary Outputs: Multiple Protections with Latching Shutdown and Soft Start Features: Low Supply Current ( 100 μA Start, 1.5 mA Operation)
DESCRIPTION The UCC3580 family of PWM controllers is designed to implement various active clamp/reset and synchronous rectification switching converter topologies. While including all the necessary features for fixed frequency, high performance pulse width modulation, the design additionally features the inclusion of an auxiliary switch driver that complements the main power switch with programmable dead time between each transition time or delay. The active clamp/reset technique allows single-ended converters to operate beyond 50% duty cycle while reducing voltage stress on the switches and allowing greater flux swings in the power transformer. This approach also allows switching losses to be reduced by recovering the energy stored in parasitic elements such as leakage inductance and switched capacitors. The oscillator is programmed with two resistors and a capacitor to set the switching frequency and maximum duty cycle. Separate synchronized ramps provide voltage feed-forward pulse width modulation and programmed maximum volt second limit. The clock generated by the oscillator contains frequency and maximum duty cycle information.

The main gate drive output (OUT1) is controlled by a pulse width modulator. The second output (OUT2) is intended to activate the auxiliary switch during the off-time of the main switch, except for a dead-time of two switches off between each transition, programmed by a single external resistor. This design provides two options for OUT2, normal and reverse. In the -1 and -2 versions, OUT2 is normal and can be used to drive the PMOS fet. In the -3 and -4 versions, OUT2 is inverted and can be used to drive the NMOS fet. In all versions, both the main and auxiliary switches are held until start-up, when the PWM command goes to zero duty cycle. Under fault conditions, OUT1 is held while OUT2 operates at maximum duty cycle with a guaranteed off-time equal to the sum of the two dead-times.
Undervoltage lockout monitors supply voltage (VDD), precision reference (REF), input line voltage (line), and shutdown comparator (SHTDWN). If a fault condition is detected by any of these four sensors, the soft start will initiate a return to full operation. VDD threshold, on and off, 15V and 8.5V for -2 and -4 versions, 9V and 8.5V for -1 and -3 versions. The UCC1580-x is specified for operation in the military temperature range of -55°C to 125°C. The UCC2580-x is specified to operate between -40°C and 85°C. The UCC3580-x is specified to operate between 0°C and 70°C. Packaging options include 16-pin surface mount or dual-in-line, and 20-pin plastic lead-free chip carriers.

PIN description

CLK: Oscillator clock output pin from low impedance CMOS driver. CLK is high during the guaranteed shutdown time. CLK can be used to synchronize up to five other UCC3580 PWMs. Delay: A resistor from delay to ground programs the non-overlapping delay between Output 1 and Output 2. The delay times Delay1 and Delay2 are shown in Figure 1 as follows: Dela yp FR 11 3=•. Delay2 is designed to be larger than Delay1, as shown in Figure 2. Inverted input error amplifier. The non-vertical input of the error amplifier is internally set to 2.5V. EAIN is used for feedback and loop compensation. EAOUT: Error amplifier output and input to the PWM comparator. The loop compensation component is connected from EAOUT to EAIN. Ground: Signal ground. Row: Hysteresis comparator input. Thresholds are 5.0V and 4.5V. Used to detect the input line voltage and turn off output 1 when the line voltage is low. OSC1 and OSC2: Oscillator programming pins. A resistor connects each pin to a timing capacitor. A resistor connected to OSC1 sets the maximum value in time. A resistor connected to OSC2 controls the guaranteed off time. Total frequency combined with timing capacitors. The frequency and maximum duty cycle are roughly given by:

() Frequency 1 R1 1.25 R2 CT=++. Maximum duty cycle R1 R1.25 R2
The maximum duty cycle of +UT1 will be slightly reduced, which is Delay1 programmed by R3. Gate drive output for the main switch, available up to 50 volts and 1A down. Ground connection for gate driver. Connect PGND to GND at a point so that the high frequency components of the output switch current are not on the ground plane of the board. Ramp: A resistor (R4) from ramp to input voltage and a capacitor (CR) from ramp to ground program the feedforward ramp signal. Ramp discharges to GND when CLK is high and allows charging when CLK is low. RAMP is the line forward sawtooth signal of the PWM comparator. Assuming the input voltage is much greater than 3.3V, the ramp is very linear. The flux comparator compares the ramp signal to 3.3V to limit the maximum allowable volts Second Product: Volt-Second Product Clamp = 3.3: R4/Cr REF: Precision 5.0V Reference Pin. REF can supply up to 5mA to external circuits. REF turns off until VDD exceeds 9V (–1 and –3 versions) or activates the 15V clamp (–2 and –4 versions), and turns off again when VDD drops below 8.5V. Bypass REF to GND with a 1µF capacitor. SHTDWN: Comparator input used to stop the chip. The threshold is 0.5V. When the chip is stopped, OUT1 is low and OUT2 continues to oscillate, ensuring that the off time is equal to the two non-overlapping delay times.

application information

UVLO and Startup For self-biased offline applications, the -2 and -4 versions are recommended (typically 15 volts and 8.5 volts with low UV on-off thresholds). For all other applications, the -1 and -3 versions provide a lower 9V turn-on threshold. When VDD is below the UVLO threshold, the IC requires only a low start-up current of 160µA, enabling the use of large trickle charge resistors (with correspondingly low power dissipation) from the input voltage. VDD has an internal clamp of 15V and can sink up to 10mA. Measures should be taken not to exceed this current. For -2 and -4 versions,
This clamp must be activated to indicate that the UVLO turn-on threshold has been reached. When the UVLO turn-on threshold is exceeded, the internal reference (REF) is displayed. Before asserting the output, the startup logic ensures that LINE and REF are above their respective thresholds and SHTDWN is below their respective thresholds. The line input can be used to monitor the actual input voltage and shut down the IC if it falls below the programmed value. A resistor divider should be used to connect the input voltage to the line input. This feature protects the power supply from excessive current at low line voltages.

Output Configuration The UCC3580 series of integrated circuits are designed to provide control functions for single-ended active clamp circuits. Different drive waveforms for the two switches (main and auxiliary) are required for different implementations of the active clamp approach. The 3 and 4 versions of the IC's complementary complementary non-overlapping waveforms (OUT1 and OUT2) have programmable delays that can be used to drive the main and auxiliary switches. Most active clamp configurations require one of the outputs to be a transformer-coupled drive floating switch (Figure 5). The -1 and -2 versions invert the phase of OUT2 to produce overlapping waveforms. This configuration is suitable for capacitively coupled drive with the ground referenced P-channel auxiliary switch driven by OUT2, while OUT1 directly drives the N-channel main switch (eg Figure 4). Programmable delays can be used judiciously to achieve zero-voltage turn-on of the main and auxiliary switches in the active clamp circuit.

Application Information (continued)

A single pin is used to program the delay between OUT1 and OUT2 on both sets of edges. During the transition from the main switch to the auxiliary switch, the delay is not very critical for the ZVS to turn on. In the first half of the off time of Out1, the body diode of the auxiliary switch is turned on, and Out2 can be turned on at any time. The transition from auxiliary switch to main switch is more critical. The energy stored in the parasitic inductance at the end of the output 2 pulse is used to release the parasitic capacitance on the main switch during the delay time. The delay (delay 1) should be optimally programmed with 1/4 of the resonant period determined by parasitic capacitance and resonant inductance (transformer leakage and/or magnetizing inductance, depending on topology). However, depending on other parasitic circuits, the resonant characteristics may change and, in some cases, ZVS turn-on may not be achieved. The results show that the optimal delay time is independent of the operating conditions of a particular circuit and should be determined specifically for each circuit.

Application Information (continued)

Application Information (continued)