feature

8.0 GHz bandwidth; 3.2 V to 3.6 V power supply; separate priming pump power supply (VP) allows long time tuning; voltage in 3.3V systems; programmable dual-mode prescaler; 8/9, 16/17, 32/ 33 or 64/65; programmable charge pump current; programmable anti-gap pulse width; three-wire serial interface; analog and digital lock detection; 20 lead filing scales packed.

application

Broadband wireless access; satellite systems; instruments; wireless local area networks; radio base stations.

General Instructions

The ADF4108 frequency synthesizer can be used to implement the up-conversion and down-conversion sections of local oscillator wireless receivers and transmitters. It consists of a low-noise digital frequency discriminator, a precision charge pump programmable reference divider, programmable A and B counters, and a dual-modulus prescaler (P/P+1). A (6-bit) and B (13-bit) counters, used with a dual-modulo prescaler (P/P+1), implement an N divider (N=BP+A). In addition, a 14-bit reference counter (R counter) allows selection of the re-input frequency at the PFD input. A complete Phase Locked Loop (PLL) if synthesizer with external loop filter and Voltage Controlled Oscillator (VCO). The very high bandwidth means that frequency multipliers can be used in many high frequency systems, simplifying the system architecture and reducing cost.

Specification

AVDD=DVDD=3.3v±2%, AVDD≤VP≤5.5v, AGND=dgd=CPGND=0v, RSET=5.1kΩ, dBm is 50Ω, TA=TMIN is TMAX, unless otherwise stated.

1. Operating temperature range (Type B) is -40°C to +85°C.

2. B chip specifications are given as typical values.

3. This is the maximum operating frequency of the CMOS counter. The prescaler value should be chosen to ensure that the RF input is divided into frequencies less than this value.

4. AVDD=DVDD=3.3 volts.

5. AC coupling ensures AVDD/2 bias.

6. Guaranteed by design. Sample testing to ensure compliance.

Timing Characteristics

AV=DV=3.3v±2%, AV≤V≤5.5v, AGND=DGND=CPGND=0v, R=5.1kΩ, dBm is 50Ω, T=T～T, unless otherwise specified.

1. Guaranteed by design, but not production tested.

2. The operating temperature range (Type B) is -40°C to +85°C.

theory of operation

reference input stage

The reference input stage is shown in Figure 10. SW1 and SW2 are normally closed switches. SW3 is normally open. When power down is initiated, SW3 is closed and SW1 and SW2 are open. This ensures that the reference pin is not loaded when power is removed.

RF input stage

The RF input stage is shown in Figure 11. Then there is a two-stage limiting amplifier to generate the CML clock levels required by the prescaler.

Prescaler (P/P+1)

The dual modulo prescaler (P/P+1), together with the A and B counters, achieves a large division ratio N (N=BP+A). A dual-modulo prescaler operating at the CML stage receives the clock from the RF input stage and divides it into manageable frequencies for the CMOS A and B counters. The prescaler is programmable. It can be set in software to 8/9, 16/17, 32/33 or 64/65. It is based on synchronous 4/5 cores. For continuous output frequencies, the smallest divider ratio is possible. This minimum value is determined by the prescaler value P and is given by (PP).

A and B counters

A and B CMOS counters combined with dual modulo prescalers allow a wide range of divide ratios in the PLL feedback counter. The counter is specified to operate when the prescaler output is less than or equal to 300 MHz. So with an RF input frequency of 4.0GHz, a prescaler value of 16/17 is valid, but a value of 8/9 is not.

Pulse swallowing function

The A and B counters, together with a dual modulo prescaler, enable the generation of output frequencies separated only by the reference frequency divided by R. The equation for the VCO frequency is as follows:

where: fVCO is an external voltage-controlled output frequency oscillator (VCO); P is the preset modulus of the dual-modulus prescaler (8/9, 16/17, etc.); B is a binary 13-bit counter (3 to 8191 ); A is the preset division ratio of the binary 6-bit swallow counter (0 to 63); fREFIN is the external reference frequency oscillator.

R counter

A 14-bit R counter allows the input reference frequency to be divided down to generate the reference clock for the phase frequency detector (PFD). Split ratios from 1 to 16383 are allowed.

Phase Frequency Detectors and Charge Pumps

The Phase Frequency Detector (PFD) receives input from the R counter and the N counter (N=BP+A) and produces an output proportional to the phase and frequency difference between them. Figure 13 is a simplified schematic diagram. The PFD includes programmable delay elements to control the width of the backgap pulses. This pulse ensures that there is no dead zone in the PFD transfer function and minimizes phase noise and reference spurs. Two bits in the reference counter latch, ABP2 and ABP1, control the width of the pulse (see Figure 16). A minimum backlash pulse width is not recommended.

Multiplexing and Lock Detection

The output multiplexers on the ADF4108 allow the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2, and M1 in the function latch. Figure 18 shows the complete truth table. Figure 14 shows the MUXOUT section in block diagram form.

lock detection

MUXOUT can be programmed for two types of lock detection: digital lock detection and analog lock detection.

Numlock detection is active high. When the Lock Detection Precision (LDP) bit in the R counter latch is set to 0, the digital lock detection is set high when the phase error for three consecutive phase detector (PD) cycles is less than 15ns. When LDP is set to 1, 5 consecutive cycles less than 15ns are required to set lock detection. It remains high until a phase error greater than 25 ns is detected in any subsequent PD cycles.

The N-channel open-drain analog lock detection should operate using an external pull-up resistor with a nominal value of 10 kΩ. When lockup is detected, the output is high with a narrow, low pulse.

input shift register

The digital part of the ADF4108 includes a 24-bit input shift register, a 14-bit R counter, and a 19-bit N counter, including a 6-bit a counter and a 13-bit B counter. Data is recorded into a 24-bit shift register on each rising edge of CLK. Data is first clocked in the MSB from the shift register to one of four latches on the rising edge of LE. The target latch is determined by the state of two control bits (C2, C1) in the shift register. These are 2 lsbs, DB1 and DB0, as shown in the timing diagram of Figure 2. The truth table for these bits is shown in Table 5.

Figure 15 shows an overview of how the latches are programmed.

function latch

When programming the on-chip function latch, C2 and C1 are set to 1 and 0, respectively. Figure 18 shows the input data format used to program the function latch.

Counter reset

DB2 (F1) is the counter reset bit. When this bit is 1, the R counter and AB counter are reset. For normal operation, this bit should be 0. After power up, the F1 bit needs to be disabled (set to 0). The N counter then continues to count closely aligned with the R counter. (The maximum error is one prescaler period.)

power outage

DB3 (PD1) and DB21 (PD2) provide programmable power down modes. They are enabled by CE pin.

When the CE pin is low, the device is immediately disabled regardless of the state of PD2 and PD1.

In programmed asynchronous shutdown, the device shuts down immediately after locking a 1 to the PD1 bit, provided that PD2 is loaded with a 0.

In programmed synchronous power-down, the charge pump gates the power-down of the device to prevent unnecessary frequency hopping. Once power down is enabled by writing a 1 to PD1 (in the case where a 1 has also been loaded to PD2), the device enters the power down state when the next charge pump event occurs.

When power-down is initiated (synchronous or asynchronous mode, including CE pin initiated power-down), the following events occur:

(1) Remove all valid DC current paths.

(2), R, N, and the timeout counter are forced to their load state conditions.

(3) The charging pump is forced to enter the three-state mode.

(4) Reset the digital lock detection circuit.

(5), RFIN input is debited.

(6) The reference input buffer circuit is disabled.

(7) The input register remains active and can load and lock data.

Multiple output control

The on-chip multiplexer is controlled by M3, M2, and M1 on the ADF4108.

Quick lock enable bit

DB9 of the function latch is the fastlock enable bit. Fast locking is only enabled when this bit is 1.

fast lock mode bit

DB10 of the function latch is the fast lock mode bit. When fastlock is enabled, this bit determines which fastlock mode is used. If the fastlock mode bit is 0, fastlock mode 1 is selected; if the fastlock mode bit is 1, fastlock mode 2 is selected.

Quick Lock Mode 1

The charge pump current switches to the contents of current setting 2. The device enters fastlock by writing a 1 to the CP gain bit in the AB counter latch. The device exits FASTLIKE by writing the CP gain bit of 0 in the AB counter latch.

Quick Lock Mode 2

The charge pump current switches to the contents of current setting 2.

The device enters fastlock by writing a 1 to the CP gain bit in the AB counter latch. The device exits FASTROCK under the control of the timer counter. After a timeout determined by the value in TC4:TC1, the CP gain bit in the AB counter latch is automatically reset to 0 and the device reverts to normal mode instead of fastlock. The timeout period is shown in Figure 18.

Timer Counter Control

The user can choose to program two charge pump currents. The purpose is to use current setting 1 when the RF output is stable and the system is static. Current setting 2 is used when the system is dynamic and in a changing state (ie, when a new output frequency is programmed).

The normal sequence of events is as follows:

The user first decides what the preferred charge pump current is. For example, select 2.5 mA for current setting 1 and 5 mA for current setting 2.

At the same time, the time that the secondary current remains active must be determined before returning to the primary current. This is controlled by the timer counter control bits DB14:DB11 (TC4:TC1) in the function latch. The truth table is shown in Figure 18.

Now, to program a new output frequency, the user simply programs the AB counter latch with the new a and B values. At the same time, the CP gain bit can be set to 1, which will set the charge pump with the value in CPI6:CPI4 for a period determined by TC4:TC1. When this time expires, the charge pump current returns to the value set by CPI3:CPI1. At the same time, the CP gain bit in the AB counter latch is reset to 0 and is now ready for the next time the user wishes to change the frequency. Note that there is an enable function on the timer counter. It is enabled when Fastlock Mode 2 is selected by setting the Fastlock Mode bit (DB10) in the function latch to 1.

charge pump current

CPI3, CPI2, and CPI1 set 1 for the charge pump programming current. CPI6, CPI5 and CPI4 are charge pump programming current setting 2.

Prescaler value

P2 and P1 in the function latch set the prescaler value. The prescaler value should be chosen so that the prescaler output frequency is always less than or equal to 300 MHz. So with an RF frequency of 4ghz, a prescaler value of 16/17 is valid, but a value of 8/9 is not.

Partial discharge polarity

This bit sets the phase detector polarity bit.

CP tri-state

This bit controls the CP output pin. When the bit is set high, the CP output will go into three states. When the bit is set low, the CP output is enabled.

initialization latch

Latch programming is initialized when C2 and C1 are set to 1 and 1. This is basically the same as a functional latch (programmed when C2, C1 = 1, 0).

However, when the initialization latch is programmed, additional internal reset pulses are applied to the R and AB counters. When the AB counter data is locked, this pulse ensures that the AB counter is at the load point and the device will start counting in near phase alignment.

If the latch is programmed for synchronous power down (CE pin high; PD1 bit high; PD2 bit low), an internal pulse will also trigger this power down. The prescaler reference and oscillator input buffers are not affected by the internal reset pulse, thus maintaining tight phase alignment when counting resumes.

When the first AB counter data is locked after initialization, the internal reset pulse is activated again. However, successive AB counter loads thereafter will not trigger an internal reset pulse.

Device programming after initial power-up There are three ways to program the device after the device is initially powered up.

1. Apply VDD.

2. Program the initialization latch (11/2 LSB of the input word). Make sure the F1 bit is programmed to 0.

3. Next, perform a function latch load (10/2 lsb of the control word), making sure the F1 bit is programmed to 0.

4. Then do an R load (00/2 LSB).

5. Then do AB loading (1/2 LSB).

When the initialization latch is loaded, the following happens:

1. Load function latch content.

2. An internal pulse resets the R, AB and timeout counters to the load state condition and resets the charge pump to three states. Note that the prescaler bandgap reference and oscillator input buffer are not affected by the internal reset pulse, allowing close phase alignment when counting resumes.

3. The initialization word activates the same internal reset pulse to lock the first AB counter data. Continuous AB loading will not trigger an internal reset pulse unless there is another initialization.

CE-Pin method

1. Apply VDD.

2. Turn CE down to power down the device. This is an asynchronous power outage because it happens immediately.

3. Program the function latch (10).

4. Program the R counter latch (00).

5. Program the AB counter latch (01).

6. Turn up CE to power off the equipment. The R and AB counters will now resume counting in a tightly aligned manner.

Note that a 1µs duration may be required after CE goes high for the prescaler bandgap voltage and oscillator input buffer bias to stabilize.

CE can be used to drive the device up and down to check for channel activity. As long as the input registers are programmed at least once after the initial application of V, they do not need to be reprogrammed each time the device is disabled and enabled. due diligence

Counter reset method

1. Apply VDD.

2. Perform functional latch loading (10 inches 2 LSB). As part of this operation, 1 is loaded into the F1 bit. This will enable the counter reset.

3. Perform R reverse loading (00/2 LSB).

4. Perform AB reverse loading (1/2 LSB).

5. Perform function latch loading (10 inches 2 LSB). As part of this operation, 0 is loaded into the F1 bit. This will disable the counter reset. This sequence provides the same tight alignment as the initialization method. It provides direct control over internal reset. Note that a counter reset keeps the counter at the point of load and puts the charge pump in three states, but does not trigger a synchronous power down.

Power Considerations

The ADF4108 operates from a 3.2 V to 3.6 V supply range. The ADP3300ART-3.3 is a low loss linear regulator from Analog Devices. It outputs 3.3 V with 1.4% accuracy and is recommended for use with the ADF4108.

interface

The ADF4108 has a simple SPI compatible serial interface for writing data to the device. CLK, DATA and LE control data transfer. When LE (latch enable) goes high, the 24 bits that have entered the input register on each rising edge of CLK are transferred to the appropriate latch. The timing diagram is shown in Figure 2, and the latch truth table is shown in Table 5.

The maximum allowable serial clock rate is 20 MHz. This means the device has a maximum update rate of 833 kHz or every 1.2 seconds. This is certainly more than enough for a system with typical lock times in the hundreds of microseconds.

ADUC812 interface

Figure 20 shows the interface between the ADF4108 and the ADuC812 MicroConverter®. Since the ADuC812 is based on the 8051 core, this interface can be used with any 8051 based microcontroller. MicroConverter is set to SPI master mode, CPHA=0. To initiate operation, the I/O port driver LE will go low. Each latch of the ADF4108 requires a 24-bit word. This is accomplished by writing three 8-bit bytes from the microconverter to the device. When the third byte is written, the LE input should be brought high to complete the transfer.

When the ADF4108 is first powered up, four writes (one each for the initialization latch, function latch, R counter latch, and N counter latch) are required to make the output active.

The I/O port lines on the ADuC812 are also used to control power down (CE input) and detect lock (MUXOUT is configured for lock detect and polled by the port input).

When operating in the described mode, the maximum burst rate of the ADuC812 is 4 MHz. This means that the maximum rate at which the output frequency can be changed is 166 kHz.

ADSP-21xx interface

Figure 21 shows the interface between the ADF4108 and the ADSP-21xx digital signal processors. The ADF4108 requires a 24-bit serial word for each latch write. The easiest way to do this with the ADSP-21xx family is to use the auto-buffered transfer mode of operation with spare frames. This provides a way to transfer the entire block of serial data before generating an interrupt. Set the word length for 8 bits and use three memory locations for each 24-bit word. To program each 24-bit latch, store three 8-bit bytes, enable autobuffer mode, and write to the DSP's transmit register. The last operation starts an automatic buffered transfer.

Chip Scale Packaging Board Design Guidelines

The solder ring on the chip scale package (CP-20-6) is rectangular. The length of the printed circuit board pad should be 0.1 mm longer than the length of the packaging tape and the width should be 0.05 mm wider than the width of the packaging tape. The land should be centered on the mat. This ensures maximum solder joint size. The bottom of the chip scale package has a central thermal pad.

The thermal pad on the PCB should be at least as large as this exposed pad. On a printed circuit board, there should be at least a 0.25 mm gap between the thermal pad and the inner edge of the pad pattern. This avoids short circuits.

Thermal vias can be used on printed circuit board thermal pads to improve the thermal performance of the package. If vias are used, they should be incorporated into thermal pads at the 1.2 mm pitch grid. The through hole diameter should be between 0.3 mm and 0.33 mm, and the through hole barrel should be plated with 1 oz copper to insert the through hole. The user should connect the PCB thermal pad to AGND.