Function

Programmable Output Turn-On Delay, Adaptive Delay Set, Bidirectional Oscillator Synchronization, Voltage Mode or Current Mode Control Capability, Programmable Soft Start/Soft Stop, Chip Disable via Single Pin, 0% to 100 % Duty Cycle Control, 7MHz Error amplifier, running to 1MHz
, low active current consumption (typically 5mA at 500kHz)
, the extremely low current consumption during undervoltage lockout (150A typical) illustrates that the UCC3895 is a phase-shifted PWM controller that phase-shifts the switching of one half-bridge with respect to the other half-bridge to achieve full-bridge power stage control. It allows constant frequency pulse width modulation to be combined with resonant zero voltage switching, providing high efficiency at high frequencies. This part can be used as both a voltage mode controller and a current mode controller.
While the UCC3895 maintains the functionality of the UC3875/6/7/8 series and UC3879, it improves this controller family with additional features such as enhanced control logic, adaptive delay settings and shutdown capabilities. Because it's built in BCDMOS, it draws much less supply current than its bipolar counterparts. The UCC3895 can operate with a maximum clock frequency of 1MHz.
The UCC3895 and UCC2895 are available in 20-pin SOIC (DW), 20-pin PDIP (N), 20-pin TSSOP (PW), and 20-pin PLCC (Q) packages. The UCC1895 is available in a 20-pin CDIP (J) package and a 20-pin CLCC (L) package.

Pin Description AD: Adaptive Delay Set. This function sets the ratio between the maximum and minimum programmed output delay deadband. When the ADS pin is directly connected to the CS pin, no delay modulation occurs. Maximum delay modulation occurs when ADS is grounded. In this case, when CS=0, the delay time is 4 times as long as when CS=2.0V (peak current threshold), ADS changes the output voltage on the delay pins DELAB and DELCD by the following formula:
VDEL=[0.75 8226 ;(VCS-VADS)]+0.5V
where VCS and VAD are in volts. ADS must be limited between 0V and 2.5V and must be less than or equal to CS. DELAB and DELCD will also be clamped to a minimum of 0.5V.
Out: Error amplifier output. It is also internally connected to the non-inverting inputs of the PWM comparator and no-load comparator. EAOUT is internally fixed at the soft-start voltage. The no-load comparator turns off the output stage when EAOUT is below 500mV and allows the output to turn on again when EAOUT is above 600mV.
Computed Tomography: Oscillator Timing Capacitors. (Refer to Figure 1, Oscillator Block Diagram) The oscillator of the UCC3895 charges the CT with the programming current. The waveform on CT is sawtooth, the peak voltage is 2.35V, and the approximate oscillator period is calculated by the following formula:
5•RT•CT
tOSC = +120 ns where CT is in farads, RT is in ohms, and tOSC is in seconds. CT can be from 100pF to 880pF. Note that the combination of a large CT and a small RT will result in a prolonged fall time of the CT waveform. The increased fall time will increase the sync pulse width, thereby limiting the maximum phase shift between the outputs of OUTA, OUTB and OUTC, OUDD, which limits the maximum duty cycle of the converter.
Counter-Strike: How It Feels Now. This is the inverting input of the current sense comparator and the non-inverting input of the overcurrent comparator, as well as the ADS amplifier. The current sense signal is used for cycle-by-cycle current limiting in peak current mode control, and overcurrent protection in all cases with output shutdown secondary thresholds. An output disabling caused by an overcurrent fault can also cause a restart cycle, called a "soft stop," a full soft start.
Dlaib, Dreyer: Delay programming between complementary outputs. DELAB programs the dead time between OUTA and OUTB switching, and DELCD programs the dead time between OUTC and OUTD. This delay is introduced between complementary outputs in the same segment of the external bridge. The UCC3895 allows the user to select the delay during which resonant switching of the external power stage occurs. Provide separate delays for the two half-bridges to accommodate differences in the resonant capacitor charging current. The delay for each stage is set according to the following formula:
(25 10•-12)•RDEL
t delay = +25 ns
VDEL, where VDEL is in volts, RDEL is in ohms, and tDELAY is in seconds. DelAB and DelCD can reach a maximum value of 1 Ma. Choose the delay resistor so that this maximum value is not exceeded. The programmable output delay can be eliminated by connecting DELAB and/or DELCD to REF. For best performance, keep stray capacitance on these pins <10pF.
Ground: Chip ground for all circuits except the output stage.
Outlet A, Outlet B, Outlet C, Outlet D: These 4 outputs are 100mA complementary MOS drivers and are optimized to drive the FET driver circuit. OUTA and OUTB are fully complementary (assuming no programming delay). They operate at nearly 50% duty cycle and half the oscillation frequency. OUTA and OUTB are used to drive the half-bridge circuit in the external power stage. OUTC and OUTD will drive the other half bridge and have the same characteristics as OUTA and OUTB. OUTC is phase-shifted with respect to OUTA, and OUTD is phase-shifted with respect to OUTB. Note that changing the phase relationship of OUTC and OUTD with respect to OUTA and OUTB requires the addition of the nominal 50% duty cycle of OUTC and OUTD during these transients.
PGND: Page output stage ground. To preserve output switching noise for critical analog circuits, the UCC3895 has two distinct ground connections. PGND is the ground connection for the high current output stage. GND and PGND must be connected tightly together near the IC. Also, since PGND has high current, the board traces must be low impedance.
Pin Description (continued)
Ramp: Inverting input to the PWM comparator. This pin receives the CT waveform under voltage and average current mode control, or the current signal (plus slope compensation) under peak current mode control. The internal discharge transistor is set on the ramp to trigger during oscillator dead time.
Room temperature: oscillator timing resistor. (Refer to Figure 1, Oscillator Block Diagram) The oscillator in the UCC3895 operates by charging an external timing capacitor CT with a fixed current programmed by RT. The RT current is calculated as follows:
In 3.0 volts, RT is in ohms and IRT is in amps. RT can start from 40kt to 120kSoft charge and discharge current is also programmed by IRT.
SS/Disable: Soft start/disable. This pin combines two independent functions.
: Fast shutdown of the chip can be done by either: externally forcing SS/DISB below 0.5V, externally forcing REF below 4V, VDD falling below the UNLO threshold, or detecting an overcurrent fault (CS=2.5V).
SS/DISB is actively pulled to ground through an internal MOSFET switch when REF is pulled below 4V or under UVLO conditions. If overcurrent is detected,
SS/DISB will sink (10•IRT) current until SS/DISB drops below 0.5V.
Note that if SS/DISB is forced below 0.5V externally, the pin will begin to source current equal to IRT. Also note that the only time the part switches to low IDD current mode is when the part is in undervoltage lockout.
application information

After a fault or disable condition is passed, VDD is above the start-up threshold, and/or the SS/DISB is below 0.5V during soft-stop, the SS/DISB will switch to soft-start mode. The pin will now generate current equal to IRT. A user-selected capacitor on SS/DISB determines the soft-start (and soft-start) time. Additionally, a resistor in parallel with the capacitor can be used to limit the maximum voltage on SS/DISB. Note that SS/DISB will actively clamp the EAOUT pin voltage to the SS/DISB pin voltage during soft-start, soft-stop, and disable conditions.
Sync: Oscillator sync. This pin is bidirectional. When used as an output, SYNC can be used as a clock, which is the same as the chip's internal clock. When used as an input, SYNC will override the chip's internal oscillator and act as its clock signal. This bidirectional capability allows multiple power supplies to be synchronized. The sync signal will also internally discharge the CT capacitors and any filter capacitors on the ramp pins. The internal synchronization circuit is level sensitive, with an input low threshold of 1.9V and an input high threshold of 2.1V. A resistor as small as 3.9k can be connected between sync and GND to reduce the sync pulse width.

Referee: 5V, 1.2% reference voltage. The reference powers internal circuitry and can also supply up to 5 mA to external loads. The voltage reference is turned off during undervoltage lockout, but is operational in all other disabled modes. For best performance, bypass with a 0.1F low ESR, low ESL capacitor to ground.
Application Information (continued)
The Adaptive Delay Set Feature (ADS) allows the user to vary the delay time between switching commands in each of the converter's two branches. Delay time modulation is accomplished by connecting ADS (pin 11) to CS, GND, or a resistive divider from CS to GND to set VAD. From the VDEL equation above, if ADS is tied to GND, then VDEL increases proportionally to VCS, resulting in a decrease in tDELAY as the load increases. In this case, the maximum value of VDEL is 2V. If ADS is connected to a resistive divider between CS and GND, (VCS-VDS) becomes smaller, reducing the level of VDEL. This will reduce the amount of delay modulation. Under the limit of ADS connected to CS, VDEL=0.5V, no delay modulation occurs. In the case of maximum delay modulation (ADS=GND), the change in VDEL is from 0.5V to 2V when the circuit goes from light to heavy load, which results in a 4:1 change in delay time with load change.

The ability to program an adaptive delay is a desirable feature because the optimal delay time is a function of the current in the primary winding of the transformer and can vary by a factor of 10:1 or more as the circuit load changes. Reference [1] explores the many relevant factors used to select the optimal delay time for the most efficient power conversion, and describes the use of the UC3879 to enable an external circuit for adaptive delay sets. The implementation of this adaptive feature is simplified in the UCC3895 controller, allowing the user to tune the delay time to suit a specific application with minimal external components

circuit description

circuit description