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Internal Synchronous PFC and PWM in an 8-Pin IC Patented Single-Pin Voltage Error Amplifier with Advanced Input Current Shaping Technology Peak or Average Current, Continuous Boost, Leading Edge Input Current Shaping Technology High Efficiency Trailing Edge Current Mode PWM Low Supply Current; Startup: 150µA (typ), Run: 2mA Typ. Synchronized leading and trailing edge modulation reduces ripple current in storage capacitor PFC and PWM sections Overvoltage, UV and power-off protection PFC VCCOVP with PFC soft start

General Instructions

4803 -ic/" title="FAN4803 Product Specifications, Documentation and Sourcing Information" target="_blank">FAN4803 is a space saving power factor controller corrected switching power supply with low starting and operating current. Power factor correction ( PFC) provides smaller, lower cost bulk capacitors, reduces power line loading and stress switch FETs, and produces a power supply that is fully compliant with IEC1000-3-2 specifications. Fan 4803 includes circuit current "boost" for leading edge average Type PFC and trailing edge, PWM. Simultaneous PFC and PWM operating frequency for fan 4803-1, 67kHz. Power factor correction frequency for fan 4803-2 is automatically set to half of 134kHz PWM. This higher frequency allows the user to use Smaller PWM component PFC frequency to maintain optimal operation. Overvoltage comparator is turned off if loaded. Power factor correction section also includes peak current limit for enhanced system reliability.

Functional description: The Fan 4803 consists of an average current mode boost to form a power factor corrector (PFC) front end followed by a synchronous pulse width modulation (PWM) controller. It is different from earlier combi controllers for its low pin count, innovative input current shaping technology, and low start-up and run current. The PWM section is dedicated to peak current mode operation. It uses conventional trailing edge modulation, while PFC uses leading edge modulation. This patented leading/trailing edge modulation technique helps reduce ripple current in the PFC DC bus capacitors. There are two versions of the FAN4803. The FAN4803-1 operates both the PFC and PWM sections at 67kHz, while the FAN4803-2 operates the PWM section at twice the power factor correction frequency (134kHz). This allows the use of smaller pulse width modulation (PWM) magnetics and output filter components while minimizing switching losses in the PFC stage. In addition to power factor correction, the FAN4803 has some built-in protections. These include soft-start, redundant PFC overvoltage protection, peak current limit, duty cycle limit and undervoltage lockout (UV). A typical application is shown in Figure 12. Detailed Pin Description This pin provides a feedback path that forces the PFC output to adjust to the programmed value. It is connected to a programming resistor connected to the PFC output voltage shunted by the feedback compensation network. This pin is connected to a resistor or a current sense transformer to sense the PFC input current. This signal should be negative with respect to IC ground. It internally provides pulse current limit comparator and current sensing feedback signal. The ILIMIT trip level is -1V. The ISENSE feedback is internally multiplied by a gain of 4 and compared against the internally programmed ramp to set the power factor correction duty cycle loop. The intersection of the boost inductor current and the downslope with the internally programmed ramp determine the startup turn-off time. DC This pin is usually connected to the feedback light harvester. It is connected to the internal 5V reference through a 26kΩ resistor and to ground through a 40kΩ resistor.

ILIMITE This pin is connected to a primary side PWM current sense resistor or transformer. It provides an internal PWM stage for current limiting (occurring at 1.5V) and a peak current mode feedback path for current mode control of the PWM stage. The current ramp is internally offset by 1.2V and then compared to the optical feedback to set the voltage for the PWM duty cycle. PFC output and PWM output The PFC output and PWM output are high current power drivers capable of directly driving the gate of power MOSFETs with peak currents up to ±1A. Both outputs are effectively held low when VCC is below the UVLO threshold. VCC Inc. VCC is the IC's power input connection. The VCC startup current is 150µA. The no-load ICC current is 2mA. The VCC company quiescent current will include IC bias current as well as PFC and PWM output current. Taking into account the operating frequency and MOSFET gate charge (Qg), the average power factor correction and PWM output current can be calculated as output current = Qg x F. Any must also include the gate drive transformer. The VCC pin is also assumed to be proportional to the PFC output voltage. Internally connected to the VCCOVP comparator (16.2V) to provide redundant high-speed overvoltage protection (OVP) during the PFC stage. VCC also works with the UVLO circuit, which enables the IC at 12V and disables it at 9.1V. VCC must bypass high quality ceramic bypass capacitors as close to the IC as possible. Good bypass for fan 4803. VCC is usually provided by a boost inductor or PFC choke, which provides a voltage proportional to the PFC output voltage. Because the VCCOVP maximum voltage is 16.2V, an internal shunt limits the VCC overvoltage to an acceptable value. External clips as shown are desirable but not required.

VCC is internally clamped to 16.7V minimum and 18.3V maximum. This limits the maximum VCC that can be applied. IC simultaneously allows a sufficiently high VCCVCCOVP. The maximum current through this zener is 10mA. An external series resistor is required to limit if the VCC voltage exceeds the Zener clamp.

Ground GND is related to this part. NOTE: A high-quality, low-impedance ground is critical to the proper operation of the integrated circuit. Grounding techniques should be used for high frequencies. Power Factor Correction Power factor correction makes a non-linear load look like a resistive load on an AC line. For resistors, the current starts from the line in sync with the line and is proportional to the voltage. This is defined as a unity power factor of (1). A common class of non-linear loads is the maximum power input supply, which is fed from the line using a bridge rectifier and capacitive input filter. The peak charging effect, which occurs with the input filter capacitors in such power supplies, causes the current to flow from the power line to briefly generate high-amplitude pulses rather than sinusoidal currents that are in phase with the line voltage. Such a power supply is another term for the current harmonics present at its input). If the input current through this supply (or any other non-linear load) can track the input voltage with an instantaneous magnitude, it has resistance to the AC line and unity power factor will be achieved. To keep the input current draw of the device pulling power from the AC line voltage in phase and proportional to the input, a way must be found to prevent loading the line, except for the voltage proportional to the instantaneous line. The PFC part of the FAN4803 uses a boostmode DC-DC converter to achieve this. The input to the frequency converter is full wave rectified AC line voltage. No filtering is applied after the bridge rectifier, so the voltage range of the input boost converter, twice the line frequency, goes from zero volts to the peak of the AC input and back to zero. By forcing the boost converter to meet both conditions, it ensures that the voltage the converter draws from the power line matches the instantaneous line voltage. One of the conditions is that the output voltage of the boost converter must be set higher than the peak value of the line voltage. A common value is 385VDC, which allows 270VACRMS of high voltage lines. The other condition is that the current allowed by the converter at any given moment must be proportional to the line voltage drawn from the straight line. Because the boost converter topology in the FAN4803 PFC is in the current averaging type, no slope compensation is required.

Lead/Track Modulation Traditional Pulse Width Modulation (PWM) techniques employ trailing edge modulation where the switch will turn right after the trailing edge of the system clock. Then compare the error amplifier output voltage with the modulation ramp. When the modulation ramp reaches the level of the error amplifier output voltage, the switch will close. When the switch is turned on, the inductor current will intensify. The effective duty cycle of the trailing edge modulation is determined when the switch is turned on. Figure 2 shows a typical trailing edge control scheme.

In the case of leading edge modulation, the switch rotation is on the leading edge of the system clock. When the modulation ramp reaches the horizontal output voltage of the error amplifier, the switch will turn on. Effectively determines the duty cycle of the leading edge modulation during the switch off period. Figure 3 shows a leading edge control scheme. One of the advantages of this control technique is that only one system clock is required. Switch 1 (SW1) turns off and Switch 2 (SW2) turns on at the same instant in order to minimize the instantaneous "no-load" time, thereby reducing the voltage produced by the ripple switching action. With such synchronous switching, the ripple voltage of the first stage is reduced. Calculations and evaluations show that the 120Hz component of the power factor corrected output ripple voltage can be reduced by as much as 30% using this method, substantially reducing losses in high voltage PFC capacitors. Typical application of the single pin error amplifier fan 4803 in the PFC section (VEAO). The error amplifier is actually a current sink, forcing 35 microamps through the output programming resistor. The nominal voltage of the VEAO pin is 5V. For the 11.3MΩ resistor, the VEAO voltage range is 4 to 6V chain to the boost output voltage and 5V steady state VEAO, the boost output voltage is 400 volts.

Programming Resistor Value Equation 1 calculates the required programming resistor value.

The PFC voltage loop compensation voltage loop bandwidth must be set to less than 120Hz to limit the amount of line current harmonic distortion. A typical crossover frequency is 30Hz. Equation 1, for simplicity, assumes that the polar capacitance dominates the error amplifier gain at the loop unity-gain frequency. Equation 2 places the pole at the crossover frequency, providing 45 degrees of phase margin. The location of Equation 3 a decade before the North Pole. Display overall gain and phase as shown. Figure shows a simplified model of the voltage loop.

Internal Voltage Ramp The internal ramp current source programs the VEAO pin voltage in the following way. The graph shows the internal ramp current versus voltage. This current source is used to charge the internal 30pF+12, forming the internal ramp/–10% capacitance. See Figures 10 and 11. The frequency of the internally programmed ramp is internally set to 67kHz. PFC Current Sense Filtering In DCM, input current drain may be caused by fan 4803. In order for this technique to operate properly in DCM, the programming ramp must meet the boost inductor current drop at zero amps. Assuming that the programming ramp is zero at light load, the off-time terminates when the inductor current reaches zero.

The PFC gate driver is then activated, eliminating the necessary dead time required for DCM mode. This powers up until the VCC OVP turns off. This condition is corrected by adding a bias voltage to the current sense signal, forcing the duty cycle to zero at light loads. This offset prevents the PFC from working in DCM and forces the pulse to jump from CCM to noduty, thus avoiding DMC operation. External filtering of the current sense signal helps to smooth the sense signal, slightly extending the operating range to the DCM range, but this should be done with care as this filtering reduces the bandwidth of the pulse signal by limiting the signal by the pulse current. The figure shows a typical circuit for adding offset to ISENSE at light loads. PFC Start-up and Soft-Start During steady-state operation, the VEAO sinks 35 µA at startup and receives this current The internal current mirror is destroyed until VCC reaches 12V. This forces the PFC to incorrectly voltage VCC when the IC is enabled. A modulated VCC on the VEAO pin with leading edge at the power factor corrected output. When selecting external compensation components and VCC supply circuits, VEAO must not be prevented from reaching the 6V sequence before VCC powers up to 12V. This will guarantee that the PFC phase will enter a soft start. Once VCC reaches 12V, the 35µA VEAO current sink is enabled. The veal compensation component is discharged through a 35µA current sink until a steady state operating point is reached. See Fig. PFC soft recovery after VCC-OVP The FAN4803 assumes that VCC is generated from the source code which is proportional to the power factor corrected output voltage. Once that power supply voltage reaches 16.2V the VEAO pin is disabled in the same sequence as the soft start switch. Once disabled, the VEAO pin charges up the way external components, until the PFC duty cycle returns to zero, disabling the PFC.

VCC OVP resets a VCC discharge below 16.2V, allowing the VEAO current to purge and drain the VEAO compensation components until the steady state operating point is reached. It should be noted that once the VEAO pin exceeds 6.5V as shown, the internal ramp is disabled. Therefore, an external Zener can be installed to reduce the maximum voltage. In the off state, the VEAO pin may rise. Clamping the VEAO pin externally to 7.4V will reduce the value of the time it takes the VEAO pin to return to steady state. UV radiation Once VCC reaches 12V, both PFC and PWM will be enabled. The UVLO threshold is 9.1V with a hysteresis of 2.9V. Generates an internal VCC clamp to limit VCC overvoltage. This clip circuit ensures that the fan 4803's VCC OVP circuit will function properly when out of tolerance and temperature to protect the component from voltage transients. This circuit allows the fan 4803 to have both a PWM output and a power factor corrected output, sufficient to drive low cost IGBTs. The current through the zener must be limited to avoid overheating or destruction. This can be done with a resistor in series with the VCC pin, returning to the bias supply typically 14V to 18V. Resistor values must be chosen to meet the operating current requirements of the FAN4803 itself (4.0mA max) plus the current driver outputs required for both gates.