feature

Serial digital interface; 28-pin SSOP; E1, T1 and MDSL operation; 64kbps to 1168kbps operation; scalable data rates; 250 mW power consumption; full HDSL analog interface; +5V power supply (5V or 3.3V digital).

illustrate

The size and cost of an XDSL is greatly reduced by providing all the analog circuits required to connect to a digital signal processor for all active analog circuits. External Compromise Hybrid Line Transformer Optimized for High Bit Rate DSLs and for Low Speed MDSL ("Medium Speed DSL") and Adaptive Rate DSL applications Because the transmit and receive filter responses automatically change the clock frequency, the AFE1124 is particularly suitable for RADSL and multi-rate DSL systems. The device operates with a wide range of data rates from 64kbps to 1168kbps. Functionally, this unit consists of a transmitter and a stealth section to generate an analog signal from the transmit section of 2-bit digital symbol data and filter the analog signal to create a 2B1Q symbol The on-board differential line driver provides a 13.5dbm signal to the telephone line stealth section The symbol data line on the filter digital reception phone is supplied by this IC operating unit 5V. The unit's digital circuitry can be connected to one supply from 3.3v to 5v. The unit is in a 28-PIN SSOP package.

theory of operation

AFE1124 consists of transmit and receive channels. It interfaces with the HDSL-DSP through a six-wire serial interface, three-wire transmit channel and three-wire receive channel. It interfaces with HDSL phone line transformers and external compromises by sending and receiving analog connections.

The transmission channel consists of a switched capacitor pulse forming network and a differential line driver. The pulse forming network receives 2-bit digital symbol data and produces a filtered 2B1Q analog output waveform. Differential line drivers use a combined output stage that combines Class B operation (for driving large signals efficiently) with Class AB operation (for minimizing crossover distortion).

The receive channel is designed around a fourth-order delta-sigma A/D converter. It includes a differential amplifier designed for external compromise mixing of first-order analog echo cancellation. Also includes a programmable gain amplifier with a gain of 0dB to +12dB. A delta-sigma modulator operating at a 24x oversampling rate produces a 14-bit output at rates up to 584kHz (1.168Mbps).

The receive channel works by adding two differential inputs, one from the line (rxLINE) and the other from the compromise hybrid (rxHYB). The connection of these two inputs is described in the paragraph titled "Echo Cancellation in AFE" in order to subtract the mixed signal from the line signal. The equivalent gain of each input in a differential amplifier is 1. The resulting signal is then passed to a programmable gain amplifier that can be set from 0dB to +12dB of gain. After the PGA, the ADC converts the signal into a 14-bit digital word.

The serial interface consists of three transmit lines and three receive lines. The three-wire transmission interface is the transmission baud rate clock, the transmission 48x oversampling clock and the data output. The three-wire receiving interface is to receive the baud rate clock, receive 48x oversampling clock and data input. The transmit and receive clocks are provided to the AFE1124 by the DSP and are completely independent.

digital data interface

Data is received from the DSP on the data line by the AFE1124. Data is transferred from the AFE1124 to the DSP on the data output line. The following paragraphs describe the timing and data structure of these signals.

Data is transmitted and received in synchronization with the 48x transmit and receive clocks (tx48xCLK and rx48xCLK). There are 48 bit times per baud rate cycle. Data input is received on the first 16 bits of each baud period. The remaining 32-bit cycles are not used for data in. The data output is transmitted in the first 16 bits of the baud period. The second interpolated value is transmitted in subsequent bits of the baud period.

txbaudCLK: The baud rate of the transmitted data generated by the digital signal processor. T1 is 392kHz and E1 is 584kHz. It may vary from 32kHz (64kbps) to 584kHz (1.168Mbps).

tx48xCLK family: transmit pulse generator oversampling clock generated by digital signal processor. The transmission symbol rate is 48 times, and the 584kHz symbol rate is 28.032MHz. The clock should run continuously.

Data Input: This is the 16-bit output data word sent from the DSP to the AFE. The 16 bits include the tx sign information and other control bits as described below. Data should be clocked from the DSP on the falling edge and valid on the rising edge of tx48xCLK. The AFE1124 reads data on the rising edge of tx48xCLK. Bits are defined in Table I. Data is read by the AFE1124 during the first 16 bits of each baud rate cycle. Only the first 8 bits are used in AFE1124. The second 8 bits are reserved for use in future products. The remaining 32-bit periods of the baud rate period are not used for data input.

Data Bits: tx enable signal - This bit controls the tx sign definition bits. If this bit is 0, only the 0 symbol is sent regardless of the state of the tx symbol definition bit. If this bit is 1, the tx sign definition bit determines the output sign. tx Symbol Definition - These two bits determine the output 2B1Q symbol sent.

Receive Gain Setting - These bits set the gain of the receive channel programmable gain amplifier.

Loopback Control - This bit controls the loopback operation. When enabled (logic 1), the rxLINE+ and rxLINE- inputs are disconnected from the AFE. The rxHYB+ and rxHYB- inputs remain connected. When disabled, connect the rxLINE+ and rxLINE– inputs.

Thromboxane - This bit controls the output line driver to add 0.5dB of extra power.

rxbaudCLK: This is the received data baud rate (symbol clock) generated by the DSP. T1 is 392kHz and E1 is 584kHz. It can vary from 32kHz (64kbps) to 584kHz (1.168Mbps).

Type rx48xCLK: This is the A/D converter on the sampling clock generated by the digital signal processor. The received symbol rate is 48 times, and the 584kHz symbol rate is 28.032MHz. The clock should run continuously.

Data Out: This is the 14-bit A/D converter output data (+2 spare bits) sent from the AFE to the DSP. The 14 bits of the A/D converter will be the high order bits of the 16-bit word (bits 15-2). The spare bits (1 and 0) will always be low. This is followed by eight extra (internal data) bits, which are always high. Data is clocked on the falling edge of rx48xCLK. The bandwidth of the A/D converter decimation filter is equal to half the symbol rate. The nominal output rate of the A/D converter is one conversion per symbol period. For more flexible post-processing, there is a second interpolating A/D conversion in each symbol period. In Figure 4, the first transition is shown as data 1 and the second transition is shown as data 1a. It is recommended to use rxbaudCLK with rx48xCLK to read data 1 and ignore data 1a. However, either or both outputs can be used for more flexible post-processing.

A/D Converter Data

The A/D converter data from the receive channel is encoded in two's complement.

Echo Cancellation in AFE

The rxHYB input is subtracted from the rxLINE input for first order echo cancellation. For proper operation, make sure that the rxLINE input is connected to the same polarity signal of the transformer (+ to + and - to -), while the rxHYB input is connected to the opposite polarity.

Scalable timing

The AFE1124 scales operation according to the clock frequency. All internal filters and pulse generators change frequency with clock speed so that they can be used at different frequencies simply by changing the clock speed.

For the receive channel, the digital filtering of the delta-sigma converter scales directly with the clock speed. The bandwidth of the converter decimation filter is always half the symbol rate. The only receive channel issue when changing baud rates is the passive single-pole anti-aliasing filter (see next section). For systems that achieve a wide speed range, the optional cutoff frequency of the passive antialiasing filter should be used.

For transmission channels, the pulse shape and power spectral density are proportional to the clock frequency. The power spectral density shown in curve 1 and the pulse template shown in curve 2 are measured at the transformer output. The transformer and RC circuit at the output provide some smoothness to the output transmission. At lower bitrates, the amount of smoothing will be smaller.

RXHYB and RXLINE input anti-aliasing filters

As shown in the basic connection diagram above, the Mixed Inputs and Line Inputs require an external input antialiasing filter. For RXLIN and RXHYB differential inputs, the 3dB frequency of the input antialiasing filter should be approximately 1MHz for T1 and E1 symbol rates. Recommended filter values for the two input resistors are 750 Ω and 100 pF for the capacitor. The two 750Ω resistors and 100pF capacitor together produce a 3dB frequency just above 1MHz. The 750Ω input resistance will minimize the divider losses of the input impedance of the AFE1124.

The anti-aliasing filter will get the best performance at a 3dB frequency approximately equal to the bit rate. For example, a 3dB frequency of 320kHz can be used for a single wire bit rate of 320kbits per second.

normative discussion

echo not canceled

A key metric for measuring transceiver performance is non-cancelling echoes. Unechoed is the sum of all errors in the transmit and receive paths of the AFE1124. It includes the effects of linearity, distortion and noise. Uncancelled echo was tested in production by Burr Brown with a circuit similar to the uncancelled test diagram shown in Figure 7.

Measurements without echo cancellation are as follows.

The AFE is connected to an output circuit including a typical 1:2 line transformer. The lines are simulated by 135Ω resistors. The symbol sequence is generated by the tester and applied to the input of the AFE and adaptive filter. The output of the adaptive filter is subtracted from the AFE output to form the undeleted echo signal. Once the filter taps have converged, the RMS value of the uncancelled echo is calculated. Since there is no far-end source or additional line noise, the uncancelled echoes only contain noise and linearity errors generated in the transmit and receive sections of the AFE1124.

The datasheet value for Uncanceled Echo is the ratio of the RMS Uncanceled Echo (referring to the receiver input through the receiver gain) to the nominal transmitted signal (13.5dBm into 135Ω or 1.74Vrms). This echo value was measured under various conditions: loopback enabled (line input open); loopback disabled in all receiver gain ranges; and line shorted (S1 closed in Figure 7).

Power consumption

About 80% of the power dissipation in the AFE1124 is in the analog circuit, and this component does not vary with clock frequency. However, the power consumption in digital circuits does decrease as the clock frequency decreases. Also, the power consumption of the digital part is reduced when operating at a smaller supply voltage (eg 3.3V) (the analog supply AVDD must be kept in the range of 4.75V to 5.25V).

The power consumption listed in the Specifications section applies to the following normal operating conditions: 5V analog supply; 3.3V digital supply; standard 13.5dBm delivered to the line; and pseudorandom equal probability HDSL output pulse train. Power dissipation specifications include all power dissipated in the AFE1124, excluding power dissipated in external loads. The external power supply is 16.5dBm: 13.5dBm to the line, 13.5dBm to the impedance matching resistor. The external load power of 16.5dBm is 45mW. The typical power consumption of the AFE1124 under various conditions is shown in Table 2.

The T1 and E1 power measurements in the specification were made using the output circuit shown in Figure 7. This circuit uses a 1:2 transformer. The power measurements shown in Table 2 use an equivalent resistive load in place of the transformer to remove the frequency-dependent impedance of the transformer.

layout

The analog front end of an HDSL system has two conflicting requirements. It must receive and transmit moderate to high rate digital signals and must generate, drive and convert accurate analog signals. In order to use the AFE1124 to achieve the best system performance, both the digital part and the analog part must be handled carefully in the circuit board layout design.

The power supply range for the digital part of the AFE1124 is 3.3V to 5V. This supply should be separated from digital ground and use ceramic 0.1µF capacitors as close to DGND and DVD as possible. One capacitor should be placed between pins 3 and 4 and the second capacitor should be placed between pins 11 and 12. Ideally, both the digital power plane and the digital ground plane should be connected above and below the digital pins (pins 5 to 10) of the AFE1124. However, DVDDs can be provided by wide printed circuit board (PCB) traces. A digital ground plane is strongly recommended under all digital pins.

The rest of the AFE1124 should be considered analog. All AGND pins should be connected directly to a common analog ground plane, and all AVDD pins should be connected to an analog 5V power plane. Both planes should have a low impedance power path. The analog power pins should be separated from the analog ground and the ceramic 0.1µF capacitors should be placed as close to the AFE1124 as possible. A 10µF tantalum capacitor should also be used for each AFE1124 between analog supply and analog ground.

Ideally, all ground planes and traces and all power planes and traces should return to the power connector before connecting them together (if necessary). Each ground and power wire should be routed against each other, should not overlap any part of the other wire pair, and should be at least 0.25 inches (6mm) apart. One exception is that the digital and analog ground planes should be connected under the AFE1104 via a small trace.