illustrate
The WM8766 is a multi-channel audio DAC ideal for DVD and surround sound processing applications in home hi-fi, automotive and other AV equipment.
Three stereo 24-bit multi-bit sigma-delta DACs are used with oversampled digital interpolation filters. Digital audio input word lengths from 16-32 bits and sample rates from 8kHz to 192kHz are supported. Each DAC channel has independent digital volume and mute controls. The audio data interface supports I2S, left justified, right justified and digital audio formats. The device is controlled via a 3-wire serial interface or directly using the hardware interface. These interfaces provide access to functions including channel selection, volume control, mute, de-emphasis and power management facilities. The device provides 28-pin SSOP.
Features, 6-Channel DAC, Audio Performance – -103dB SNR ('A' Weighted @48kHz) DAC, DAC Sampling Frequency: 8kHz – 192kHz, 3-Wire SPI Serial or Hardware Control Interface, Programmable Audio Data Interface Mode –-I 2S , left, right justified or DSP - 16/20/24/32-bit word length, three independent stereo DAC outputs with independent digital volume controls, master or slave audio data interface, 2.7V to 5.5V analog , 2.7V to 3.6V digital power supply operation, 28-pin SSOP package applications, DVD players, surround sound AV processors and hi-fi systems, car audio

Absolute Maximum Ratings are for stress ratings only. Permanent damage to equipment may result from continuous operation at or beyond these limits. Under the specified test conditions, the functional operating limits and guaranteed performance specifications of the equipment under the electrical characteristics are given.
Electrostatic discharge sensitive devices. The device is fabricated using a CMOS process. Therefore, it is generally susceptible to damage by excessive static voltages. Proper ESD precautions must be taken when handling and storing this equipment.
Wolfson tests the moisture sensitivity of its packaging types according to IPC/JEDEC J-STD-020B to determine acceptable storage conditions prior to surface mount assembly. These levels are:
MSL1 = infinite floor life at <30°C/85% relative humidity. Usually not stored in moisture-proof bags. MSL2 = 1 year storage outside the bag at <30°C/60% relative humidity. A moisture-proof bag is provided. MSL3 = 168 hours out of bag at <30°C/60% relative humidity. A moisture-proof bag is provided.

Note: 1. The ratio of the output level of a 1kHz full-scale input to the output level of all zeros in the digital input, measured "A" weighted. 2. All performance measurements were done with a 20kHz low-pass filter, and if noted, an A-weight filter. Failure to use this filter will result in higher THD+N, lower SNR and dynamic range readings than in the electrical characteristics. A low-pass filter removes out-of-band noise; although inaudible, it may affect dynamic specification values. three. VMID is separated with 10uF and 0.1uF capacitors (smaller values may result in lower performance).
term 1. Signal-to-Noise Ratio (dB) - Signal-to-noise ratio is a measure of the difference in level between the full-scale output and the output with no signal. (Do not use auto-zero or auto-mute to achieve these results). 2. Dynamic Range (dB) - DNR is the difference between the highest and lowest parts of the measured signal. Typically THD+N is measured 60dB below full scale. It is then corrected by adding 60dB to the measurement signal. (eg THD+N@-60dB=-32dB, DR=92dB). three. THD+N (dB) - THD+N is the ratio of (noise + distortion)/rms value of the signal. Four. Stop Band Attenuation (dB) - is the degree of spectral attenuation (out of the audio band). 5. Channel Separation (dB) - Also known as Crosstalk. This is a measure of the isolation of one channel from another. Usually measured by sending a full-scale signal to one channel and measuring the other channel. 6. Passband Ripple - Any change in frequency response in the passband region.

Introduction to Device Description
The WM8766 is a complete 6-channel DAC including digital interpolation and decimation filters and switched capacitor multi-bit sigma-delta DACs with digital volume controls and output smoothing filters on each channel.
The unit is implemented as 3 independent stereo DACs in a single package and controlled by a single interface.
Each stereo DAC has its own data input DIN1/2/3. The DAC word clock LRCLK, the DAC bit clock BCLK, and the DAC master clock MCLK are shared among them.
The audio interface can be configured to work in master or slave mode. In slave mode, both LRCLK and BCLK are inputs. In master mode, both LRCLK and BCLK are outputs.
Each DAC has its own digital volume control that can be adjusted in 0.5dB steps. Digital volume control can be operated independently. In addition, a zero-crossing detection circuit is provided for each DAC for digital volume control. The digital volume control detects a transition through zero before updating the volume. This minimizes audible clicks and "zipper" noise as the gain value changes.
Control the internal functions of the device via a 3-wire serial or pin programmable control interface. The software control interface can be asynchronous to the audio data interface because the control data will be resynchronized internally with the audio processing.
Provides the DAC with operation using a master clock of 128fs, 192fs, 256fs, 384fs, 512fs, or 768fs. In slave mode, the selection between clock rates is automatically controlled. In master mode, the sample rate is set by the control bit data rate. The DAC allows audio sample rates (fs) from less than 8ks/s to 192ks/s if an appropriate master clock is input. The audio data interface supports right, left and I2S interface formats, and has a highly flexible DSP serial port interface.
Audio Data Sampling Rate In a typical digital audio system, only one central clock source generates a reference clock to which all audio data processing is synchronized. This clock is often referred to as the master clock of the audio system. The external main system clock can be applied directly through the DAC MCLK input pin without software configuration.
The WM8766's DAC master clock supports audio sampling rates from 128fs to 768fs, where fs is the audio sampling frequency (LRCLK), typically 32kHz, 44.1kHz, 48kHz, 96kHz, or 192kHz. The master clock is used to operate the digital filters and noise shaping circuits.
In slave mode, the WM8766 has a master clock detection circuit that automatically determines the relationship between the system clock frequency and the sampling rate (within the range of plus or minus 32 master clocks). If there are greater than 32 clock errors, the interface defaults to 768fs mode. The WM8766 is tolerant of phase variation or jitter on the master clock. Table 5 shows the typical master clock frequency input for the WM8766.
The signal processing of the WM8766 typically operates at an oversampling rate of 128fs. The exception is for operation with a 128/192fs system clock when the oversampling rate is 64fs, e.g. for 192kHz operation.

Audio interface format audio data is applied to the internal DAC filter through the digital audio interface. 5 popular interface formats are supported:
All 5 formats send MSB first and support word lengths of 16, 20, 24 and 32 bits, but not 32 bit right justified mode. In left-justified, right-justified, and I2S modes, the digital audio interface receives DAC data through the DIN1/2/3 inputs. The audio data for each stereo channel is time multiplexed with LRCLK, which indicates whether the left or right channel is present. LRCLK is also used as a timing reference to indicate the start or end of a data word. In left-justified, right-justified, and I2S modes, the minimum number of bclks per LRCLK cycle is 2 times the selected word length. LRCLK must be high for minimum word length BCLKs and low for minimum word length BCLKs. Any mark-to-space ratio on LRCLK is acceptable as long as the above requirements are met.
In DSP early or DSP late mode, all 6 DAC channels are time multiplexed onto DIN1. LRCLK is used as a frame sync signal to identify the MSB of the first word. The minimum number of bclks per LRCLK cycle is 6 times the selected word length. Any mark-to-space ratio on LRCLK is acceptable as long as the rising edge is positioned correctly.
Left-Justified Mode In left-justified mode, the WM8766 samples the MSB of DIN1/2/3 on the first rising edge of BCLK after LRCLK transitions. LRCLK is high for left sampling, LRCLK is low for right sampling

Recommended Analog Low-Pass Post-DAC Filters - Low-pass filters are recommended to be applied to the output of each DAC channel for high-fidelity applications. Typically, a second-order filter is appropriate and provides adequate attenuation of high-frequency components (the unique low-order, high-bit-count, multi-bit sigma-delta DAC architecture used in the WM8766 produces higher frequencies than ordinary sigma-delta DACs much less noise at the output). This filter is also typically used to provide the required 2x gain to provide the standard 2Vrms output level of most user equipment.
Figure 28 shows a suitable post-DAC filter circuit with a gain of 2. Alternative inverse filter structures can also be used with good results.