feature

256 Kbit Ferroelectric Random Access Memory (F-RAM) logically organized as 32k x 8 High Endurance 100 Trillion (1014) Read/Write 151 Year Data Retention Period (see Data Retention and Endurance Table) NoDelay 8482 ; Write Advanced High reliability ferroelectric process compatible with SRAM and EEPROM Industry standard 32 K×8 SRAM and EEPROM pins 70 ns access time, 130 ns cycle time better than battery-backed SRAM modules No battery issues Monolithic reliability True surface mount Mounting solution with no rework steps Suitable for moisture, shock and vibration Negative voltage overshoot resistance Temperature: –40°C to +85°C? ? 28-pin Small Outline Integrated Circuit (SOIC) package compliant with Restriction of Hazardous Substances (RoHS)

Function description

The FM18W08 is a 32K×8 non-volatile memory that can read and write similar to standard SRAM. Ferroelectric random number access memory, or F-RAM, is non-volatile, which means that data is retained after a power outage. It has been battery-backed SRAM (BBRAM) for 151 years while eliminating reliability issues, functional flaws and system design complexity. Fast write timing and high write endurance make F-RAM superior to other types of memory. The FM18W08 operates similarly to other RAM devices so it can act as a standard SRAM in the system. The minimum read and write cycle times are equal. Due to the uniqueness of F-RAM memory, it is a non-volatile ferroelectric memory process. These features make the FM18W08 ideal for frequent or fast writing. The device is available in a 28-pin SOIC surface mount package. Device specifications are guaranteed industrially over a temperature range of -40°C to +85°C.

Device Operation: The FM18W08 is a byte-range F-RAM memory that is logically organized as 32768×8 and uses an industry standard parallel access interface. All data written to the part is immediately lost without hesitation. The functional operation of the F-RAM memory is the same as that of the SRAM type device, but the FM18W08 requires the falling edge of CE to start each memory cycle. See Functional Truth Table, page 13, for a complete description of read and write modes. Memory Structure The user accesses 32768 memory locations, each with 8 data bits through a parallel interface. The full 15-bit address uniquely specifies each of the 8192 bytes. The F-RAM array is organized into 4092 rows of 8 bytes each. This row segmentation has no effect on the operation, but the user can group the data into the endurance characteristics of the block, such as the endurance section. The cycle times for reading and writing memory are the same operations. This simplifies the memory controller logic and timing circuits. Likewise, the access times for reads and writes are the same as memory operations. The precharge operation begins when CE is de-high voltage, and is required for each memory cycle. So unlike SRAM, access and cycle times are not equal. Writes happen immediately at the end of the access, with no delay. Unlike an EEPROM, there is no need to poll the device for readiness since the write occurred at bus speed. It is the user's responsibility to ensure that VDD remains within the data sheet tolerances that prevent erroneous operation. It is also suitable that the voltage level and timing relationship between VDD and CE must be maintained during power-up and power-down events. See "Power Cycle Timing" on page 12.

Memory Operation The FM18W08 is designed in the same way as other byte memory products. For the familiar user BBSRAM, the performance is comparable, but the byte-range interface operates slightly differently, as described below. For users familiar with EEPROM, the difference is higher write performance from F-RAM technology including NoDelay writing and higher writing endurance. READ OPERATIONS A read operation begins with the falling edge of CE. At this time, the address bits are latched and a memory cycle is initiated. Once booted, a full memory cycle must be completed internally even if the CE fails. Data is available on the bus after the access time. After the address is locked, the address value can be changed when the hold time parameter is met. Unlike SRAM, changing the address value locks the address after the memory operation. When OE is asserted low, the FM18W08 will drive the data bus and meet the memory access time. If the memory access time is met, the data bus will be driv data. If OE is asserted before the memory access is complete, the data bus will not be driven until valid data is available. This feature works by eliminating transients caused by invalid data driven to the bus. when? OE is de-configured high and the data bus will remain in the HI-Z state.

Write operation In the FM18W08, the interval between writing and reading is the same. The FM18W08 supports both CE and WE controlled write cycles. In both cases, the address is locked on the falling edge of CE. In a CE-controlled write operation, the WE signal starts a memory cycle. That is, when the device is activated when the chip is enabled. In this case, the device starts the memory cycle with a write. The inability of the FM18W08 to drive the data bus has nothing to do with the state of operating experience. In the write we control, the memory cycle is from the edge of CE. The WE signal falls after the CE falling edge. Therefore, a store cycle begins with a read. The data bus will drive based on operating experience until we fall. The timing of writes to the Chief Executive and our control is shown on page 12. A write access to the array starts a memory loop. Write accesses are on the rising edge of US or CE, whichever comes first. Effective handwriting operations require users to meet access time specifications before we or the Chief Executive leave. The data setup time is indicated during write access.

Unlike other non-volatile memory technologies, it has no write latency to F-RAM. Because the underlying memory is the same, the user experience does not experience a delay on the bus. The entire memory operation happens in a single bus cycle. Therefore, any operation including a read or write can occur immediately after a write. Data polling, a used with eeprom to determine if a write operation is complete, is unnecessary. Precharge Operation A precharge operation is an internal condition where the memory state is ready for a new access. All memory cycles include memory access and precharge. Precharge is initiated by the user by driving the CE signal high. It must be left high for at least the minimum precharge time, tPC. The user determines the start of this operation because precharge will not start until CE is raised. However, the device has a maximum CE low time specification that must be met. Endurance Internally, F-RAM operates through a read and restore mechanism. Therefore, each read and write cycle contains a country change. The memory structure is based on an array of rows and columns. Every read or write access results in an entire row of endurance cycles. In FM18W08, a line is 64 a bit wide. Every 8-byte boundary marks a new row. By frequently ensuring that the data being accessed is in a different row. Regardless, F-RAM offers higher write-persistence memories than other non-volatiles. The rated endurance limit of 1014 cycles would allow 150,000 accesses to the same row per second for over 20 years.

F-RAM Design Considerations When designing with F-RAM for the first time, SRAM users will recognize some subtle differences. First, byte-range F-RAM memory is latched at every address on the falling edge of chip enable. This allows the address bus to change in after starting the memory. Because every access is locked to the edge of the CE, the user can't ground SRAM like it does with it. Users modifying existing designs to use F RAM should check the memory controller for timing compatibility with address and control pins. Every memory access must be qualified with low CE content. In many cases this is all that needs to be changed. An example of a signal relationship is shown in the figure below. Also shown is a relationship where a common SRAM signal does not apply to the FM18W08. The CE is gated for each address for two reasons: it latches the new address and creates the necessary precharge period when CE is high.

The second design consideration is operation. Battery powered SRAMs are forced to monitor VDD in order to switch to battery backup. They typically prevent user access below a certain VDD level to prevent the current demands of loading the active SRAM battery. Users can abruptly interrupt access to non-volatile memory without warning or indication of a power outage condition. F-RAM memory does not require this overhead. This memory will not block access to any VDD level that meets the specified operating range. The user should take action when VDD is too high. It may be sufficient to hold the processor in a reset state during a shutdown. It is recommended to pull the chip enable high and allow VDD to be tracked during power up and power down cycles. It is the user's responsibility to ensure that the chip enable prevents accesses below the VDD minimum (2.7 V). The diagram shows a pull-up resistor on CE that will keep the pin high during power cycling, assuming the MCU/MPU pin is tri-stated in a reset condition. The pull-up resistor value should be chosen to ensure that the CE pin trace VDD is high enough, so the current drawn when CE is low is an issue.

Note that if CE is tied to ground, the user must ensure that we are not low during a power-up or power-down event. If the chip is enabled and we are low during the energy cycle, the data will be corrupted. The diagram shows a pull-up resistor on WE that will keep the pin high during power cycling, assuming the MCU/MPU pin is tri-stated in a reset condition. The pull-up resistor value should be chosen to ensure that we lock the track VDD to a high enough value, so the current drawn when we're low is an issue.