feature

Serial digital data link requires few I/O pins; analog input track/hold capability; 4- or 8-channel input multiplexer options with address logic; on-chip 2.5V bandgap reference (±2%+ guaranteed temperature); no zero-scale or full-scale adjustment required; TTL/CMOS input/output compatible; 0V to 5V analog input range with single 5V supply.

Main Specifications

Resolution 8 bits; conversion time (fC=1MHz) 8µs (max); power consumption 20mW (max); single supply 5 VDC (±5%) n Total unadjusted error ±1/2 LSB and ± 1 LSB; Linearity Error (VREF=2.5V) ±1/2 LSB; No Missing Code (Over Temperature); On-Board Reference Voltage +2.5V ±1.5% (max).

application

Digital automotive sensors; process control/monitoring; remote sensing in noisy environments; embedded diagnostics.

General description

The ADC08131 /Series A/O is configured to mate with the NSC Microwire Serial Data Exchange standard to facilitate interfacing with process family of controllers that can easily interface standard porting registers or microprocessors. All three devices provide 2.5V band Gap source reference temperature guarantees performance. A track/hold function causes the analog voltage to enter Vary during the actual conversion process. The analog inputs can be configured to operate in various single-ended, differential, or combined pseudo-differential modes. Additionally, a small 1V input voltage can be adjusted.

Function description

The multiplexer addressing modes can also select polarity. Channel 0 may be that these converters are designed with a comparator structure and built-in sample-and-hold to provide a different input or vice versa. This programmability is best illustrated by analog inputs, converted with a continuous analog program. Various product options. Select as positive input, channel 1 is negative The MUX addressing code shown in the table below actually converts the voltages are always poor - the MUX address is transferred into the converter via the DI line. Between the designated "+" input terminal and "-" input terminal. The polarity of each pair of input terminals represents the most positive line expected by the converter. If-because the ADC08131 contains only one differential input channel with fixed polarity assignment, it doesn't need to be addressing.

A signed "+" input voltage is less than the "-" input voltage on the common input line (COM) on the ADC08138 can respond with an all-zero output code. Used as pseudo-differential input. In this mode, a unique input multiplexing scheme has been used to support any other input that this pin is considered an "other" input to VIDE multiple analog channels with software configurable single-ended, differential, or pseudo-differential ( This translates the difference between any analog input voltages. This feature is most useful in single-supply applications and common terminal) operation. Using this type of input flex, analog signal options can be greatly simplified, where analog circuits can be biased to the desired potential conditions in sensor-based data acquisition systems-channels. This voltage does not have to be analog ground; it can be all signals except ground and the potential of the output signal.

A converter package can now handle ground-referenced and true differential inputs and signals Table 1. Multiplexer/package option with arbitrary voltage reference.

A specific input configuration is assigned during the MUX addressing sequence before starting a conversion. The MUX address selects which analog input to enable, and whether that input is single-ended or differential. Differential inputs are limited to adjacent channel pairs. For example, channel 0 and channel 1 may be selected as a differential pair, but channel 0 or channel 1 cannot act differentially with any other channel. In addition to selecting the differential, the first logical '1' that appears on this line can be modified as desired before each transition, since the input configuration is software controlled. channel (ignore all leading zeros). After the start bit, it can be treated as a single-ended, ground-referenced input converter expecting the next 2 to 4 bits to be a converted MUX; this can then be reconfigured as part of the signed word.

Another converted differential channel. Figure 1 Inset-3. Input flexibility is achieved when the start bit has been shifted to the start position. In the MUX register, the input channels - the analog input voltage for each channel can be signed and the conversion is about to start. A gap of 50 mV below ground to 50 mV above VCC (typically 5V) is automatically inserted (with -/2 clock period) to allow sampling to reduce conversion accuracy. Lock the analog input. At the end of this time, the SARS line will go high, indicating that a conversion is in progress, and the DI line is disabled (it no longer accepts 1 data. One of the most important features of these converters is the serial data with the control processor. Link. Use Sequence 4. The Data Out (DO) line is now in tri-state communication format, providing two very important system im- and providing leading zeros.

provents; it allows at 5. During the conversion process, the output of the SAR comparator small package can eliminate the transmission of low-level signals by positioning the converter on a series of continuous voltage general-purpose analog sensors, indicating whether the analog input is greater than the (high) level analog signal; Internally transfers high noise immune digital data from the rated capacitor array (first 5 bits) and resistor ladder (last 3 bits). Back to the host processor after each comparison.

To understand the operation of these converters, it is best to route the output of the comparator to the DO line on the timing diagram and functional block diagram of the falling edge of the reference clock. This data is the result of Converland following the complete transformation sequence. For clarity, a version is shown for each device that is shifted out (MSB first) and can be a separate timing diagram. The processor reads immediately.

1. Initiate conversion by pulling CS (chip select) 6. After 8 clock cycles, the conversion is complete. Line is low. This line must be held low so that the entire convert-SARS line returns low to indicate subsequent /2 clock cycles. The converter is now waiting for the start bit and its MUX assignment word.

2. On each rising edge of the clock (DI) line is recorded into the MUX address shift register. The start bit is the first logical "1" that appears on the line (all leading zeros are ignored). After the start bit the converter expects the next 2 to 4 bits to be the MUX assignment word.

3. When the start shift is moved to the start position in the MUX register, the input channel has been allocated and the conversion is about to start. Intervals are automatically inserted into 1/2 clock cycle for sampling the analog input. The SARS line ends during this time, indicating that the conversion is in progress and the DI line is disabled (it no longer accepts data).

4. The Data Out (DO) line is now out of tri-state and provides leading zeros.

5. During conversion, the output of the SAR comparator indicates whether the analog input is greater (high) or less than (low) a series of continuous voltages (first 5 bits) and a resistive ladder (last 3 bits) generated inside the rated capacitor array. The output of the comparator is sent to the falling edge of CLK after each comparison. This data is the result of the conversion (MSB first) and can be read immediately by the processor.

6. After 8 clock cycles, the conversion is complete. The SARS line returns low to represent 1/2 the clock cycle.

7. The stored data in the successive approximation register is loaded into the internal shift register. If the programmer wants the data to be available in LSB-first format [this makes use of the Shift Enable (SE) control line]. Turn on ADC08138 SE line pinout, if held high LSB value remains valid on DO line. When SE is forcibly lowered, data is clocked by LSB first. On devices that do not include SE control lines, the LSB takes precedence and the MSB flows first. The DO line then goes low and remains low until CS returns high. The ADC08131 is an exception because its data is output only in MSB first format.

8. When the CS line is high, all internal registers are cleared to meet the t selection requirements. See "Data Input Timing" under "Timing Diagram". If another transition is required, CS must do a high-to-low transition followed by the address information. The DI and DO lines can be tied together and controlled via a single line of bidirectional processor I/O bits. This is possible because the DI input is only "seeing" when the DO line is still in a high impedance state.

reference factor

The VRIFIN pin on these converters is on top of the resistor divider string and capacitor array used for successive approximation transformations. The voltage applied to this reference input defines the voltage range of the analog input (the difference between VIN (max) and VIN (min) for which the 256 possible output codes apply). The reference source must be able to drive the reference input resistance, which can be as low as 1.3 kΩ.

For absolute accuracy, the reference input must be biased with a stable voltage source when the analog input varies between specific voltage limits. The ADC08134 and ADC08138 provide the output of a 2.5V bandgap reference at VREFOUT. This voltage does not vary widely over temperature, supply voltage, or load current (see Reference Characteristics in the Electrical Characteristics table), can be connected directly to VREFIN, and has an analog input range of 0V to 2.5V. This output can also be used to bias external circuits, so it can be used as a reference in ratiometric measurement applications. A 100µF capacitor is recommended to bypass VREFOUT.

For the ADC08131, the output of the onboard reference is connected internally to the reference input. Therefore, the analog input range of the device is set to 0V to 2.5V. Pin VREFC is provided for bypassing and biasing the above external circuits. The maximum reference value is limited to the VCC supply voltage. However, the minimum value may be the di-sensitivity of the allowed converter (1LSB equals VREF/256) due to small (see Typical Performance Characteristics) when operating at reduced span. Provides rectangular conversion of sensor outputs with less than 5V output range.

analog input

The most important feature of these converters is that they can be located at the analog signal source and communicate with a control processor with a high noise immunity serial bit stream over only a few wires. This in itself greatly reduces the circuitry to maintain the accuracy of analog signals that are otherwise most susceptible to noise pickup. However, for analog inputs, if the input is noisy at the beginning, or possibly on a large common-mode voltage, there are several words in sequence.

The differential inputs of these converters actually reduce the effects of common-mode input noise, which is a signal that is common to both the selected "+" and "-" inputs for one converter (60 Hertz is the most typical). The time interval between sampling the "+" input and the "-" input is /2 of the clock period. During this short time interval, changes in the common-mode voltage can cause conversion errors. For a sinusoidal common-mode signal, this error is:

where fCM is the frequency of the common-mode signal, VPEAK is its peak voltage value, and fCLK is the A/D clock frequency.

For a 60Hz common-mode signal to produce an LSB error of 4 (5 mV), the converter operating at 250kHz must peak at 663V, which would be more than allowed because it exceeds the maximum analog input limit. 1

The source resistance limit is important for the DC leakage current into the multiplexer. Bypass capacitors should not be used if the source resistance is greater than 1K at near or maximum speed operation. Worst-case leakage current over temperature of ±1µA will result in a 1mV input error with a 1kΩ source resistance. If a high-impedance signal source is required, an op amp RC active low-pass filter can provide impedance buffering and noise filtering.

optional adjustment

zero error

The zero point of the A/D does not need to be adjusted. Zero offset is possible if the minimum analog input voltage value VIN(MIN) is not grounded. By biasing any VIN (negative) input at that VIN (min) value, the converter can output a 0000 0000 numeric code for this min input voltage. This takes advantage of the differential mode operation of the A/D.

The zero error of the A/D converter is related to the position of the first riser of the transfer function and can be measured by grounding the VIN (-) input and applying a small positive voltage to the VIN (VIN) input. Zero error is simply the difference between the actual DC input voltage and the ideal /2 LSB value (/2 LSB) required to convert the output digital code from 0000 to 0000 0001 = 11; 9.8mV at VREF = 5.000VDC).

full scale

A full-scale adjustment can be made by applying a differential input voltage (1/2 LSB down from the desired analog full-scale voltage range), then adjusting the VREFIN input magnitude of the digital output code just changed from 1111 1110 to 1111 1111 (see heading Figure for "Range Adjustment; 0V≤VIN≤3V"). This is only possible on the ADC08134 and ADC08138. (Refer to VREFIN connected internally to ADC08131).

Adjustment of any analog input voltage range

If the A/D's analog zero voltage is moved away from ground (for example, to accommodate an ungrounded analog input signal), the new zero reference should first be adjusted properly. Apply a VIN (+) voltage equal to the desired zero reference voltage plus /2 LSB (where 1 LSB=analog span/256 is used to calculate the LSB of the desired analog span) to the selected "+" input, The zero reference voltage at the corresponding "-" input should then be adjusted to obtain a code transition of 00HEX to 01HEX. 1

A voltage shall be applied to the VIN (-) input [with the appropriate VIN (-) voltage applied], given by:

Where: VMAX=high end of analog input range; VMIN=low end of analog range (offset zero). (Both are ground referenced.) The VREFIN (or VCC) voltage is then adjusted to provide a code change from FEHEX to FFHEX This completes the adjustment process.