feature

Built-in sample and hold; single +5V supply; 1, 2, or 4 input multiplexer options; no external clock required; speed adjustment pins for fast conversions ( ADC10462 and ADC10464).

Main Specifications

Time to convert to 10 bits, 600 ns typical; 800 kHz sampling rate; low power consumption 235MW (max); total harmonic distortion (50 kHz) –60 dB (max); no over-temperature missing codes.

application

Digital signal processor front end; instrumentation; disk drives; mobile communications.

General Instructions

Using innovative, patented multi-step* conversion technology, the 10-bit ADC10461, ADC10462, and ADC10464 provide sub-microsecond CMOS analog-to-digital converter conversion times that still dissipate a maximum of only 235 megawatts. The ADC10461, ADC10462, and ADC10464 perform 10-bit conversions in two low-resolution "flashes", thus eliminating the cost, power, and other concerns associated with true flash methods. Dynamic performance (THD, S/N) is guaranteed. This ADC10461 is pin-compatible with the ADC1061, but faster, hence the ADC1061.

ADC10461, ADC10462 and ADC10464 sample and hold circuit by internal sampling. Input signals from DC to frequencies above 200 kHz Therefore, no external sample-and-hold circuit is required. The ADC10462 and ADC10464 include a "speed up" pin. Connecting an external resistor from this pin to ground adds only a little bit of linearity error. To facilitate interfacing with the microprocessor ADC10461, the ADC10462 and ADC10464 are designed as memory locations or I/O ports without the need for external interface logic.

Function description

The ADC10461, ADC10462, and ADC10464 digitize the analog input signal to 10-bit precision by performing two low-resolution "flash" conversions. The first flash conversion provides the 6 most significant bits (msb) and the second flash conversion provides the 4 least significant bits lsb.

Figure 3 is a simplified block diagram of the converter. There is a string of resistors near the center of the diagram. There are 16 resistors at the bottom of the resistor string, each with a value of 1/1024 of the resistance of the entire string. So the voltage drop across these lower 16 resistors (LSB ladder) is 16/1024 or 1/64 of the total reference voltage (VREF+-VREF-). The rest of the resistor string consists of eight sets of eight resistors in series. They make up the MSB ladder diagram.

Each section of the MSB ladder diagram has /8 of its total reference voltage, and each LSB resistor has 1/64 of its total reference voltage. The tap points on these resistors can be connected in groups of 16 to the 16 comparators on the right side of the diagram.

On the left side of the diagram are seven resistor strings connected between VREF+ and VREF-. Six comparators compare the input voltage to the tap voltage on this resistor string to provide a low-resolution "estimate" of the input voltage. This estimate is then used to control the multiplexer that connects the MSB ladder to the 16 comparators on the right. Note that the comparators on the left do not have to be very accurate; they just provide an estimate of the input voltage. Only the 16 comparators on the right and 6 on the left are required to perform the initial 6-bit flash conversion, instead of the 64 comparators required with the traditional half-flash approach.

To convert, the estimator compares the input voltage to the tap voltage across the seven resistors on the left. The estimator decoder then determines which MSB trapezoidal tap points will be connected to the 16 comparators on the right. For example, suppose the estimator determines that VIN is between 11/16 and 13/16 of VREF. The Estimator Decoder will instruct the Comparator MUX to connect the 16 comparators to taps on the MSB ladder between 10/16 and 14/16 of VREF. The 16 comparators will then perform the first flash conversion. Note that since the comparator is connected to a step voltage beyond the range indicated by the estimator circuit, the error in the estimator will be corrected by 1/16 of the reference voltage (64 lsb). The first flash conversion produces the 6 most significant data bits - 4 for the flash itself and 2 for the estimator.

The remaining four lsbs are now determined using the same sixteen comparators as the first flash transition. The MSB ladder tap voltage just below the input voltage (determined by the first flash) is subtracted from the input voltage and compared to the tap points on the 16 LSB ladder resistors. Then, the results of the second and fourth flash conversions are decoded and the complete 10-bit result is locked.

Note that the 16 comparators used in the first flash conversion are reused for the second flash. Therefore, the multi-step conversion technique used in the ADC10461, ADC10462, and ADC10464 requires only a fraction of the number of comparators required by conventional flash converters, and far less than the number of comparators used in conventional half-flash methods. This allows the ADC10461, ADC10462, and ADC10464 to perform high-speed conversions without excessive power consumption.

application information

1.0 Operation Mode

The ADC10461, ADC10462 and ADC10464 have two basic digital interface modes. Figures 1 and 2 are timing diagrams for these two modes. The ADC10462 and ADC10464 have input multiplexers controlled by logic levels on pins S0 and S1 when S/H goes low. Tables 1 and 2 are truth tables showing how to assign input channels.

Mode 1

In this mode, the S/H pin controls the start of a conversion.

S/H is pulled low for at least 250 ns. This causes the comparator in the "rough" flash converter to become ac-active. When S/H goes high, the result of the coarse conversion is latched and a "fine" conversion begins. After 600 ns (typ), INT goes low, indicating that the conversion result is locked and can be read by pulling RD low. Note that CS must be low to enable S/H or RD. CS is internally "ANDed" with S/H and RD; the input voltage is sampled when CS and S/H are low, and the data is read when CS and RD are low. On the rising edge of RD, INT is reset to high.

Mode 2

In Mode 2 (also known as "RD Mode"), the S/H and RD pins are tied together. Conversions are initiated by pulling both pins low. The A/D converter samples the input voltage and activates the coarse comparator. Then an internal timer terminates the coarse conversion and starts the fine conversion. 850 ns (typ) after S/H and RD is pulled low, INT goes low, indicating that the conversion is complete. After approximately 20 nanoseconds, the data appearing on the tri-state output pins will be valid. Note that data will be present on these pins during the conversion process, but the data at the output pins until INT goes low will be the result of the previous conversion.

2.0 Reference Factors

The ADC10461, ADC10462, and ADC10464 each have two reference inputs. These inputs, VREF+ and VREF-, are fully differential and define the zero to full scale range of the input signal. For ratiometric measurement applications, the reference inputs can be connected to the entire supply voltage range (VREF-=0V, VREF+=VCC), or when other input ranges are required, they can be connected to different voltages (as long as they are between ground and VCC) . Reducing the overall VREF range to less than 5V increases the sensitivity of the converter (eg, 1LSB=1.953mV if VREF=2V). However, please note that when

Use a lower reference voltage. See Typical Performance Curves for details. Therefore, it is not recommended that the reference voltage be less than 2V.

In most applications, VREF- will simply be connected to ground, but it is often useful to have an input span offset from ground. The reference configurations used in the ADC10461, ADC10462 and ADC10464 are easily adapted to this situation. VREF- can be connected to a voltage other than ground as long as the voltage source connected to this pin is capable of sinking the converter's reference current (12.5 mA max at VREF=5V). If VREF- is connected to a voltage other than ground, bypass it with multiple capacitors.

Since the resistance between the two reference inputs can be as low as 400 Ω, the voltage source driving the reference inputs should have low output impedance. Any noise on either reference input can cause conversion errors, so clean, low-noise voltage sources must be provided for these pins. Each reference pin should be bypassed with 10µF tantalum and 0.1µF ceramic.

3.0 Analog Input

The ADC10461, ADC10462, and ADC10464 sample the analog input voltage once per conversion cycle. When this happens, the input is briefly connected to an impedance approximately equal to 600µm, in series with 35 PFs.

Therefore, during normal operation, short-duration current spikes can be observed at the analog input. These spikes are normal and do not degrade the performance of the converter.

A large source impedance will slow down the charging speed of the sampling capacitor and reduce conversion accuracy. Therefore, use a signal source with output impedance less than 500 Ω only when the rated accuracy is achieved at the minimum sampling time (250 ns maximum). The longer the sampling time, the higher the source impedance. If the signal source has high output impedance, its output should be buffered with an op amp. The output of the op amp should perform well when driving a switching load of 35 pF/600Ω. Any ringing or voltage offset at the op amp output during sampling can cause conversion errors.

Correct conversion results will be obtained when the input voltage is greater than GND-50 mV and less than V++50 mV. Signal sources are not allowed to drive analog input pins more than 300 mV above AVCC and DVCC or 300 mV below GND. If the analog input pins are forced to exceed these voltages, the current flowing through the pins should be limited to 5mA or less to avoid permanent damage to the IC. The sum of all overdrive currents into all pins must be less than 20mA. When the input signal exceeds the power supply limit by more than 300mV, some kind of protection scheme should be used. A simple network using diodes and resistors is shown in Figure 4.

Figure 4. Typical connection. Note the multiple bypass capacitors on the reference and supply pins. If VREF- is not grounded, it should also be bypassed to analog ground with multiple capacitors (see 5.0" Power Supply Considerations). AGND and DGND should be at the same potential. VIN0 is shown with the input protection network. Pin 17 is normally open, But an optional "speed up" resistor RSA can be used to reduce conversion time.

4.0 Inherent Sample and Hold

Because the ADC10461, ADC10462, and ADC10464 sample the input signal once during each conversion, they are able to measure relatively fast input signals without resorting to external sample and hold. In non-sampling successive approximation A/D converters, regardless of speed, the input signal must settle to ±1/2 LSB in each conversion cycle, otherwise significant errors will occur. Therefore, even for many relatively slow input signals, if a SAR is used without internal sample and hold, the signal must be sampled externally and held constant during each conversion.

Because they contain direct sample/hold control inputs, the ADC10461, ADC10462, and ADC10464 are suitable for use in DSP-based systems. The S/H input allows sampling rates for A/D converters and DSP systems and other ADC10461s, ADC10462s and ADC10464s.

The ADC10461, ADC10462, and ADC10464 can perform accurate conversion of frequency components from DC to input signals above 250 kHz.

5.0 Power Considerations

The ADC10461, ADC10462, and ADC10464 are designed to operate from a +5V (nominal) supply. There are two power pins, AVCC and DVCC. These pins allow the use of separate external bypass capacitors for the analog and digital portions of the circuit. To ensure accurate conversion, both power pins should be connected to the same voltage source, and each pin should be bypassed with a 0.1µF ceramic capacitor and a 10µF tantalum capacitor in parallel. Depending on board layout and other system considerations, additional bypassing may be required.

The ADC10461 has a ground pin, and the ADC10462 and ADC10464 each have separate analog and digital ground pins for bypassing the analog and digital supplies separately. The ground pins of devices with separate analog and digital ground pins should be connected to the same potential and all grounds should be "clean" and free of noise.

In systems with multiple power supplies, careful attention to power sequencing may be required to avoid entering too fast. The power supply pins of the A/D converter should be at the proper voltage before applying digital or analog signals to any other pins.

6.0 Layout and Grounding

To ensure fast and accurate conversions from the ADC10461, ADC10462, and ADC10464, proper board layout techniques must be used. The analog ground return should be low impedance and free from noise from other parts of the system. Noise in digital circuits is particularly troublesome, so the digital ground should always be separated from the analog ground. For best performance, separate ground planes should be provided for the digital and analog parts of the system.

All bypass capacitors should be as close as possible to the converter and should be connected to the converter and shorted to ground. The analog input should be isolated from noisy signal traces to avoid spurious signal coupling into the input. Any external components connected to the input of the converter (such as filter capacitors) should be connected to a very clean ground return. Grounding components to the wrong location will result in reduced conversion accuracy.

7.0 Dynamic Performance

Many applications require A/D converters to digitize AC signals, but traditional DC integral and differential nonlinear metrics cannot accurately predict A/D converter performance under AC input signals. An important specification for AC applications reflects the converter's ability to digitize AC signals without significant spectral errors and without adding noise to the digitized signal. Dynamic properties, such as signal-to-noise ratio (SNR) and total harmonic distortion (THD), are quantitative measures of this capability.

The AC performance of an A/D converter can be measured using the Fast Fourier Transform (FFT) method. A sinusoidal waveform is applied to the input of the A/D converter, and the digitized waveform is transformed. The resulting spectrum may be similar to that shown in a typical performance curve. The largest peak is the fundamental frequency, and noise and distortion components (if present) are visible above and below the fundamental frequency. Harmonic distortion components appear at integer multiples of the input frequency. Their amplitudes are combined as the square root of the sum of squares and compared to the base amplitude to derive the THD specification. Guaranteed limits for THD are shown in the Electrical Characteristics table.

The signal-to-noise ratio is the ratio of the amplitude of the fundamental frequency to the rms value of all other frequencies, excluding any harmonic distortion components. Guaranteed limits are given in the Electrical Characteristics table. Another definition of signal-to-noise ratio includes distortion components and random noise resulting in a signal-to-noise ratio plus distortion ratio (S/(N+D)).

The THD and noise performance of an A/D converter will vary with the frequency of the input signal, producing more distortion and noise at higher signal frequencies. One way to describe the performance of an A/D as a function of signal frequency is to plot the "significant bits" versus frequency. The ideal signal-to-noise ratio of an A/D converter without wireless error or self-generated noise would be equal to (6.02n + 1.8) dB, where n is the bit resolution of the A/D converter. A real A/D converter will have some noise and distortion, the significant bits can be found by:

where S/(N+D) is the signal-to-noise ratio and the degree of distortion, which varies with frequency.

For example, an ADC10461 with a 4.85vp-P, 100khz sine wave input signal typically has a signal-to-noise ratio and distortion ratio of 59.2db, which equates to 9.54 significant bits. As the input frequency increases, the noise and distortion gradually increase, producing a plot of effective bits or S/(N+D), as shown in a typical performance curve.

8.0 Speed Adjustment

In applications that require faster conversion times, the speed adjustment pins (pin 14 on ADC10462, pin 17 on ADC10464) can significantly reduce conversion times. The speed regulation pins are connected to on-chip current sources that determine the converter's internal timing. As shown in Figure 4, by connecting a resistor between the speed pin and ground, the internal programming current is increased, thereby reducing the transition time. For example, an 18k resistor reduces the transition time of a typical part from 600 ns to 350 ns without a significant effect on linearity. It is also possible to use smaller resistors to further reduce the transition time, although the linearity will start to drop a bit (see curve). Note that the resistor values required to obtain a given transition time will vary from part to part, so this technique usually requires some "adjustment" to obtain satisfactory results.

For applications requiring guaranteed performance using the speed regulation pins, the ADC10662 and ADC10664 are tested and guaranteed for static and dynamic performance with a fixed speed-up resistor value.