Gradually design

Application conditions: vin u003d 3.3V, ± 10%vout u003d 1.25V IOUT u003d 5A fsw u003d 270kHz

Input a capacitor.

Pulse current (the average value is zero) flows through the input capacitor of the buck converter. The AC component of this current is quite high, and the ESR of the capacitor consumes a lot of power:

The average root current that the capacitor must provide is:

Among them, Δ is the last item of the duty occupation ratio of the application, and the equation is simplified to:

Which maximum value corresponds to Δ u003d 1/2, which is equal to iOUT/2. Therefore, in the worst, in the worst, the worst is In the case, the valid value of the input capacitor should be as high as half of the maximum output current. Electrolytic capacitors are the most commonly used because they are the cheapest and have a wide range of market -based current range rated range. The only disadvantage is that they are more physical than other capacitors. Very good electric container is about to be launched, with very low ESR and small size. The only problem is that if they are very high in the charging process, they sometimes burn. Therefore, it is best to avoid this type of capacitor as an input filter device. In fact, they may be connected to the current when the high waves are affected. If the required capacitance value and rated voltage are suitable for a given physical size, ceramic capacitors usually have a high average root current rated value (due to low blood sink). The disadvantage is that the cost is quite high. Possible solutions:

Electric sensor

Definition of inductance, first determine the inductance value. Its minimum value is given by the following formulas:

In the formula RF u003d #8710; I/IOUT (basically about 30%).

According to our parameters: minimum value ≥2 μH saturation current must be higher than 5A

output capacitance and ripple voltage

Select the output capacitor according to static and dynamic output voltage accuracy. Static output voltage accuracy mainly depends on the current variable of the output capacitor, and the dynamic accuracy usually depends on ESR and capacitance. If the static accuracy of the 1.25V output voltage is ± 1%, the output ripple is ± 12.5mv. In order to determine the ESR value according to the output accuracy, the ripple current needs to be calculated:

Among the FSW u003d 270kHz.

According to the above formula, the ripple current is about 1.25A. Therefore, ESR is concluded from the following formulas:

The dynamic specifications are availableShi is more loose than static requirements. In any case, the minimum output capacitor must be made to avoid changes in the output voltage caused by charging and discharge during the load transient process. In order to make the device control loop working normally, the output capacitor ESR (τ u003d ESR) introduces zero point · COUT) must be at least ten times smaller than the switch frequency. Low ESR 钽 electric container is close to 10 kilo, suitable for output filtering. The output capacitor value Cout and its ESR, ESRCOUT, should be large enough and small to keep the output voltage in a load transient within the accuracy range, and give the device a minimum signal -to -noise ratio. The current ripple flows through the output capacitor, so it should also be calculated to maintain the ripple: the equal square root current value is given by the type 18.

MOSFET and Schottky diode

3.3V bus to power the grille drive of the device. Current application. MOSFET breakdown voltage VBRDSS must be greater than Vinmax. Once you determine the allowable power consumption, you can choose RDSON. By selecting the same power MOSFET for US and LS, the total power they consume does not depend on the duty cycle. Therefore, if PON's power loss (a few percent of the rated output power) is required? RDSON (@25 ° C) can be concluded by the following formulas:

α It is the temperature coefficient of RDSON (usually, for these low-voltage levels, α u003d 510-3 ° C-1) and allowed temperature rise. However, it is worth noting that, in general, the lower the RDSON, the higher the door charging QG, which will lead to higher door -driven consumption. In fact, each switching cycle has a charge QG move from the input power to ground to generate an equivalent driving current:

A Schottky diode can be increased to high at high to high at high to high at high to high. The system efficiency at the switch frequency (where the dead area may be an important part of the entire switching cycle). This optional diode must be packed in parallel, and the rectifier must have a reverse voltage VRRM larger than Vinmax. The current of the diode must be selected to make it safe. In order to use less space than possible, a dual MOSFET: STS5DNF20V

output voltage settings are selected in a package

The first step is to select the output pressure device to set the output voltage. There is no condition to choose this value, but the low -point network value (about 100 ) will reduce the efficiency of low -current; on the contrary, high -scoring frequency device will reduce the impact of the efficiency network (100K #8486). From 1K to 10K network allocation device values u200bu200bare correct. We chose:

r3 u003d 1K

R2 u003d 1.1k

By connecting the pressure divider from the output to the VSENSE pin, the output voltage of the device can be adjusted. The minimum output voltage is vout u003d VREF u003d 0.6V. Once the output frequency division and frequency divider design is designed as the required output voltage and switching frequency, the lower formula gives the minimum input voltage, and L6997S is allowed ]

Voltage feedback

From equation 1, 2, and 3, select 270kHz switch frequency to select the resistor division.

For example:

r3 u003d 470k

r4 u003d 8.5k Formula 8, considering the RDSON STS5DNF20V and ICIR u003d 5A, you can set the valley current limit: r8 u003d 120K

assuming fu u003d 15kHz, vout u003d 1.25V. Due to VREF u003d 0.6V, according to the Formula 2 described by the device, it follows αout u003d 0.348 and follows C u003d 250pf according to Formula 5. The output ripples are around 22mv, so the system does not need a second integral.

Soft -raising the power capacitor

Considering the soft starting equation on page 10 (Formula 11), it can be found that: CSS u003d 150 pounds/square feet is valid under air load. When there are activity loads, the results of the equation are more complicated; further some contributed loads will have an unexpected impact, because during the soft startup process, higher than the expected current will cause changes to the startup time. In this case, the capacitor value can be selected in the application; no matter what, the EQ11 gives the CSS value.

15A demonstration board description

The evaluation board display device runs under the following conditions: vin u003d 3.3v vout u003d 1.8v out u003d 15a, fsw u003d 200kHz, no accumulator function. There are two different input voltages of the evaluation board: VCC [from 3V to 5.5V] to supply power and provide VIN [up to 35V] for power conversion. In this way, change the configuration of power components (CIN, COUT, MOSFET, L), you can evaluate the performance of the device under different conditions. You can also install a linear regulator to generate VCC on board. There are two switches and four jumpers on the top. These two switches have different goals: the closest to VCC is turned on/off the device when both VCC and VIN exist;Open/turn off the PFM function. The device can also be opened with a power supply, but it is necessary to correctly start the sequence. You must first improve the vehicle identification number (VIN) before you can apply VCC. If the order is correct, the device will not be started. The jump line is used to set the integral function and use remote sensing; please refer to the jumper table for more information. Sometimes when using the integral configuration, a low -frequency filter is required to reduce noise interference. The extreme value should be at least 5 times higher than the switch frequency. Low -pass filter should be inserted in this way: resistance, in the INT jump position, the capacitor between the resistor and ground (refer to the schematic diagram).

Demonstration board layout

Actual size: 5.7cm x 7.7cm (2.28 inches x 3.08 inches)

Efficiency curve

DDR memory and terminal power supply

dual data rate (DDR) memory memory Need a specific power management architecture. This is because the tracking between the driving chipset and the memory input must be terminated with a resistor. Because the chipset drives memory has a push -pull output buffer, the terminal voltage must be able to generate and absorb current. In addition, the terminal voltage must be equal to half of the memory power supply (input end) memory is a differential stage, which requires a midpoint of reference deviation) and tracking it. For the DDRI memory power supply is 2.5V, the terminal voltage is 1.25V, the storage power supply of DDRII is 1.8V, and the terminal voltage is 0.9V. Figure 27 shows the use of 2 x L6997s. The 1.8V part is powered by memory, and the 0.9V part provides terminal voltage.

The current required for the memory and terminal power supply depends on the type and size of the memory. Figure 28 and 29 show the termination of the application displayed in Figure 27.

CH1- GT; sensor current

ch2- gt; stage node

CH3 - gt; output voltage