Features: Differential clock source for direct RAMBUS memory subsystem for data transfer rates up to 800 MHz. Provides synchronization flexibility: RAMBUS® channels can optionally be synchronized to an external system or processor clock. A power management output allows the RAMBUS channel clock to be turned off to minimize power consumption. For mobile applications, Cypress CY2210 , W133 , W158, W159, W161 and W167 work together to support Intel architecture platform, low power CMOS in 24-pin QSOP ( 150 mil SSOP) package Design Description Cypress W134M/W134S for Direct Rambus The memory subsystem provides differential clock signals. It includes signals to synchronize the direct Rambus channel clock with an external system clock, but can also be used in systems that do not need to synchronize the Rambus clock.

Main Specifications Supply Voltage: VDD=3.3V±0.165V Operating Temperature: …….0°C to +70°C Input Threshold: 1.5V Typical Maximum Input Voltage: …VDD+0.5V Maximum Input Frequency: …100 MHz Output Duty Cycle: 40/60...Worst Case Output Type:...RAMBUS Signaling Level (RSL) DDLL System Architecture and Gear Ratio Logic Distributed Delay Locked Loop (DDLL) System Architecture including Main System Clock Source, Direct Rambus Clock Generator (DRCG) and core logic containing Rambus Access Unit (RAC), Rambus Memory Controller (RMC) and gear ratio logic. (This diagram abstractly represents a differential clock as a single bus clock line.) The purpose of the DDLL is to frequency lock and phase align the core logic and Rambus clocks (Pclk and Synclk) at the RMC/RAC boundary so that no additional delays are incurred data transfer is allowed. In the DDLL architecture, the PLL is used to generate the desired Busclk frequency, while the distributed loop forms the DLL to align the phases of Pclk and Synclk at the RMC/RAC boundary. The main clock source drives the system clock (Pclk) to the core logic and also drives the reference clock (Refclk) to the DRCG. For a typical Intel architecture platform, Refclk will be half the frequency of the CPU's front side bus. The PLL within the DRCG is multiplied by the Refclk to generate the frequency required by the Busclk, which is driven through the terminating transmission line (Rambus channel). At the midpoint of the lane, the RAC uses its own DLL-aware Busclk for clock alignment, followed by a fixed divide-by-4 that generates the Synclk.
Pclk is the clock used in the memory controller (RMC) in the core logic and Synclk is the clock used in the RAC core logic interface. The DDLL and gear ratio logic enable users to exchange data directly from the Pclk domain to the Synlk domain without incurring additional synchronization delays. In general, Pclk and Synclk can have different frequencies, so the gear ratio logic must choose the appropriate M and N dividers so that the frequencies of Pclk/M and Synclk/N are equal. In an interesting example, Pclk=133mhz, Synclk=100mhz, M=4, and N=3, giving Pclk/M=Synclk/N=33mhz. Example of a clock waveform with gear ratio logic. The output clocks of the gear ratio logic Pclk/M and Synclk/N are output from the core logic and routed to the DRCG phase detector input. The routing of Pclk/M and Synclk/N must match in the core logic and on the board. After comparing the phases of Pclk/M and Synclk/N, the DRCG phase detector drives the phase calibrator to adjust the phase of the DRCG output clock Busclk. Since everything else in the distributed loop is a fixed delay, adjusting Busclk adjusts the phase of Synclk and thus the phase of Synclk/N. In this way, the distributed loop adjusts the phase of Synclk/N to match the phase of Pclk/M, thereby eliminating the phase error at the input of the DRCG phase detector. When the clocks are aligned, data can be exchanged directly from the Pclk domain to the Synlk domain. The most interesting combinations of Pclk and Busclk frequencies, organized by gear ratio.

More details on DDLL system architecture, including DRCG output enable and bypass mode. Phase Detector Signal The DRCG phase detector receives two inputs from core logic Pclk M (Pclk/M) and Synclk N (Synclk/N). The M and N dividers in the core logic are chosen so that the frequencies of PclkM and SynclkN are the same. The phase detector detects the phase difference between the two input clocks and drives the DRCG phase calibrator through a distributed loop to make the input phase error zero. When the loop is locked, the input phase error between PclkM and SynclkN is within the tERR,PD specification given in the Device Characteristics table after the lock time given in the state transition section. The phase detector aligns the rising edge of PclkM with the rising edge of SynclkN. The duty cycle of the phase detector input clock should be within the DCIN, PD specifications given in the Operating Conditions table. Since the duty cycles of the two phase detector input clocks are not necessarily the same, when the rising edges are aligned, the falling edges of PclkM and SynclkN may not be aligned. The voltage levels of the PclkM and SynclkN signals are determined by the controller. Pin VDDIPD is used as the voltage reference for the phase detector input and should be connected to the output voltage supply of the controller. In some applications, the DRCG PLL output clock will be used directly by bypassing the phase calibrator. If PclkM and SynclkN are not used, these inputs must be grounded. Logic to select the PLL prescaler and feedback divider to determine the multiplier of the PLL from the input Refclk. Divider A sets the feedback, and divider B sets the prescaler, so the PLL output clock frequency is set by: PLLclk=Refclk*A/B.
Table 3 shows the logic to enable the clock output using the StopB input signal. When StopB HIGH, the DRCG is in normal mode, and Clk and ClkB are the complementary outputs after the phase calibrator output (PAclk). When StopB is low, the DRCG is in Clk stop mode, the output clock driver is disabled (set to Hi-Z), Clk and ClkB are set to the DC voltage VX, stopped, as shown in the device characteristics table. The level of VX, STOP is set by an external resistor network.
Table 4 shows the logic for selecting bypass and test modes. Selection bits S0 and S1 control the selection of these modes. Bypass mode generates the full-speed PLL output clock, bypassing the phase calibrator. Test mode brings the Refclk input all the way to the output, bypassing the PLL and phase calibrator. In output test mode (OE), both the Clk and ClkB outputs are put into a high impedance state (Hi-Z). This can be used for component testing and board level testing.

Frequency and Gear Ratio Several supported Pclk and Busclk frequencies, corresponding A and B dividers required in the DRCG PLL, and corresponding M and N dividers in the gear ratio logic. The column ratio gives the gear ratio defined as Pclk/Synclk (same as M and N) F@PD column gives the frequency division at the phase detector (in MHz), where F@PD=Pclk/M=Synclk/ N. The state transition clock source has three basic operating states. Figure 4 shows the state diagram, with each transition labeled A to H. Note that the clock source output may not be glitch-free during state transitions. After the device is powered on, the device can enter any state, depending on the settings of the control signals, pwrdb, and StopB. In the power down mode, the clock source is powered down and the control signal pwrdb is equal to 0. Before the device is powered on, the control signals S0 and S1 must be stable and can only be changed in power-down mode (pwrdb=0). The reference inputs, VDDR and VDDPD, may remain on or grounded in power-down mode.

layout example

Packaging diagram

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