General description

Using a patented multi-step A/D conversion technique, the 8-bit ADC08061 and ADC08062 CMOS ADCs provide 500 ns (typ) conversion time, internal sample and hold (S/H), and consume only 125 megawatts of power. The ADC08062 has a dual channel multiplexer. The ADC08061/2 family performs 8-bit conversion using a 2-bit voltage estimator, generating 2 MSBs and two low-resolution (3-bit) blinks to generate 6 lsbs. Input track and hold circuitry eliminates the need for external sample and hold. The ADC08061/2 series performs with a frequency range from DC to 300 kHz (full power bandwidth) without external S/H. The digital interface is designed to facilitate connection to a microprocessor and allow components to be I/O or memory mapped.

Main Specifications

8-bit resolution; 560 ns maximum conversion time (WR-RD mode); 300 kHz full power bandwidth; 1.5 MHz throughput; 100 mW maximum power consumption; total unadjusted error ±1/2 LSB and ±1 LSB.

Features

1 or 2 input channels; no external clock required; analog input voltage range from GND to cascade-available V+n overflow output (ADC08061); ADC08061 pinout conforms to industry standard ADC0820 type.

application

Mobile communications; hard disk drives; instrumentation; high-speed data acquisition systems.

Pin Description

These are analog inputs. The input range is CS low and begins to transition when VIN1–8 falls to ground –50 mV≤VINPUT≤V++50 mV. RD's Edge. The output data appears on the DB0–DB7 ADC08061 with a single input (VIN) and at the end of the conversion (see Figures 1, 5).

The ADC08062 has a dual multiplexer, which is an active low output, representing (V) 1–2). Conversion complete, data at DB0–DB7 3-state data output - bit 0 (LSB) is latched by output device. INT is bit 7 (MSB). road.

WR/RDY WR-RD Mode (logic high applied to mode pin) GND This is the power ground pin. Ground WR: With CS low, the conversion is initiated on the pin and should be connected to a "clean" ground on the falling edge of WR. The numerical result will be Ellens points.

At con-VREF-, these are the output latches at the reference voltage input. their versions (see Figures 2, 3, 4). VREF+ can be placed at ground -: RD Mode (logic low for mode pins) 50 mV and V++ 50 mV, but VREF+ must be greater than V.

Absolute Maximum Ratings (Note 1, 2) Lead Temperature

If military/aerospace equipment is required, J package (soldering, 10 seconds) + 300 303C please contact National Semiconductor Sales Office / N package (soldering, 10 seconds) + 260 303C distributor for availability and specifications.

Converter characteristics

The following specifications are for RD mode, V+=5V, VREF+=5V, and VREF-=GND, unless otherwise specified. Bold limits apply to TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C.

AC Electrical Characteristics

The following specifications apply to V+=5V, tr=tf=10ns, VREF+=5V, VREF-=0V unless otherwise specified. Bold limits apply to TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C.

DC characteristics

The following specifications apply to V+=5V unless otherwise specified. Bold limits apply to TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C.

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply to equipment operation beyond the stated operating ratings. Operating ratings indicate the conditions under which the device will operate, but do not guarantee performance limitations. See Electrical Characteristics for guaranteed specifications and test conditions. Warranty specifications apply only to the test conditions listed. Certain performance characteristics may be degraded when the device is not operated under the listed test conditions.

Note 2: Unless otherwise specified, all voltages are measured with respect to the GND pin.

Note 3: When the input voltage (V) of any pin exceeds the supply voltage (V V), the absolute value of this pin should be limited to 5 mA or less. The 20mA package input current specification limits the number of pins that exceed the power supply boundary to four, and the 5mA current limit is limited to four.

Note 4: The power consumption of this unit during normal operation should not exceed 875 mW (static power consumption + load on digital output). Care should be taken not to exceed the absolute maximum power rating when the equipment is in a critical fault condition (for example, when any input or output exceeds the power supply). The maximum power dissipation must be reduced at elevated temperatures and is determined by T (maximum junction temperature), Th (package junction-to-ambient thermal resistance), and T (ambient temperature). The maximum allowable power dissipation at any temperature is PD = (t)TT / or the number given in Absolute Ratings, whichever is lower. The table below details the Tandθ for various packages and versions of the ADC08061/2.

Note 8: The quota is guaranteed to meet the country's AOQL (Average Output Quality Level).

Note 9: Unadjusted total error includes offset, full scale and linearity errors.

Note 10: Two on-chip diodes are connected to each analog input and are reverse biased during normal operation. One is connected to Vand and the other is connected to GND. When the analog input voltage is equal to or greater than Vor one diode drop below GND, they become forward biased and conduct. Therefore, care should be taken when testing with V=4.5V. An analog input with a value equal to 5V can cause the input diode to conduct, especially at high temperatures. This creates conversion errors for analog signals that are close to full scale. The specification allows for 50 mV of forward bias on either diode; for example, as long as the analog input signal does not exceed 50 mV of the supply voltage, the output code will be correct. Exceeding this range on unselected channels will corrupt the reading of selected channels. An absolute analog input signal voltage range of 0V≤V≤5V can be achieved by ensuring that the minimum supply voltage applied to Vis is 4.950V with temperature variation, initial tolerance and load.

Note 11: Measure the leakage current outside the channel after channel selection.

application information

1.0 Functional Description

The ADC08061 and ADC08062 perform 8-bit analog-to-digital conversion using a multi-step flash technique. The first flash generates five most significant bits (msb) and the second flash generates three least significant bits (lsb). Figure 6 shows the main functional blocks of the ADC08061/2's multi-step flash converter. It consists of an over-coded 2/2-bit voltage estimator, an internal DAC with two different voltage ranges, a 3½-bit flash converter, and a comparator multiplexer.

resistor string near the center of the block diagram

Figure 6 constitutes the internal main DAC. Each of the eight resistors at the bottom of the string is equal to 1/256 of the total resistance of the string. These resistors form an LSB ladder with a voltage drop of 1/256 of the total reference voltage (VREF+ - VREF-) across them. The remaining resistors form the MSB ladder. They consist of eight groups of four resistors in series. 8% of the total reference voltage on each main switchboard run. In a given MSB ladder section, each MSB resistor has 8/256 or 1/32 of its total reference voltage. Wiper points are found between all resistors in the MSB and LSB ladders. Through the comparator multiplexer, these tap points can be connected in groups of 8 to the 8 comparators shown on the right side of Figure 6. This function provides the necessary reference voltage for the comparator during each flash transition.

The six comparators, seven resistor strings (estimator DACs) and the estimator decoder on the left side of Figure 6 constitute the voltage estimator. The estimator DAC is connected at VREF+ and VREF- to generate the reference voltages for the six voltage estimator comparators. These comparators perform very low resolution A/D conversions to obtain an "estimate" of the input voltage. This estimate is then used to control the comparator multiplexer, connecting the appropriate MSB ladder section to the eight flash comparators. Only 14 comparators (6 in the voltage estimator and 8 in the flash converter) can achieve full 8-bit resolution instead of the 32 comparators required by the traditional half-flash approach.

The conversion starts with a voltage estimator, which compares the analog input signal to the six-tap voltage on the estimator's DAC. The estimator decoder then selects a set of tap points along the MSB ladder. These eight tap points are then connected to eight flash comparators. For example, if the analog input signal applied to VIN is between 0 and 3/16 of VREF (VREF=VREF+-VREF-), the estimator decoder instructs the comparator multiplexer to select 8/256 and 2/8 of VREF between the 8 tap points and connect them to the 8 flash comparators. Now perform the first flash conversion, generating five MSBs of data.

The remaining three lsbs are then generated using the same eight comparators used for the first flash conversion. As determined by the result of the MSB flashing, the voltage from the MSB ladder is equal to the five most significant bits subtracted from the analog input voltage when the upper switch is moved from position 1 to position 2. The resulting residual voltage is applied to the eight flash comparators and, with the lower switch in position 2, is compared with the eight tap points from the LSB ladder.

By using the same eight comparators for both flash conversions, the number of comparators required for multi-step converters is significantly reduced compared to standard half-flash techniques.

Since the flash comparator is connected to a step voltage that is outside the specified range of the voltage estimator, the voltage estimator error will be corrected up to 1/16 of VREF (16 lsb). For example, if 7/16 VREF

2.0 digital interface

The ADC08061/2 has two basic interface modes, selected by connecting the mode pin to logic high or low.

2.1 RD Mode

When a logic low is applied to the mode pin, the converter is set to read mode. In this configuration (see Figure 1), a full version is done by pulling RD low and holding it low until the conversion is complete and output data is displayed. This typically takes 655 nanoseconds. At the end of the conversion, the INT (interrupt) line goes low. A typical delay of 50 ns is required between the rising edge of RD (after conversion ends) and the start of the next conversion (by pulling RD low). The RDY output goes low after the falling edge of CS and goes high at the end of the conversion. It can be used to signal the processor that the converter is busy, or as a system transmission acknowledgement signal. For the ADC08062, the data generated in the first conversion cycle after power-up comes from an unknown channel.

2.2 RD mode pipeline operation

Applications requiring shorter RD pulse widths than those used in the read modes described above can be developed by setting the width of RD between 200 ns – 400 ns (Figure 5).

Pulse widths outside this range will result in conversion linearity errors. These errors are due to in-interface logic using CS and/or RD during conversion.

When RD goes low, a conversion is initiated and data from the previous conversion is available for DB0–DB7 outputs. The first two reads of D0–D7 after power up generate random data. Data will be valid during the third RD pulse that occurs after the first conversion.

2.3 WR-RD (WR-then-RD) mode

ADC08061/2 is in WR-RD mode with mode pin hit high. Conversion begins with the falling edge of the WR signal. There are two options for reading output data related to interface timing. If an interrupt-driven scheme is desired, the user can wait for the INT output to go low before reading the conversion result (see Figure 3). Typically, INT will be low for 520 ns, maximum, after the rising edge of WR. However, if a short conversion time is required, the processor does not need to wait for INT and can perform a read in as little as 350 ns (see Figure 2). If RD is pulled low before INT runs, INT will go low immediately and data will appear on the output. This is the fastest operating mode (tRD≤tINTL) with a conversion time (including data access time) of 560ns. 100 ns is allowed for reading conversion data, and the delay between conversions results in a total throughput time of 660 ns (1.5 MHz throughput rate).

2.4 WR-RD mode to reduce interface system connection

CS and RD can be limited to lower levels, using only WR to control the start of conversion for applications that require a reduced digital interface when operating in WR-RD mode (Figure 4). Data will be valid approximately 705 ns after the rising edge of WR.

2.5 Multiplexer addressing

The ADC08062 has 2 multiplexer inputs. These are selected using the A0 multiplexer channel select input. Table 1 shows the input codes required to select a given channel. The multiplexer address is locked on reception, but the multiplexer channel is updated after the current conversion is complete.

The multiplexer address data must be valid on the falling edge of RD, during conversions, and can go high after RD goes high when operating in read mode.

The multiplexer address data should be valid on or before the falling edge of WR, remain valid while WR is low, and de-assert when operating in WR-RD mode while WR is high.

3.0 Reference Input

The two VREF inputs of the ADC08061/2 are fully differential, defining the zero-to-full-scale input range of the A-to-D converter. This allows the designer to vary the range of the analog input, as this range will be equivalent to the voltage difference between VREF+ and VREF-. The sensor can also compensate for a minimum output voltage above GND by connecting VREF- to a voltage equal to this minimum voltage. By reducing VREF (VREF=VREF+–VREF-) below 5V, the sensitivity of the converter can be increased (ie, if VREF=2.5V, then 1 LSB=9.8mV). The reference configuration of the ADC08061/2 also facilitates ratiometric operation, and in many cases the power supply of the ADC08061/2 can be used for the sensor supply and the VREF supply. Ratiometric operation is achieved by connecting VREF- to GND, and connecting VREF+ and the sensor's power supply input to V+. When the VREF+ voltage is lower than 2.0V, the linearity of the ADC08061/2 is degraded.

The voltage setting at VREF produces the input level of the digital output with all zeros. Although the VIN itself is not differential, the reference design provides nearly differential input capability for some measurement applications. Figure 7 shows one possible differential configuration.

It is important to note that when the two VREF inputs are completely different, the digital output of any analog input voltage will be zero if VREF – ≥ VREF+.

4.0 Analog Input and Source Impedance

The analog input circuit of the ADC08061/2 consists of an analog switch with an "on" resistance of 70Ω and capacitances of 1.4 pF and 12 pF (see Figure 7). The switch is at the A/D's input signal acquisition time (WR-RD mode is used when WR is low). Every time the switch closes, a small transient current flows into the input pin. There may be a transient voltage at the input, the magnitude of which can increase as the source impedance increases. As long as the source impedance is less than 500Ω, input voltage transients will not cause errors and do not require filtering.

A large source impedance will slow down the charging speed of the sampling capacitor and reduce conversion accuracy. Therefore, only use a signal source with an output impedance less than 500Ω when the rated accuracy is achieved at the minimum sampling time (100 ns maximum). Signal sources with high output impedance should buffer their output with an op amp. Any ringing or voltage offset at the op amp output during sampling can cause conversion errors.

Correct conversion results will be obtained when the input voltage is greater than GND-100 mV and less than V++100 mV. Signal sources are not allowed to drive analog input pins more than 300 mV above V+ or 300 mV below GND. Current flowing through any analog input pins should be limited to 5 mA or less to avoid permanent damage to the IC if the analog input pins are forced above these voltages. The sum of all overdrive currents into all pins must be less than 20mA. When the input signal exceeds the power supply limit by more than 300mV, some kind of protection scheme should be used. Figure 9 shows a simple protection network using resistors and diodes.

6.0 Inherent Sample and Hold

An important advantage of the ADC08061/2 input structure is the inherent sample-and-hold (s/H) and its ability to measure relatively high-speed signals without resorting to an external s/H. In a non-sampling converter, regardless of its speed, if full accuracy is to be maintained. Therefore, for many high-speed signals, the signal must be externally sampled and held stationary during the conversion process.

The ADC08061 and ADC08062 are suitable for DSP based systems because the WR signal is passed. The WR input signal allows the A/D to be synchronized with the sample rate of the DSP system or other ADC08061 and ADC08062s.

The ADC08061 can perform accurate conversion of full-scale input signals from dc to frequencies in excess of 300kHz (full power bandwidth) without the need for an external sample and hold (S/H).

7.0 Layout, Grounding and Bypassing

It is necessary to employ proper board layout techniques in order to ensure that from the ADC08061/2. Ideally, the ground reference for the analog-to-digital converter should be low impedance and unaffected by noise from other parts of the system. Digital circuits generate a lot of noise on their ground loops, so they should have their own separate ground wire. For the digital and analog parts of the system, use separate ground planes for best performance.

The analog input should be isolated from noisy signal traces to avoid spurious signal coupling into the input. Any external components connected to the input (such as input filter capacitors) should be returned to a very clean ground. Improper grounding of the ADC08061/2 will result in reduced conversion accuracy. The V+ supply pins, VREF+ and VREF- (if not grounded) should be bypassed with a parallel combination of 0.1µF ceramic capacitors and 10µF tantalum capacitors.