Features: Output Range: 0.8V to VIN – 0.8V Internal Reference Voltage – ±1.5% Overline and Temperature Drive N-Channel MOSFET Simple Single Loop Control Design – Voltage Mode PWM Control Fast Transient Response – High Bandwidth Error Amplifier – Full 0% to 100 % Duty Cycle Non-destructive, Programmable, Over Current Protection – RDS (On) Small Converter Using Upper MOSFET – 300kHz Fixed Frequency Oscillator – Internal Soft Start – 8-Lead SOIC

Applications: Power supplies for PC subsystems and peripherals MCH, GTL and AGP supply Cable modems, set-top boxes and DSL modems Digital signal processors, memory Low voltage distributed power supply

Description: The FAN6520A simplifies the complete control and protection scheme of a DC-DC buck converter. Designed to drive synchronous buck topologies, the FAN6520A integrates control, output regulation, monitoring, and protection functions in an 8-wire package. The FAN6520A employs voltage mode control with a single feedback loop and fast transient response. The output voltage is precisely regulated to 0.8V, with a maximum temperature tolerance of 1.5% and line voltage variations. Fixed frequency oscillators reduce design complexity while balancing typical application cost. The error amplifier has a 15MHz gain bandwidth and a slew rate of 8V/µs enabling fast transient performance with high slew bandwidth. The resulting PWM duty cycle ranges from 0% to 100%. The integrated circuit monitors the upper MOSFET and inhibits PWM operation appropriately to prevent overcurrent conditions. This approach simplifies by eliminating the need for a current sense resistor. Fan 6520A is rated to operate from 0° to +70°C, and Fan 6520AI is rated to operate from -40° to +85°C.

CIRCUIT DESCRIPTION INITIALIZATION The auto-initialization power function continuously monitors the bias voltage of the VCC PIN after receiving the power reset power function. When the supply voltage exceeds the threshold, the IC initiates the overcurrent protection operation UPON Completion of the OCP sample-and-hold operation, and the Por function initiates soft-start operation. On shortening the output, RDS ("On-Resistance", to Monitor the Current. This method improves the efficiency of the converter and reduces cost by eliminating the need for a current sense resistor. The tea overcurrent function loops the soft-start function and the covert mode provides faults Protection. A resistor ("ROCSET") program overcurrent travel level ("see typical") application diagram immediately follows triggering overcurrent protection sample-and-hold operation. First, the internal error amplifier is lossless. This allows An internal 20 micro a current sink develops the voltage on the roof. The French film then places a sample of this voltage on the compressor. This sampled match, which is referenced to the VCC pin, is held Internally as the over-current set point. When the voltage exceeds On Morse, this is also referenced to in addition to the overcurrent set point, the VCC PIN overcurrent function begins a soft-start sequence. Figure 3 shows the inductor current after a fault, which is positive at 15A when introduced. A typical hidden cause of continuous faults Mode Period of 25ms. The inductor current increases to 18A during the soft-start interval and during the process of causing excess current. The converter's very small power method measures the condition of the input power as 1.5W.

After the soft-start, the POR function initiates the soft-start sequence and the overcurrent setpoint has been sampled. The soft-start clamps the error amplifier output (COMP pin) and the reference input (the non-vertical terminal of the error amplifier) to an internally generated soft-start voltage. Figure 4 shows the typical startup interval for the COMP/OCSET pin to have a release from ground (system shutdown) state. Initially, COMP/OCSET was used to draw 20µA by disabling the error amplifier and by ROCSET. Once the overcurrent level has been sampled, the soft-start function is activated. The clamp pin on the error amplifier (COMP/OCSET) initially controls the output voltage soft start of the converter. The oscillator's triangular waveform is compared to the ramp-up error amplification voltage. This produces wider and wider SW pulses for the output capacitor. The output voltage is in regulation when the internally generated soft-start voltage exceeds the feedback (FB pin) voltage. This method provides fast control of the output voltage rise. The entire boot process typically takes 11 milliseconds.

The FAN6520A integrates a MOSFET pass-through, a protection method that allows the converter to sink and source current simultaneously. When designing an inverter with the FAN6520A it is known that the converter may draw current. When the converter sinks current, it behaves as the boost converter regulates the input voltage. This means that the inverter is delivering current to the VCC rail, biasing the fan 6520A. If this way the water has nowhere to go to the load on the VCC rail, sink current through the VCC bus through a voltage limiting protection device or some other method. This allows the level of the voltage VCC rail to increase. If the rail is lifted to a level that exceeds the maximum voltage rating of the FAN620A, the IC experiences an irreversible failure and the converter is no longer available. operational. Make sure the current has a path other than the capacitance on the track to prevent this failure mode. Application Information Layout Considerations In any high frequency switching converter, layout is very important. Switching current from one power supply device to another can trace the impedance of interconnecting bond wires and circuits. Use wide, short printed traces to minimize interconnect resistance. Critical components should be constructed as close to the ground plane as possible or grounded at a single point.

The diagram shows the key power components of the converter. To minimize voltage overshoot, the interconnecting wire (indicated by the bold line) should be the ground or power strip in the printed circuit board. The components shown in this figure should be located as close together as possible. Note that capacitors CIN and COUT can respectively represent many physical capacitors. Position the fan 6520A within two inches of Q1 and Q2 MOSFETs. The mosfet's circuit traces the gate and source connections from the FAN6520A must withstand peak currents up to 1A. The figure shows that additional layout considerations are required. The structure of the circuit shown using a single point and a ground plane. Minimize leakage of the current path on the COMP/OCSET pin and locate the ROSCET resistor close to the COMP/OCSET pin as the internal current source is only 20µA. Provide a local VCC decoupling pin between VCC and GND. As close as possible to the capacitor CBOOT boot and phase pins. The compensation used for feedback should be as close to the IC as practical.

The feedback compensation diagram highlights the synchronous rectification buck converter. The output voltage (VOUT) is regulated to the reference voltage level. This comparator error amplifier (error amplifier) output (VE/A) provides the VIN of the SW node of the PWM wave with the oscillator (OSC) triangle wave. through the output LC filter (LOUT and COUT).

The modulator transfer function is the small signal transfer function of VOUT/VCOMP. This function is dominated by the DC gain and output filters (LOUT and COUT), with the bipolar disconnect frequency at the FLC and the FBI. The DC gain of the modulator is the input voltage (VIN) divided by the peak-to-peak oscillator voltage (ΔVOSC.) The following equation defines the modulator turn-off frequency as a function of the output LC filter: The compensation network consists of an error amplifier (internal to the FAN6520A) and Impedance network ZIN and ZFB. The goal of the compensation network is to provide a crossover frequency (F0dB) with a maximum of 0dB and sufficient phase margin. Phase margin is the difference between the closed loop phase at F0dB and 180 degrees. Below the equation are the poles, zeros of the compensation network, and obtained components (R1, R2, R3, C1, C2, and C3) as shown. Use the following steps to locate the poles and zeros

Compensation Network:

1. Pickup gain (R2/R1) for the desired converter bandwidth.

2. Place the first zero below the double pole of the filter (about 75% FLC).

3. Put the second zero on the double pole of the filter.

4. Place the first pole at ESR zero.

5. Place the second pole at half the switching frequency.

6. Check the gain against the open loop gain of the error amplifier.

7. Estimate the phase margin. Repeat as necessary.

The figure shows an asymptotic plot of DC-DC converter gain versus frequency. The actual modulator gain has a high gain peak due to the high Q factor of the output filter, as shown. Using the guidelines above should give something similar to the curve drawn out. The open loop error amplifier gain limits the compensation gain. Check to compensate for the ability of the error amplifier to gain gain at FP2. The closed-loop gain is constructed on the graph of Figure 8 by adding the modulator gain (in dB) to the compensation gain (in dB). This is equivalent to multiplying the modulator's compensation transfer function transfer function and plotting the gain. The compensation gain uses external impedance networks ZFB and ZIN to provide a stable high bandwidth overall loop. The stable control loop has a gain crossover with a -20dB/decade slope and a larger phase margin greater than 45°. Including the worst-case component variation determines the phase margin.

An output capacitor is required to filter the output and provide load transient current. Filtering requirements are switching frequency and ripple current. Load transient requirements are slew rate (di/dt) and transient load current. These requirements are usually met with hybrid capacitors and careful layout. Component Selection Output Capacitors (COUT) Modern components and loads are capable of producing instantaneous duty rates higher than 1A/ns. High frequency capacitors initially provide transient currents and slow down the load rate of current bulk capacitors. Effective series resistance (ESR) and voltage rating are often the main considerations for bulk filter capacitors that are higher than actual capacitance requirements. High frequency decoupling capacitors should be placed on the power pins of the load as physically as possible. Taking care not to add inductance to the board layout can counteract these low inductance performance components. Negotiate specific decoupling requirements with the load manufacturer. Only use dedicated low-resistance capacitors for switching regulators applied to bulk capacitors. The ESR of the bulk capacitor determines the output ripple voltage and initial voltage drop after a high slew rate transient. The ESR value of aluminum electrolytic capacitors is case-dependent. In larger case sizes, lower ESR sizes are available; however, equivalent series inductance (ESL) capacitors for these sizes increase with case size, and capacitors can be reduced Action loading for high slew rate transients. Since ESL is not a specified parameter, do the following with the capacitor supplier to measure the frequency impedance of the capacitor to select the appropriate component. In general, multiple small capacitors perform better than one large capacitor.