feature

Integrated dual 14-bit ADC; single 3 V supply operation (2.7 V to 3.6 V); SNR = 71.6 dB (to Nyquist, AD9248-65) SFDR = 80.5 dBc (to Nyquist, AD9248-65) low power : 300 mW/channel at 65 MSPS; differential input, 500 MHz, 3 dB bandwidth; excellent crosstalk immunity >85 dB; flexible analog input: 1 VP to 2 VPP range; offset binary or two's complement code data format; clock duty cycle stabilizer; output datamux options.

application

Ultrasonic equipment; direct conversion or IF sampling receivers; WB-CDMA, CDMA2000, WiMAX; battery powered instruments; handheld oscilloscopes; low cost digital oscilloscopes.

General Instructions

The AD9248 is a dual, 3V, 14-bit, 20MSPS/40MSPS/65MSPS analog-to-digital converter (ADC). It features dual high-performance sample-and-hold amplifiers (SHAs) and an integrated voltage reference. The AD9248 uses a multi-stage differential pipeline structure with output error correction logic to provide 14-bit accuracy and guarantee no code loss over the entire operating temperature range at data rates up to 65 MSPS. The wide bandwidth, differential SHA allows a variety of user-selectable input ranges and offsets, including single-ended applications. It is suitable for a variety of applications, including multiplexed systems that switch full-scale voltage levels in continuous channels, and sampling inputs at frequencies well in excess of the Nyquist rate.

Dual single-ended clock inputs are used to control all internal conversion cycles. A duty cycle stabilizer is available to compensate for wide variations in the clock duty cycle, allowing the converter to maintain good performance. Digital output data is displayed in binary or two's complement format. The out-of-range signal indicates an overflow condition and can be used with the most significant bit to determine low or high overflow.

Fabricated on an advanced CMOS process, the AD9248 is available as a lead-free, space-saving 64-lead LQFP or LFCSP, and is specified over the industrial temperature range (-40°C to +85°C).

Product Highlights

1. Pin compatible with AD9238, 12-bit 20 MSPS/40 MSPS/65 MSPS ADC.

2. Speed grade options of 20 MSPS, 40 MSPS and 65 MSPS allow flexibility between power, cost and performance to suit the application.

3. Low power consumption: AD9248-65: 65 MSPS=600 MW, AD9248-40: 40 MSPS=330 MW, AD9248-20: 20 MSPS= 180 MW.

4. Typical channel isolation is 85dB@f=10MHz. exist

5. The clock duty cycle stabilizer (AD9248-20/AD9248-40/AD9248-65) maintains performance over a wide range of clock duty cycles.

6. Multiple data output option allows single port operation from data port A or data port B.

Specification

DC specification

AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CKKYA = CLKHYB; A = 0.5 dBFs differential input, 1 V internal reference, T to T, DCS enabled unless otherwise noted.

1. Gain error and gain temperature coefficient are based on ADC only (with fixed 1.0V external reference).

2. Measure the maximum clock rate with a low frequency sine wave input and approximately 5 pF loaded on each output bit.

3. Input capacitance refers to the effective capacitance between a differential input pin and AVSS. The equivalent analog input structure is shown in Figure 29.

4. Measured with DC input at maximum clock rate.

5. Standby power is measured with the CLK_A and CLK_B pins inactive (ie, set to AVDD or AGND).

AC Specifications

AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CKLYA = CLKHYB; A = = 0.5 DBFS differential input, 1 V external reference, T to T, DCS enabled unless otherwise noted.

Digital Specifications

AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CKKYA = CLKHYB; A = 0.5 dBFs differential input, 1 V internal reference, T to T, DCS enabled unless otherwise noted.

Switch Specifications

AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CKKYA = CLKHYB; A = 0.5 dBFs differential input, 1 V internal reference, T to T, DCS enabled unless otherwise noted.

1. The AD9248-65 model has a duty cycle stabilizer circuit that, when enabled, can correct a wide range of duty cycles.

2. Measure output delay from clock 50% transition to data 50% transition with 5 pF load on each output.

3. Wake-up time depends on decoupling capacitor value; typical values shown for 0.1µF and 10µF capacitors on REFT and REFB.

Absolute Maximum Ratings

Absolute Maximum Ratings are the limits for individual application beyond which maintainability of the circuit may be compromised. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

the term

Aperture delay

SHA performance measured from the rising edge of the clock input to holding the input signal transitioning.

Aperture jitter

Aperture delay variation for successive samples, manifested as noise at the ADC input.

Integral Nonlinearity (INL)

The deviation of each individual code for the line drawn from negative full scale to positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as 1.5 LSBs past the last code transition. Measure the deviation from the middle of each specific code to a true straight line.

Differential Nonlinearity (DNL, No Missing Code) An ideal ADC would show code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes at 14-bit resolution means that all 16384 codes must be present in all working ranges.

offset error

When the analog value is less than VIN+=VIN-, a large carry conversion should occur. Offset error is defined as the deviation of the actual transition point from this point.

gain error

The first code transition should occur at 1/2 LSB of the analog value above negative full scale. The last conversion should occur at the analog value 1.5 LSB below the nominal full scale. Gain error is the deviation between the actual difference between the first and last transcoding and the ideal difference between the first and last transcoding.

temperature drift

Temperature drift for zero error and gain error specifies the maximum change from the initial (25°C) value to the value of Tmin or TMAX.

Power supply rejection

The specification shows the maximum size change from the maximum value change with supply to the minimum value with supply at its maximum.

Total Harmonic Distortion (THD)

The ratio of the rms sum of the first six harmonic components to the rms value of the input signal under test, expressed as a percentage or decibels relative to the peak carrier signal (dBc).

Signal-to-noise ratio The ratio of the rms value of the input signal under test to the rms sum of all other spectral components below the Nyquist frequency, including harmonics, but excluding DC. The value of SINAD is expressed in dB.

Effective Number of Numbers (ENOB) using the formula: Signal-to-Noise Ratio (SNR)

For a sine wave input device at a given input frequency, ENOB can be calculated directly from its measured SINAD.

signal to noise ratio

Measures the ratio of the rms value of the input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and DC. The signal-to-noise ratio is expressed in decibels.

Spurious Free Dynamic Range (SFDR)

The difference in decibels between the rms amplitude of the input signal and the peak spurious signal.

Nyquist sampling

When the frequency components of the analog input are below the Nyquist frequency (f/2), this is often referred to as Nyquist sampling.

IF sampling

The ADC is not limited to Nyquist sampling due to the effects of aliasing. Higher sampling frequencies alias to the first Nyquist zone (DC-f/2) on the ADC output. The bandwidth of the sampled signal should not overlap with the Nyquist zone and aliasing. Nyquist sampling performance is limited by the bandwidth of the input SHA and clock jitter (jitter adds more noise at higher input frequencies).

Two-tone SFDR

The ratio of the rms value of any input tone to the rms value of the peak spurious components. Peak spurious components may or may not be IMD products.

Out of range recovery time

The time it takes for the ADC to regain the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale.

crosstalk

When an adjacent interfering channel is driven by a full-scale signal, couples to one channel driven by a (-0.5 dBFS) signal. Measurements include all spurs caused by direct coupled and mixed components.

theory of operation

The AD9248 consists of two high performance ADCs based on the AD9235 converter core. The dual ADC paths are independent except for the shared internal bandgap reference, VREF. Each ADC path consists of a dedicated front-end SHA and a pipelined switched capacitor ADC. The pipeline ADC is divided into three parts, including 4-bit first stage, 8 1.5-bit stages and the last 3-bit flash. Each stage provides enough overlap to correct flash errors in previous stages. The quantized output of each stage is combined into a final 14-bit result by digital correction logic blocks. The pipeline architecture allows the first stage to operate on new input samples, while the remaining stages operate on previous samples. Sampling occurs on the rising edge of the corresponding clock.

Each stage of the pipeline (excluding the last stage) consists of a low-resolution flash ADC and a residual multiplier that drives the next stage of the pipeline. The remaining multipliers use the flash ADC output to control a switched-capacitor digital-to-analog converter (DAC) with the same resolution. The DAC output is subtracted from the stage's input signal, and the remainder is amplified (multiplied) to drive the next pipeline stage. The remaining multiplier stages are also known as multiplying DACs (MDACs). A bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage consists of a flash ADC.

The input stage contains a differential SHA that can be configured as ac or dc coupled in differential or single-ended mode. The output scratch block aligns the data, performs error correction, and passes the data to the output buffer. The output buffer is powered by a separate supply, allowing the output voltage swing to be adjusted.

analog input

The analog input to the AD9248 is a differential switched capacitor SHA designed for optimum performance when dealing with differential input signals. The SHA input accepts inputs with a wide common-mode range. To maintain optimum performance, it is recommended to use the input common-mode voltage of the power supply.

The SHA input is a differential switched capacitor circuit. In Figure 32, the clock signal alternately switches the SHA between the sample mode and the hold mode. When the SHA switches to sampling mode, the signal source must be able to charge and stabilize the sampling capacitor within half a clock cycle. Small resistors in series with each input help reduce the peak transient current required to drive the source output stage. Additionally, a small shunt capacitor can be placed at the input to provide dynamic charging current. This passive network creates a low-pass filter at the ADC input; therefore, the exact value depends on the application.

If in sampling applications, remove any parallel capacitors. Combined with the driving source impedance, they limit the input bandwidth. For best dynamic performance, the source impedances driving VIN+ and VIN- should be matched so that the common-mode regulation errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC.

Internal differential reference buffers generate positive and negative reference voltages REFT and REFB, respectively, which define the span of the ADC core. The output common mode of the reference buffer is set to "medium supply", and the reference voltage and reference voltage range are defined as:

The above equations show that the REFT and REFB voltages are symmetrical around the mid-supply voltage, and by definition, the input span is twice the value of the V voltage.

The internal voltage reference can be pinned to a fixed value of 0.5 V or 1.0 V, or it can be adjusted within the same range discussed in the Internal Reference Connections section. Maximum SNR performance is achieved with a maximum input range of 2 V, and the relative SNR reduction is 3 dB when going from 2 V mode to 1 V mode.

The SHA can be driven from a source that keeps the signal peaks within the allowable range of the selected reference voltage. The minimum and maximum common-mode input levels are defined as:

The minimum common-mode input level allows the AD9248 to accommodate ground-referenced inputs. Although the best performance is obtained with differential inputs, single-ended supplies may be driven to VIN+ or VIN-. In this configuration, one input accepts a signal, while the other input should be set to midscale by connecting it to the appropriate reference. For example, a 2 volt pp signal can be applied to VIN+, while a 1 volt reference voltage can be applied to VIN-. The AD9248 then receives an input signal that varies between 2v and 0v. In a single-ended configuration, the distortion performance can be significantly reduced compared to the differential case. However, this effect is less pronounced at lower input frequencies and lower speed grade models (AD9248-40 and AD9248-20).

Differential Input Configuration

As previously mentioned, the best performance is achieved when driving the AD9248 in a differential input configuration. For baseband applications, the AD8138 differential driver provides excellent performance and a flexible ADC interface. The output common-mode voltage of the AD8138 is easily set to AVDD/2, and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal.

At input frequencies in the second Nyquist zone and above, the performance of most amplifiers is insufficient to achieve the true performance of the AD9248. This is especially useful for undersampling applications with sampling frequencies in the 70mhz to 200mhz range. For these applications, differential transformer coupling is the recommended input configuration, as shown in Figure 33.

Signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few megahertz, and excessive signal power can also cause the core to saturate, resulting in distortion.

Single-ended input configuration

In cost-sensitive applications, single-ended inputs can provide adequate performance. In this configuration, SFDR and distortion performance are degraded due to large input common-mode oscillations. However, if the source impedances at each input are matched, there should be little impact on the SNR performance.

Clock Inputs and Considerations

Typical high speed ADCs use two clock edges to generate various internal timing signals and, as a result, may be sensitive to the clock duty cycle. Typically, a 5% tolerance is required for the clock duty cycle to maintain dynamic performance characteristics.

The AD9248 provides separate clock inputs for each channel. Clocks operating at the same frequency and phase achieve the best performance. Timing channels asynchronously can significantly degrade performance. In some applications, it is desirable to skew the clock timing of adjacent channels. The independent clock inputs of the AD9248 allow for clock timing skew between channels (typically ±1ns) without significant performance degradation.

The AD9248-65 contains two clock duty cycle stabilizers, one for each converter, to retime non-sampling edges, providing an internal clock with a nominal 50% duty cycle. Maintaining a 50% duty cycle clock is especially important in high speed applications when proper track and hold times for the converter are required to maintain high performance. It is difficult to maintain a tightly controlled duty cycle on the input clock on the PCB (see Figure 24). DCS can be enabled by tying the DCS pin high.

The duty cycle stabilizer uses a delay locked loop to create non-sampling edges. Therefore, any change in sampling frequency takes about 2 μs to 3 μs for the DLL to acquire and settle to the new rate.

High-speed, high-resolution ADCs are very sensitive to the quality of the clock input. At a given full-scale input frequency (f), the SNR degradation due only to aperture jitter (t) can be calculated as:

In the equation, the rms aperture jitter, t, represents the root sum squared of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter specification. Undersampling applications are particularly sensitive to jitter.

For best performance, especially where aperture jitter can affect the dynamic range of the AD9248, it is important to minimize input clock jitter. The clock input circuit should use a stable reference; for example, use the analog power and ground planes to generate valid high and low numbers for the AD9248 clock input. The power supply for the clock driver should be separated from the ADC output driver power supply to avoid modulating the clock signal with digital noise. Low jitter, crystal controlled oscillators are the best clock sources. If the clock is generated from another type of source (by gating, division, or other methods), it should be retimed by the original clock in the last step.

Power Consumption and Standby Modes

The power consumption of the AD9248 is proportional to its sampling rate. Digital (DRVDD) power consumption is primarily determined by the strength of the digital drivers and the load on each output bit. Digital drive current can be passed through:

where N is the number of bits changed and C is the average load on the changed digital pins.

The analog circuits are optimally biased, so each speed grade provides excellent performance while reducing power consumption. Each speed grade dissipates baseline power at a low sampling rate that increases with increasing clock frequency.

Either channel of the AD9248 can enter standby mode independently by asserting the PDWN_A or PDWN_B pins.

Recommended input clock and analog input

Static during stand-alone or full standby, this will result in a typical power consumption of the ADC of 1 mW. Note that if DCS is enabled, the clocks for the independent power-down channels must be disabled. Otherwise, significant distortion will occur on the active channel. Typical power consumption of 12 mW is incurred if the clock input remains active in total standby mode.

When both channels are in full power down mode (PDWN_A = PDWN_B = HI). In this case, the internal reference will be closed. When one or both channel paths are enabled after a power-down, the wake-up time is directly related to the recharge of the REFT and REFB decoupling capacitors and the duration of the power-down. Typically, it takes about 5ms to restore full operation, fully discharging the 0.1µF and 10µF decoupling capacitors on the RFT and ReFB.

digital output

The AD9248 output driver can be configured to interface with 2.5V or 3.3V logic families by matching DRVDD to the digital supply of the interface logic. The output drivers are sized to provide enough output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the power supply, affecting converter performance. Applications that require the ADC to drive large capacitive loads or large sectorized outputs may require external buffers or latches.

The data format can be selected for offset binary or two's complement. See the Data Formats section for details.

opportunity

The AD9248 provides a latched data output with a pipeline delay of seven clock cycles. The data output is available one propagation delay (t) after the rising edge of the clock signal. See Figure 2 for a detailed timing diagram. The internal duty cycle stabilizer can be enabled on the AD9248 using the DCS pin. This provides a stable 50% duty cycle internal circuit.

The length of the output data lines and load should be minimized to reduce transients within the AD9248. These transients degrade the dynamic performance of the converter. The minimum typical conversion rate of the AD9248 is 1 ms. Dynamic performance may degrade when clock rates are below 1 ms/sec.

Individual channels can be turned off for modest power savings. The power-down channel shuts down the internal circuitry, but the reference buffer and shared reference remain powered. Wake-up time is reduced to a few clock cycles as the buffers and voltage reference remain powered.

Data Format

The AD9248 data output format can be configured as two's complement or offset binary. This is controlled by the data format selection pin (DFS). Connecting DFS to AGND produces offset binary output data. Conversely, connecting DFS to AVDD will format the output data as two's complement.

Output data from dual ADCs can be multiplexed onto a single 14-bit output bus. Multiplexing is accomplished by toggling the MUXYSELY bit, which directs channel data to the same or opposite channel data port. When MUX_SELECT is logic high, Channel A data is directed to the Channel A output bus and Channel B data is directed to the Channel B output bus. When MUX_SELECT is logic low, channel data is inverted, ie, channel A data is directed to the channel B output bus, and channel B data is directed to the channel A output bus. Multiplexed data can be used on either output data port by toggling the MUX_SELECT bit.

This clock can be applied to the MUX_SELECT pin if the adc is running with synchronous timing. Any skew between CLK_A, CLK_B, and MUX_SELECT will degrade AC performance. It is recommended to keep clock skew <100ps. After the rising edge of MUX_select, any data port has the data of its own channel; after the falling edge, the data of the spare channel is put on the bus. Typically, other unused buses will be disabled by setting the appropriate OEB high to reduce power consumption and noise. Figure 34 shows an example of the multiplexing mode. When multiplexing data, the data rate is twice the sample rate. Note that in this mode, both channels must remain active, and the power down pin of each channel must be held low.

voltage reference

The AD9248 has a built-in stable and accurate 0.5V voltage reference. The input range can be adjusted by varying the reference voltage applied to the AD9248 using an internal reference with different external resistor configurations or an externally applied reference voltage. The input range of the ADC tracks a linear change in the reference voltage. If the ADC is driven differentially through a transformer, the reference voltage can be used to bias the center tap (common mode voltage).

Shared reference mode allows the user to connect the reference from the dual ADCs externally for higher Table 7. Refer to Configuration Summary Gain and Offset Matching Performance. If the ADCs work independently, the reference decoupling can be handled independently and can provide better isolation between the dual channels. To enable shared reference mode, the shared reference pin must be tied high and the external differential reference must be shorted externally. (Reference A must be externally shorted to reference B, and reference A must be shorted to reference B.)

Internal reference connection

The comparator in the AD9248 senses the potential at the sense pin and configures the reference into four possible states, as shown in Table 7. If the sensor is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 35), setting VREF to 1 V. Connecting the sensor pin to VREF switches the reference amplifier output to the sensor pin, completing the loop and providing a 0.5 V reference output. As shown in Figure 36, if a resistive divider is connected, the switch is again set to the sense pin. This puts the reference amplifier in a non-vertical mode and the VREF output is defined as: VREF= 0.5 × (1 + R2/R1)

In all reference configurations, REFT and REFB drive the ADC core and establish its input range. The input range of the ADC is always equal to twice the reference pin voltage of the internal or external reference.

Xref Operations

An external reference may be required to improve the gain accuracy of the ADC or to improve thermal drift characteristics. When multiple ADCs are tracking each other, a single reference (internal or external) may be required to reduce gain matching errors to acceptable levels. A high-accuracy external reference can also be selected to provide lower gain and offset temperature drift. Figure 37 shows the typical drift characteristics of the internal reference in 1V and 0.5V modes. When the sense pin is tied to AVDD, internal references are disabled, allowing external references to be used. The internal reference buffer loads the external reference with an equivalent 7kΩ load. Internal buffers still generate positive and negative full-scale references (REFT and REFB) for the ADC core. The input span is always twice the reference voltage value; therefore, the external reference must be limited to 1 V maximum. If the internal reference of the AD9248 is used to drive multiple converters to improve gain matching, the reference loads of the other converters must be considered. Figure 38 depicts the effect of the load on the internal reference voltage.

AD9248 LQFP Evaluation Committee

The evaluation board supports the AD9238 and AD9248 and has five main parts: clock circuit, input, reference circuit, digital control logic, and output. Below is a description of each part. Table 8 shows the jumper settings and comment assumptions in the comment column.

The evaluation board requires four power connections to TB1: analog power for the DUT, power for the onboard analog circuits, power for the digital driver DUT, and power for the onboard digital circuits. It is recommended to use separate analog and digital supplies, with 3 V nominal on each supply. Each power supply is separate on board, and each IC includes the DUT, decoupled locally. All ground should be tied together.

Clock circuit

The clock circuit is designed for a low jitter sine wave source, AC coupled and level shifted before driving the 74VHC04 hex inverter chips (U8 and U9) whose output provides the clock to the part. Potentiometers (R32 and R31) on the horizontal shift circuit allow the user to vary the duty cycle as desired. The amplitude of the sine wave must be large enough to be within the trip point of the hexagonal inverter and within the power supply to avoid clipping noise. To ensure a 50% duty cycle inside the part, the AD9248-65 has an on-chip duty cycle stabilizer circuit that is enabled by inserting jumper JP11. The duty cycle stabilizer circuit can only be used when the clock frequency is higher than 40ms/sec.

Each channel has its own clock circuit, but usually both clock pins are driven by a 74VHC04 and solder jumper JP24 is used to connect the clock pins together. When the clock pins are connected together and only one 74VHC04 is used, the other channel's series termination resistor (R54 or R55, depending on which inverter is used) must be removed.

A data capture clock is created for each channel and sent to the output buffer for use in the data capture system when needed. Jumpers JP25 and JP26 are used to invert the data clock if necessary and can be used to debug data capture timing issues.

analog input

The AD9248 achieves best performance with differential inputs. The evaluation board has two input options for each channel, a transformer (XFMR) and an AD8138, both of which perform single-ended to differential conversion. XFMR has the best high-frequency performance, and the AD8138 is ideal for dc evaluation, low-frequency inputs, and differentially driving ADCs without loading a single-ended signal.

The common mode level of both input options is set to "mid-supply" by a resistive divider on the AVDD supply, but can also use (test points) TP12, TP13 (for AD8138s) and TP14, TP15 (for XFMRs) Overdriven by external power supply. For low distortion of the full-scale input signal when using the AD8138, place jumper JP17 and jumper JP22 in position B and place an external negative supply on the TP10 and TP11 test points.

For best performance, use a low-jitter input source and a high-performance bandpass filter after the signal source and before the evaluation board (see Figure 39). For XFMR input, use solder jumpers JP13 and JP14 for channel A and jumpers JP20 and JP21 for channel B. For the AD8138 input, use solder jumpers JP15 and JP16 for channel A and jumpers JP18 and JP19 for channel B. Remove all solder from unused jumper wires.

Reference circuit

The EV kit circuit allows the user to select the reference mode via a series of jumpers and to provide an external reference if necessary. See Table 9 for jumper settings for each reference mode. The external reference on the board is a simple resistor divider/zener diode circuit buffered by an AD822 (U4). POT (R4) can be used to change the level of the external reference to fine tune the ADC full scale.

digital control logic

The digital control logic on the evaluation board is a series of jumpers and pull-down resistors that serve as digital inputs on the AD9248 for the following pins: power-down and output-enable bars for each channel, duty-cycle recovery circuitry, dual-complement output mode, Shared reference mode and MUX_select pins. See Table 8 for jumper locations for normal operation.

output

The outputs of the AD9248 (and the data clock discussed earlier) are buffered by 74VHC541s (U2, U3, U7, U10) to ensure proper loading of the DUT outputs, and additional drive capability for the next part of the system. The 74VHC541s are latches, but on this evaluation board they are wired and act as buffers. If desired, jumper JP30 can be used to connect the data clocks together. If the data clock is bound, the R39 or R40 resistor must be removed, depending on the clock circuit used.

Thermal factor

The AD9248 LFCSP has an integrated thermal slug that, when locally connected to the ground plane of the PCB, improves the thermal and electrical performance of the package. A hot (filled) pass through the array to a ground plane under the part provides a path for the heat to escape the package, lowering the junction temperature. Improved electrical performance is also due to reduced package parasitics due to proximity to the ground plane. Recommended arrays are 0.3mm vias with 1.2mm pitch. θ=26.4°C/W with this recommended configuration. Soldering the slag to the printed circuit board is a requirement for this package.