feature

25 µsec max sample and convert; single supply +5V operation; 12-bit ADS7824 compatible pinout; parallel and serial data outputs; 28-pin 0.3" plastic dip and SOIC; ±2.0 LSB max; 50mW max power dissipation ; 50 microwatt power-down mode; ± 10V input range, four-channel multiplexer; continuous conversion mode.

illustrate

The ADS7825 can acquire 16 bits and convert them to a ±2.0 LSB maximum in 25 microseconds while consuming only up to 50 mW Laser-trimmed scaling resistors provide a standard industry ±10V input range with a channel matching of ±0.1 %. The ADS7825 is a quad-channel low-power 16-bit sampling A/D input multiplexer, S/H, clock, reference, and a parallel/serial microprocessor interface. It can be configured in continuous conversion mode to digitize all four channels sequentially. The 28-pin ADS7825 is fully specified in both 0.3-inch plastic dipping and SOIC for operation over the industrial –40°C to +85°C range.

Basic operation

Parallel output

Figure 1a shows the basic circuit for operating the ADS7825 with parallel outputs (channel 0 selected). A conversion will be initiated if R/C (Pin 22) is low for 40 ns (12 μs max). BUSY (pin 24) will go low and remain low until the conversion is complete and the output registers are updated. If the byte (pin21) is low, the 8 most significant bits will be active when pin 24 goes up; if the byte is high, the 8 least significant bits will be active when busy. Data will be output in binary two's complement format. Busy high can be used to lock data. After the first byte is read, the bytes can be switched to allow the remaining bytes to be read. When busy, all conversion commands will be ignored low.

The ADS7825 will begin tracking the input signal at the end of the conversion. Allow 25 microseconds between transition commands to ensure accurate acquisition of new signals.

Serial output

Figure 1b shows the basic circuit for operating the ADS7825 serial output (channel 0 selected). Setting R/C (pin 22) low for 40ns (12 microseconds max) will initiate a conversion and output valid data from the previous conversion on SDATA (pin 16), synchronized to 16 clock pulses of the data clock (pin 16). foot 15). BUSY (pin 24) will go low and remain low until the conversion is complete and serial data has been transferred. Data will be output in binary 2's complement format, MSB first, and on the rising and falling edges of the data clock. Busy high can be used to lock data. All conversion commands will be ignored while busy.

The ADS7825 will begin tracking the input signal at the end of the conversion. Allow 25 microseconds between transition commands to ensure accurate acquisition of new signals.

Start conversion The combination of CS (pin 23) and R/C (pin 22) is too low for at least 40ns to put the sample/hold of the ADS7825 in hold and start converting "n". BUSY (pin 24) will go low and remain low until conversion "n" is complete and the internal output registers have been updated. All new conversion commands during busy-low periods will be ignored. CS and/or R/C must go high before BUSY goes high, otherwise a new conversion will be initiated without enough time to acquire a new signal.

The ADS7825 will begin tracking the input signal at the end of the conversion. Allow 25 microseconds between transition commands to ensure accurate acquisition of new signals. Figures 2 to 6 and Table II are timing information CS and R/C are internally or horizontally triggered. when initiating the conversion. However, if CS or R/C initiates transition "n", make sure the lower critical input is at least 10ns before initiating the input. If EXT/INT (pin 12) is low when conversion "n" is initiated, the serial data for conversion "n–1" will be output to SDATA (pin 16) after conversion "n" begins. See Clock in Internal Data Read Data Area.

In order to reduce the number of control pins, the CS can be placed in a lower position to use R/C to control the read and transfer modes. This will not work when using the internal data clock in serial output mode. However, parallel outputs and serial outputs (only when using an external data clock) will be affected when R/C is high. See the Reading Data section and Figures 2, 3, 5, and 6.

read data

Parallel output

To use the parallel output, tie PAAR/SER (pin 20) high. When R/C (Pin 22) is high and CS (Pin 23) is low. Any other combination of CS and R/C will tri-state the parallel outputs. Valid conversion data can be read in two 8-bit bytes on D7-D0 (pins 9-13 and 15-17). When the byte (pin 21) is low, the 8 most significant bits are valid for the MSB on D7. When BYTE is HIGH, the 8 least significant bits are valid for the LSB on D0. Bytes can be switched to read two bytes in one conversion cycle. On initial power-up, the parallel outputs will contain indeterminate data.

Parallel output (after conversion)

Busy (pin 24) will go high after conversion "n" is complete and the output register has been updated. Valid data for transition 'n' will be available on D7-D0 (pins 9-13 and 15-17). Busy high can be used to lock data. See Table II and Figures 2 and 3 for timing constraints.

Parallel output (during conversion)

After starting conversion "n", valid data in conversion "n–1" can be read and valid for 12 microseconds after conversion "n" begins. Do not attempt to read data more than 12 microseconds after transition "n" begins until busy (pin 24) goes high; this may result in invalid data being read. See Table II and Figures 2 and 3 for timing constraints.

Serial output

When PAR/SER (PIN 20) is low, data can be serially synchronized to the internal data clock or to an external data clock. When EXT/INT (pin 12) is low, DATACLK (pin 15) is the output always active regardless of the state of CS (pin 23) and R/C (pin 22). When busy (pin 24) is low, the SDATA output is active. Otherwise, it is in a three-state condition. When EXT/INT is HIGH, DATACLK is an input.

The SDATA output is active when CS is low and R/C is high. Otherwise, it is tri-stated. Regardless of EXT/INT, the state of SYNC (pin 13) is an output and is always active, while TAG (pin 17) is always an input.

Internal data clock (during conversion)

To use the internal data clock, connect EXT/INT (pin 12) low.

A combination of R/C (Pin 22) and CS (Pin 23) low will initiate conversion 'n' and activate the internal data clock (typically 900kHz clock rate). The ADS7825 will output 16 bits of valid data (MSB first) from transition 'n–1' on SDATA (pin 16), synchronized to the 16 clock pulses output data clock (pin 15). Data is valid on both the rising and falling edges of the internal data clock. The rising busy edge (pin 24) can be used to lock data. After the 16th clock pulse, DATACLK will remain low until the next conversion begins, and SDATA will go into whatever logic level clock pulse is input on the tag (pin 17) during the first conversion. When BUSY returns to HIGH, the SDATA output will be tri-stated.

External data clock

To use an external clock, connect EXT/INT (pin 12) high. This external clock is not a conversion clock; it can only be used as a data clock. To enable the output mode of the ADS7825, CS (pin 23) must be low and R/C (pin 22) must be high. DATACLK must be as high as 20% to 70% of the total data clock period; the clock frequency can be between DC and 10MHz. Serial data from transition 'n' can be output on SDATA (pin 16) after transition 'n' is complete or during transition 'n+1'.

An obvious way to simplify converter control is to use the R/C to initiate conversions with CS low. While this is perfectly acceptable, problems can arise when using an external data clock. At an indeterminate point 12µs after the start of conversion 'n' until BUSY rises, the internal logic transfers the result of conversion 'n' to the output register. If CS is low and R/C is high, the external clock is high at this time, and the data will be lost. Therefore, with CS low, R/C and/or DATACLK must be low during this period to avoid loss of valid data.

External data clock (after conversion)

After conversion "n" is complete, the output register has been updated and busy (pin 24) will go high. With CS low (pin 23) and R/C high (pin 22), valid data from transition "n" will be output on SDATA (pin 16), synchronized to DATACLK (pin 15) external data clock input. Between 15 and 35 ns after the first external data clock rising edge, the sync output pin will go high for one full data clock cycle (at least 100 ns). The MSB is valid between 25 and 55ns after the rising edge of the second data clock. The LSB is valid on the 17th falling edge and the 18th rising edge of the data clock. The tag (pin 17) will input one bit of data per external clock pulse.

The first input on the label will be valid on SDATA on the 18th falling edge and 19th rising edge of DATACLK

The second input bit will be valid on the 19th falling edge, the 20th rising edge, etc. Under the continuous data clock, the tag data will be output on the data until the internal output register is updated according to the result of the next converter - Zion.

External data clock (during conversion)

After starting conversion "n", the valid data in conversion "n-1" can be read for up to 12 microseconds after conversion "n" starts. Do not attempt to clock data rising 12 microseconds from the start of transition "n" to busy (pin 24); this will result in data loss.

Notes For the best possible performance when using an external data clock, data should not be clocked during conversions. Switching noise from asynchronous data clocks can cause digital feedthrough and degrade converter performance. Timing information is shown in Table 2 and Figure 6.

Mark function

Tag (pin 17) input serial data synchronized to external or internal data clock. When using an external data clock, the serial bit stream input on the label will follow the LSB output on SDATA (pin 16) until the internal output register is updated with the new conversion result.

The logic level input on the label on the first rising edge of the internal data clock is valid on SDATA after all 16 bits of valid data have been output.

Multiplexer Timing

The four-channel input multiplexer can be manually addressed or placed in continuous conversion mode, where all four channels are addressed sequentially.

Continuous conversion mode (CONTC=5V)

To put the ADS7825 into continuous conversion mode, CONTC (pin 25) must be tied high. In this mode, acquisition and conversion will be continuous, looping

Pass all four channels as long as CS, R/C, and PWRD are low (see Table 3). The last loaded address goes into the A0 and A1 registers (pins 19 and 18, respectively) before CONTC is raised, becoming the first address in sequential sequential conversion mode (for example, if channel 1 is the last address selected, channel 2 will follow, then channel 3, and so on). When the device is in this mode, the A0 and A1 address inputs become outputs. When BUSY goes up at the end of a conversion, A0 and A1 will output the address of the channel that will be converted when BUSY goes low at the beginning of the next conversion. When busyness rises, the data of the previous channel will be valid. Channel selection timing in continuous conversion mode is shown in Table IVa and Figure 7.

PWRD (pin 26) can be used to reset the multiplexer address to zero. Since the ADS7825 is configured not to convert, the PWRD can be as high as at least 200ns. When PWRD returns low, the multiplexer address is reset to zero. When continuous conversion mode is enabled, the first conversion will be done on channel 0. Subsequent transitions will go through each higher channel, looping back to zero after channel 3.

If PWRD is held high for an extended period of time, the REF (pin 7) bypass capacitor may discharge (if using an internal reference) and the CAP (pin 6) bypass capacitor will discharge (for both internal and external references). Continuous conversion mode should not be enabled until the bypass capacitor is charged and stabilized (1 ms for a 2.2µF capacitor is recommended). Also, continuous conversion mode should not be enabled even with short pulses on PWRD until the minimum acquisition time is met.

The channel of the ADS7825 can be manually selected using the A0 and A1 address pins (pins 19 and 18, respectively). The multiplexer truth table is shown in Table IVb, and the channel selection timing is shown in Figure 8.

calibration

The ADS7825 has no internal provisions to correct for a single bipolar zero error or full scale error for each individual channel. Conversely, the bipolar zero error per channel is guaranteed to be less than fairly small for a 16-bit converter with a ±10V input range (slightly more than ±32lsb). Also, the channel errors should match each other within 16 lsb.

For full-scale error, the circuit in Figure 9 can be used. This will allow the reference to be adjusted so that the full-scale error of any single channel can be set to zero. Again, the close matching of the channels will ensure less full-scale error on the other channels.

refer to

The ADS7825 can operate with its internal 2.5V reference or with an external reference. The internal reference can be bypassed by applying an external reference to pin 7.

referee

REF (Pin 7) is the input for the external reference or the output for the internal 2.5V reference. The 2.2µF capacitor should be connected as close as possible to the reference pin. This capacitor and the output resistance of REF create a low-pass filter on the reference to limit noise. Using a smaller capacitor value will introduce more noise to the reference signal, thereby reducing the signal-to-noise ratio and the signal-to-noise ratio. The REF pin should not be used to drive external AC or DC loads.

The external reference is in the range of 2.3V to 2.7V and determines the actual LSB size. Increasing the reference voltage can increase the full-scale and LSB size of the converter, thereby improving the signal-to-noise ratio.

hat

CAP (pin 6) is the output of the internal reference buffer. The 2.2µF capacitor should be placed as close as possible to the cap pins to provide the best switching current for the CDAC throughout the conversion cycle. This capacitor also provides compensation for the output of the buffer. Using capacitors smaller than 1µF can cause the output buffer to oscillate and there may not be enough charge available for the CDAC. Capacitance values greater than 2.2µF have little effect on improving performance.

The output of the buffer is capable of driving up to 1 mA into a DC load. Using an external buffer will allow the internal reference to be used for larger DC and AC loads. Do not attempt to directly drive an AC load whose output voltage is capped. This will result in reduced converter performance.

pressurized water reactor

PWRD (pin 26) high will turn off all analog circuits including the reference. The previously converted data will be kept in the internal registers and can still be read. For PWRD HIGH, the convert command produces meaningless data. When PWRD returns low, sufficient time must be provided for the capacitors on REF (pin 7) and CAP (pin 6) to recharge. For a 2.2µF capacitor, it is recommended that the charge/settling time be at least 1 ms before the conversion result is considered valid.

layout

that power

90% of the power of the ADS7825 is used in the analog circuit and the converter should be considered an analog component. For best performance, connect both power pins to the same +5V supply, and connect the analog and digital grounds together.

The +5V supply for the converter should be separate from the +5V supply for the system digital logic. Connecting VS1 and VS2 (pins 28 and 27) directly to the digital power supply can degrade converter performance due to switching noise from the digital logic. For best performance, the +5V supply can be generated from any analog supply used for analog signal conditioning. A simple +5V regulator can be used if a +12V or +15V supply is present. While it is not recommended to use a digital power supply to power the converter, make sure the power supply is properly filtered. Whether using a filtered digital supply or a regulated analog supply, VS1 and VS2 should be connected to the same +5V supply.

ground

There are three ground pins on the ADS7825. DGND is the digital power ground. AGND2 is the analog power ground. AGND1 is the ground referenced to all A/D internal analog signals. AGND1 is more susceptible to current induced voltage drops and must have a minimal resistive path back to the power supply.

All ground pins of the A/D should be tied to the analog ground plane and separated from the system's digital logic ground for best performance. Both analog and digital ground planes should be connected to the "system" ground as close to the power supply as possible. This helps prevent dynamic digital ground currents from modulating analog ground to power ground through the common impedance.

crosstalk

The worst-case channel-to-channel crosstalk versus input frequency is shown in the Typical Performance Curves section of this datasheet. The worst-case crosstalk on the ADS7825 is better than -115dB for a full-scale 1kHz input signal. This should be enough for the most demanding applications. However, if crosstalk is an issue, the following should be kept in mind: The worst crosstalk is usually from channel 3 to channel 2. Furthermore, the crosstalk from channel 3 to any other channel is worse than the crosstalk from those channels to channel 3. The reason is that channel 3 is closer to the reference signal on the ADS7825. This allows two coupling modes: channel to channel and channel 3 to reference. In general, avoid placing signals with higher frequency components on channel 3 when crosstalk is an issue.

The worst-case crosstalk occurs from channel 3 to channel 2, as shown in the crosstalk versus input frequency plot in the Typical Performance Curve section. Other adjacent channels are usually a few decibels better than this, and non-adjacent channels are usually 10 decibels better. If a particular channel should avoid crosstalk as much as possible, channel 0 will be the best channel for the signal and channel 1 should have the signal with the lowest frequency content. If you want the two signals to have as little crosstalk as possible, you should place them on channel 0 and channel 2, and use lower frequency, less sensitive inputs on the other channels.

If crosstalk is a concern for all channels, remember that the crosstalk graph shows the crosstalk between any two channels. The total crosstalk for any given channel is the sum of the crosstalk contributions from all other channels. Since the contributions of non-adjacent channels are small, their contributions are usually negligible. A good approximation for absolute worst-case crosstalk is to add 6dB to the highest curve shown in the crosstalk vs. input frequency plot.

signal conditioning

In many CMOS A/D converters, the FET switches used for sample and hold release a large amount of charge injection, which can cause the drive op amp to oscillate. The charge injection due to the sampling FET switches on the ADS7825 is about 5-10% of the amount on an ADC with a similar structure to a charge redistribution DAC (CDAC). There is also a resistive front end that attenuates any charge released. The end result is a minimum requirement for the drive capability of the signal conditioning prior to A/D. In the application, any op amp large enough to drive the signal is sufficient to drive the ADS7825.

The resistive front end of the ADS7825 also provides guaranteed ±15V overvoltage protection. In most cases, this eliminates the need for an external overvoltage protection circuit.

middle latch

The ADS7825 has tri-stated outputs for the parallel port, but if the bus is active during conversion, an intermediate latch should be used. The tri-state output can be used to isolate the A/D from other peripherals on the same bus if the bus is not active during the conversion process.

The intermediate latch is good for any monolithic A/D converter. The internal LSB size of the ADS7825 is 38µV. Transients resulting from fast switching signals on the parallel port, even when the A/D is tri-stated, can couple through the substrate to the analog circuitry, resulting in degraded converter performance.

With the ADS7825 properly laid out, grounded, and bypassed, the effect could be some LSB errors. In some cases, this error can be seen as an increase in converter noise and simply averaged. In other cases, the error may not be random, and even an average value will create an error in the transformation result. Poor grounding, poor bypassing, and high-speed digital signals can increase the size of the error—perhaps to tens of LSBs.