General Instructions

The ADSP-2183 is a microcontroller optimized for digital signal processing (DSP) and other high-speed digital processing applications.

The ADSP-2183 combines the basic architecture of the ADSP-2100 series (three computational units, data address generator, and program sequencer) with two serial ports, 16-bit internal DMA port, one byte DMA port, a programmable timer, Flag I/O, extensive interrupt capability, and on-chip program and data memory are combined.

The ADSP-2183 integrates 80K bytes of on-chip memory, configured as 16K words (24 bits) of program RAM and 16K words (16 bits) of data RAM. Power-down circuits are also provided to meet the low-power requirements of battery-powered portable devices. The ADSP-2183 has 128 lead LQFP and 144 fans in your BGA package.

In addition, the ADSP-2183 supports new instructions including bit manipulation bit set, bit clear, bit toggle, bit test - new ALU constant, new multiply instruction (X squared), offset rounding, resultless ALU operations, I/O Memory transfers and global interrupt masking for added flexibility.

The ADSP-2183 is fabricated in a high-speed, bi-metal, low-power CMOS process with an instruction cycle of 19ns. Each instruction can be executed in one processor cycle.

The flexible architecture and comprehensive instruction set of the ADSP-2183 allow the processor to execute multiple operations in parallel. In one processor cycle, the ADSP-2183 can:

(1), generate the next program address;

(2), get the next instruction;

(3), perform one or two data movements;

(4), update one or two data address pointers;

(5), perform a calculation operation.

When the processor continues:

(1) Receive and transmit data through two serial ports;

(2) Receive and/or transmit data through the internal DMA port;

(3) Receive and/or transmit data through the byte DMA port;

(4), decrement timer.

development system

ADSP-2100 series development software is a complete set of software and hardware system development tools, supporting ADSP-2183. The assembler has an algebraic syntax for easy programming and debugging. The linker merges object files into executable files. The simulator provides an interactive instruction-level simulation with a reconfigurable user interface to display different parts of the hardware environment.

EZ-KIT Lite is a hardware/software kit that provides a complete development environment for the ADSP-21xx family: an ADSP-2189M evaluation board with PC monitoring software and assembler, connectors, simulator and PROM split device software. The ADSP-2189M evaluation board is a low-cost, easy-to-use hardware platform on which you can quickly start your DSP software design. EZ-KIT Lite includes the following features:

(1), 35.7 MHz ADSP-2189M;

(2), full 16-bit stereo audio input/output with AD73322 codec;

(3), RS-232 interface;

(4) EZ-ICE connector for emulator control;

(5) Demonstration program of digital signal processor;

(6), VisualDSP evaluation kit.

The ADSP-218x EZ-ICE® emulator facilitates hardware debugging of ADSP-218x systems. The ADSP-218x integrates on-chip emulation support and a 14-pin ICE port interface. Compared to other ADSP-2100 Series EZ ICEs, this interface provides a simpler target board connection that requires fewer mechanical clearance considerations. When using the EZ-ICE, the ADSP-218x device does not need to be removed from the target system, nor does it require any adapters. Due to the small footprint of the EZ-ICE connector, simulation can be supported in the final board design.

EZ-ICE performs a full suite of functions, including:

(1), in the target operation

(2), up to 20 breakpoints

(3), single step or full speed operation

(4), can check and change register and memory values

(5), PC upload and download function

(6) Instruction-level simulation of program guidance and execution

(7), complete assembly and disassembly instructions

(8), C source code level debugging

Additional Information

This data sheet outlines the capabilities of the ADSP-2183. For more information on the processor's architecture and instruction set, see the ADSP-2100 Series User's Manual Third Edition. For more information on development tools, see the ADSP-2100 Series Development Tools Data Sheet.

Architecture Overview

The ADSP-2183 instruction set provides flexible data movement and multifunction (one or two data move with computation) instructions. Each instruction can be executed in one processor cycle. The ADSP-2183 assembly language uses an algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development.

Figure 1 is the overall block diagram of the ADSP-2183. The processor contains three independent computational units: arithmetic unit, multiplier/accumulator (MAC), and shifter. The calculation unit directly handles 16-bit data and has provisions to support multi-precision calculations. The ALU performs a standard set of arithmetic and logical operations; division primitives are also supported. The MAC performs single-cycle multiply, multiply/add, and multiply/subtract operations, accumulating 40 bits. Shifters perform logical and arithmetic shifts, normalization, denormalization, and derived exponentiation operations. Shifters can efficiently implement digital format control including multi-word and block floating-point representations.

The internal result (R) bus connects the computational units so that the output of any unit can be the input of any unit in the next cycle.

The ADSP-21xx family of DSPs includes a shadow register for single-cycle context switching of the processor.

A powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these computational units. The sequencer supports conditional jumps, subroutine calls, and single-cycle returns. Using an internal loop counter and loop stack, the ADSP-2183 executes loop code with zero overhead; no explicit jump instructions are required to maintain loops.

Two data address generators (DAGs) provide addresses for fetching dual operands from data memory and program memory simultaneously. Each DAG maintains and updates four address pointers. Whenever data is accessed using a pointer (indirect addressing), it is post-modified by the value of one of the four possible modified registers. A length value can be associated with each pointer to enable automatic modulo addressing for circular buffers.

Efficient data transfer is achieved through the use of five internal buses:

(1), program memory address (PMA) bus

(2) Program memory data (PMD) bus

(3), data memory address (DMA) bus

(4), data storage data (DMD) bus

(5), result (R) bus

Two address buses (PMA and DMA) share an external address bus, allowing memory to expand off-chip, and two data buses (PMD and DMD) share an external data bus. The byte memory space and the I/O memory space also share the external bus.

Program memory can store both instructions and data, allowing the ADSP-2183 to fetch two operands in one cycle, one from program memory and one from data memory. The EZ-ICE and SoundPort are registered trademarks of Analog Devices, Inc.

The ADSP-2183 can fetch an operand from program memory and fetch the next instruction in the same cycle. In addition to the address and data buses for external memory connections, the ADSP-2183 has a 16-bit internal DMA port (IDMA port) for connecting to external systems. The IDMA port consists of 16 data/address pins and 5 control pins. The IDMA port provides transparent, direct access to the DSPs' on-chip program and data RAMs.

The byte DMA port (BDMA port) provides a low-cost byte-wide memory interface. The BDMA port is bidirectional and can directly address up to 4 Mbytes of external RAM or ROM for off-chip storage of program overlays or data tables.

Byte memory and I/O memory space interfaces support slow memory and I/O memory mapped peripherals with programmable wait state generation. External devices can gain control of the external bus through the bus request/grant signals (BR, BGH, and BG). One execution mode (Go mode) allows the ADSP-2183 to continue running from on-chip memory. Normal execution mode requires the processor to be stopped when the bus is granted.

The ADSP-2183 can respond to 13 possible interrupts, 11 of which can be accessed at any given time. There can be up to six external interrupts (one edge-sensitive, two level-sensitive, and three configurable) and seven internal interrupts generated by timers, serial ports (motion), byte DMA ports, and power-down circuitry. There is also a master reset signal.

These two serial ports provide a complete synchronous serial interface with optional companding in hardware, and various modes of operation for framed or unframed data transmission and reception. Each port can generate an internal programmable serial clock or accept an external serial clock.

The ADSP-2183 provides up to 13 general purpose flag pins. The data input and output pins on SPORT1 can also be configured as input flags and output flags. In addition, eight flags can be programmed as inputs or outputs, and three flags are always outputs.

A programmable interval timer generates periodic interrupts. The 16-bit count register (TCOUNT) is decremented every n processor cycles, where n is the scaled value stored in the 8-bit register (TSCALE). When the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from the 16-bit period register (TPERIOD).

serial port

The ADSP-2183 contains two complete synchronous serial ports (SPORT0 and SPORT1) for serial communication and multiprocessor communication.

The following is a list of features of the ADSP-2183 Motion Edition. For more information, please refer to the third edition of the ADSP-2100 Series User Manual.

(1) The movement is bidirectional, with a separate, double-buffered transmit and receive section.

(2), SPORTs can use external serial clock, or can generate line serial clock internally.

(3) Sports has an independent frame in the receiving and transmitting parts. Some operate in frameless mode, or generate frame sync signals internally or externally. The frame sync signal is high or inverted and has two pulse widths and timings.

Pin function description

These ADSP-2183 pins can only be connected to the EZ-ICE connector in the target system. These pins have no function except during simulation and do not require pull-up or pull-down resistors.

interrupt

The interrupt controller allows the processor to respond to 11 possible interrupts and resets with minimal overhead. The ADSP-2183 provides four dedicated external interrupt input pins IRQ2, IRQL0, IRQL1 and IRQE. In addition, SPORT1 can also be reconfigured as IRQ0, IRQ1, FLAG-In and Exit, for a total of six external interrupts. The ADS-2183 also supports timers, a byte DMA port, two serial ports, software and internal interrupts for power-down control circuitry. Interrupt levels are prioritized internally and can be masked individually (except power down and reset). The IRQ2, IRQ0, and IRQ1 input pins can be programmed to be level or edge sensitive. IRQL0 and IRQL1 are level sensitive and IRQE is edge sensitive. Priority and vector addresses of all interrupts.

Interrupt routines can be nested, with higher priority interrupts taking precedence, or processed sequentially. Interrupts can be masked or masked with the IMASK register. A single interrupt request is logically ANDed with the bits in IMASK; the highest priority unmasked interrupt is then selected. Power interruptions are not allowed.

After executing an instruction that modifies the IMASK register, the ADSP-2183 masks all interrupts for one instruction cycle. This does not affect serial port automatic buffering or DMA transfers.

The interrupt control register ICNTL controls interrupt nesting and defines IRQ0, IRQ1 and IRQ2 external interrupts as edge or level sensitive. The IRQE pin is an external edge-sensitive interrupt that can be forced and cleared. The IRQL0 and IRQL1 pins are external level sensitive interrupts.

The IFC register is a write-only register used to force and clear interrupts.

The on-chip stack preserves processor state and is automatically maintained during interrupt processing. The stack is 12 levels deep, allowing interrupts, loops and subroutine nesting.

The following instructions allow interrupt servicing (including power down) to be globally enabled or disabled, regardless of the state of IMASK. Disabling interrupts does not affect serial port autobuffering or DMA.

cancel; cancel;

Interrupt servicing is enabled when the processor is reset.

low power operation

The ADSP-2183 has three low-power modes that significantly reduce power consumption when the device is operating in standby. These modes are: Power Off; Idle; Slow Idle. The CLKOUT pin can also be disabled to reduce external power consumption.

power outage

The ADSP-2183 processor has a low-power function that enables the processor to enter a very low-power sleep state through hardware or software control. Below is a brief list of power-off functions. For details on the power-down function, see the "System Interfaces" chapter of the ADSP-2100 Series User Manual, Edition 3.

(1) Quick recovery after power failure. The processor starts executing instructions at 300 clock cycles.

(2), support externally generated TTL or CMOSprocessor clock. The external clock can continue to run during power outages without affecting the minimum power rating and 300 clock cycle recovery.

(3) Support for crystal operation includes disabling the oscillator to save power (the processor automatically waits 4096 CLKIN cycles for the crystal oscillator to start and stabilize), and allowing the oscillator to run to allow 300 CLKIN cycles to start.

(4) Power-off is initiated by power-off pin (PWD) or software power-off force bit.

(5) Interrupt support allows an unlimited number of instructions to be executed before selective power down. Power-down interrupts can also be used as non-maskable edge-sensitive interrupts.

(6), the context clear/save control allows the processor to continue to shut down in a power-off state or start with a clean context.

(7), the reset pin can also be used to terminate the power-off.

(8) The shutdown confirmation pin indicates when the processor enters the shutdown state.

idle

When the ADSP-2183 is in idle mode, the processor waits indefinitely in a low-power state until an interrupt occurs. When an unmasked interrupt occurs, it is serviced; then execution continues with the instruction following the idle instruction.

local

Enhanced idle instructions on the ADSP-2183 slow down the processor's internal clock signal, further reducing power consumption. The reduced clock frequency is a programmable portion of the normal clock frequency, specified by an optional divisor given in the idle instruction. The format of the instruction is

free(n); where n = 16, 32, 64, or 128. This instruction keeps the processor fully functional, but running at a slower clock speed. While it is in this state, the processor's other internal clock signals, such as SCLK, CLKOUT, and the timer clock, are reduced by the same ratio. When no clock divisor is given, the default form of the instruction is the standard idle instruction.

When the IDLE(n) instruction is used, it effectively lowers the processor's internal clock and thus reduces the response time to incoming interrupts. The one-cycle response time of the standard idle state is increased by a divisor of n clocks. When an enable interrupt is received, the ADSP-2183 will remain idle until a maximum of N processor cycles (n=16, 32, 64 or 128) before resuming normal operation.

When using idle (n) instructions in a system with an externally generated serial clock (SCLK), the serial clock rate may be faster than the processor's reduced internal clock rate. Under these conditions, interrupts cannot be generated at a faster rate than servicing, due to the extra time the processor takes to come out of idle (maximum N processor cycles).

system interface

Figure 2 shows a typical basic system configuration, including the ADSP-2183, two serial devices, a byte-wide EPROM, and optional external program and data overlay memory. Programmable wait state generation allows the processor to easily connect to slower peripherals. The ADSP-2183 also provides four external interrupts and two serial ports or six external interrupts and one serial port.

clock signal

The ADSP-2183 can be clocked by a crystal or TTL compatible clock signal.

The CLKIN input cannot be stopped, changed during operation, or run below the specified frequency during normal operation. The only exception is when the processor is powered off. For more information, see Chapter 9, ADSP-2100 Series User Manual, Third Edition, for details on this power-down feature.

If an external clock is used, it should be a TTL compatible signal running at half the instruction rate. The signal is connected to the CLKIN input of the processor. When using an external clock, the external input must be left unconnected.

The frequency of the input clock used by the ADSP-2183 is equal to half the instruction rate; an input clock of 16.67mhz yields 30ns of processor cycles (equivalent to 33mhz). Typically, instructions are executed in one processor cycle. All device timings are relative to the internal command clock rate, indicated by the CLKOUT signal when enabled.

Since the ADSP-2183 includes an on-chip oscillator circuit, an external crystal can be used. The crystal should be connected through the CLKIN and XTAL pins, with the two capacitors connected as shown in Figure 3. The capacitance value depends on the crystal type and should be specified by the crystal manufacturer. A parallel resonant, fundamental frequency, microprocessor grade crystal should be used.

The clock output (CLKOUT) signal is generated by the processor at the processor's cycle rate. This can be enabled and disabled via the CLKODIS bit in the SPORT0 Auto Buffer Control register.

reset

The reset signal initiates the master reset of the ADSP-2183. The reset signal must be asserted during the power-up sequence to ensure proper initialization. The reset during initial power-up must be held long enough for the internal clock to stabilize. If a reset is initiated at any time after power-up, the clock continues to run and no stabilization time is required.

The power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid VDD is applied to the processor, and the total time required for the internal Phase Locked Loop (PLL) to lock to a specific crystal frequency. A minimum of 2000 CLKIN cycles ensures that the PLL is locked, excluding the crystal oscillator start-up time. During this power-up sequence, the reset signal should be held low. On any subsequent resets, the reset signal must meet the minimum pulse width specification tRSP.

The reset input contains some hysteresis; however, if an RC circuit is used to generate the reset signal, an external Schmitt trigger is recommended.

A master reset sets all internal stack pointers to an empty stack condition, masks all interrupts and clears the MSTAT register. When RESET is released, if there are no pending bus requests and the chip is configured to boot (MMAP=0), the bootload sequence is performed. After boot loading is complete, the first instruction is fetched from the on-chip program memory location 0x0000.

memory structure

The ADSP-2183 offers a variety of memory and peripheral interface options. Key functional groups include program memory, data memory, byte memory, and I/O.

Program memory is a 24-bit wide space used to store instruction opcodes and data. The ADSP-2183 chip has 16K words of program memory RAM and can access two 8K external memory overlays using an external data bus. Both instruction opcodes and data values can be read from on-chip program memory in one cycle.

Data memory is a 16-bit wide space used to store data variables and memory-mapped control registers. The ADSP-2183 has 16K words in on-chip data memory RAM, consisting of 16352 user-accessible locations and 32 memory-mapped registers. Support also exists for up to two 8K external memory overlay spaces via the external data bus.

Byte memory provides access to an 8-bit wide memory space through the Byte DMA (BDMA) port. The byte memory interface utilizes eight data lines as additional address lines, providing access to 4mbytes of memory. This provides a valid 22-bit address range for the BDMA port. After power up, the DSP can automatically load boot code from byte memory.

The I/O space allows access to 2048 16-bit wide data locations. It is used to communicate with parallel peripherals such as data converters and external registers or latches.

program memory

The ADSP-2183 contains a 16K×24 on-chip program RAM. The on-chip program memory is designed to allow up to two accesses per cycle so that all operations can be completed in one cycle. Additionally, the ADSP-2183 allows the use of 8K external memory overlays.

The program memory space is organized by the MMAP pin and the PMOVLAY register. Usually, the ADSP2183 is configured as MMAP=0, and the program memory organization is shown in Figure 4.

When the PMOVLAY register is set to 0, 16K words of memory can be accessed internally. When PMOVLAY is set to a value other than 0, external accesses occur at addresses 0x2000 to 0x3FFF.

This organization provides two outer 8K coverage segments using only the normal 14 address bits. This allows for simple program coverage using one of two external segments instead of on-chip memory. Care must be taken when using this overlay space, as the PMOVLAY register value is not considered by the processor core (ie the sequencer). For example, if a looping operation occurs on one outer overlay, and the program changes to another outer overlay or internal memory, an incorrect looping operation may occur. Also, care must be taken in interrupt service routines, as overlay registers are not automatically saved and restored on the processor mode stack.

For ADSP-2100 series compatibility, MMAP=1 is allowed. In this mode, boot and overwrite memory are disabled (PMOVLAY must be 0). Figure 5 shows the memory map in this configuration.

data storage

The ADSP-2183 has an internal data memory of 16352 16-bit words. Additionally, the ADSP-2183 allows the use of 8K external memory overlays. Figure 6 shows the organization of the data memory.

When the DMOVLAY register is set to 0, 16352 words of memory can be accessed internally. When DMOVLAY is set to non-zero, external accesses occur at addresses 0x0000 to 0x1FFF.

This organization only allows two external 8K overlays with the normal 14 address bits.

All internal accesses are completed in one cycle. Accesses to external memory are timed using the wait states specified by the DWAIT register.

I/O space

The ADSP-2183 supports additional external memory space called I/O space. This space is designed to support simple connections to peripherals or bus interface ASIC data registers. The I/O space supports 2048 locations. Use the lower 11 bits of the external address bus; the upper 3 bits are undefined. Two instructions have been added to the core ADSP-2100 family instruction set for reading and writing to the I/O memory space. The I/O space also has four dedicated 3-bit wait state registers, IOWAIT0-3, which specify up to seven automatically generated wait states for each of the four regions.

Composite Memory Selection (CMS)

The ADSP-2183 has programmable memory select signals for generating memory select signals for memory mapped to multiple spaces. The generated CMS signal has the same timing as each individual memory select signal (PMS, DMS, BMS, IOMS), but their functions can be combined.

When set, each bit in the CMSSEL register causes the CMS signal to be asserted when the selected memory selection is asserted. For example, to use 32K words of memory for program and data memory, set the PMS and DMS bits in the CMSSEL register and use the CMS pin to drive the memory's chip select; use DMS or PMS as additional address bits.

The CMS pin functions similarly to other memory select signals, with the same timing and bus request logic. A 1 in the enable bit causes the assertion of the CMS signal at the same time as the selected memory select signal. Except for the BMS bit, all enable bits default to 1 at reset.

byte memory

Byte memory space is a bidirectional, 8-bit wide external memory space used to store programs and data. Byte memory is accessed using the BDMA feature. The byte storage space is 256 pages, each page is 16K×8.

The byte memory space on the ADSP-2183 supports read and write operations as well as four different data formats. Byte memory uses data bits 15:8 for data. Byte memory uses data bits 23:16 and address bits 13:0 to create a 22-bit address. This allows up to 4meg x 8 (32megabit) of ROM or RAM to be used without glue logic. All byte memory accesses are clocked by the BMWAIT register.

Byte Memory DMA (BDMA)

The byte memory DMA controller allows the use of the byte memory space to load and store program instructions and data. The BDMA circuit is able to access the byte memory space while the processor is operating normally and steal only one DSP cycle per 8, 16 or 24-bit word transfer.

The BDMA circuit supports four different data formats selected by the BTYPE register field. Make the appropriate number of 8-bit accesses from the byte memory space to generate the chosen word size. Table V shows the data formats supported by the BDMA circuit.

Unused bits in the 8-bit data memory format are padded with 0s. The BIAD register field is used to specify the starting address of the on-chip memory associated with the transfer. The 14-bit magnetic bead register specifies the starting address of the external byte memory space. The 8-bit BMPAGE register specifies the starting page of the external byte memory space. The BDIR register field selects the direction of the transfer. Finally, the 14-bit BWCOUNT register specifies the number of DSP words to transfer and initiates the BDMA circuit transfer.

During sequential addressing, BDMA accesses can cross page boundaries. A BDMA interrupt is generated when the number of transfers specified by the BWCOUNT register is complete. The BWCOUNT register is updated after each transfer, so it can be used to check the status of the transfer. When it reaches zero, the transfer is complete and a BDMA interrupt is generated. During BDMA operations, the DSP must not access the BMPAGE and bead registers.

The source or destination of a BDMA transfer will always be on-chip program or data memory, regardless of MMAP, PMOVLAY, or DMOVLAY.

When the BWCOUNT register is written with a non-zero value, the BDMA circuit begins to perform byte memory accesses and the wait state is set by BMWAIT. These visits will continue until the count reaches zero. When there are enough accesses to generate a destination word, it is transferred to or from the on-chip memory. The transfer requires one DSP cycle. DSP accesses to external memory take precedence over BDMA byte memory accesses.

The BDMA Context Reset bit (BCR) controls whether the processor is delayed while making BDMA accesses. Setting the BCR bit to 0 allows the processor to continue operating. Setting the BCR bit to 1 causes the processor to stop execution when a BDMA access occurs to clear the processor's context and begin execution at address 0 when the BDMA access completes.

Memory DMA Port (IDMA Port) The IDMA port provides an efficient means of communication between the host system and the ADSP-2183. This port is used to access the DSP's on-chip program memory and data memory with an overhead of only one DSP cycle per word. However, the IDMA port cannot be used to write to the DSP's memory-mapped control registers.

The IDMA port has a 16-bit multiplexed address and data bus and supports 24-bit program memory. The IDMA port is fully asynchronous and can be written to while the ADSP-2183 is running at full speed.

DSP memory addresses are locked and then auto-incremented after each IDMA transaction. Therefore, external devices can access blocks of sequentially addressed memory by specifying only the starting address of the block. This increases throughput because addresses don't have to be sent for every memory access.

IDMA port access occurs in two stages. The first is the IDMA address latch cycle. When acknowledgment is asserted, the 14-bit address and 1-bit destination type can be driven onto the bus by an external device. The address specifies the on-chip memory location; the target type specifies whether it is a DM or PM access. The falling edge of the address latch signal latches this value into the IDMAA register.

Once the address is stored, data can be read from or written to the ADSP-2183's on-chip memory. The assertion select line (IS) and the appropriate read and write lines (IRD and IWR, respectively) signal the ADSP-2183 that a specific transaction is required. In both cases, synchronization has a process or cycle delay. A memory access consumes one additional processor cycle.

Once an access occurs, the latched address will automatically increment and another access may occur.

Through the IDMAA register, the DSP can also specify the starting address and data format of the DMA operation.

bootloader (boot)

The ADSP-2183 has two mechanisms that allow automatic loading of on-chip program memory after reset. The boot method after reset is controlled by the MMAP and BMODE pins.

BDMA boot

When the BMODE and MMAP pins specify BDMA boot (MMAP=0, BMODE=0), the ADSP-2183 initiates the BDMA boot sequence when reset is released. When BDMA boot is specified, the BDMA interface is set during reset to the following defaults: the BDIR, BMPAGE, BIAD, and bead registers are set to 0, the BTYPE register is set to 0 to specify a 24-bit word of program memory, and the BWCOUNT register is set to 32. This will cause 32 words of on-chip program memory to be loaded from byte memory. These 32 words are used to set up the BDMA to load into the rest of the program code. The BCR bit is also set to 1, which will cause program execution to be delayed until all 32 words are loaded into the on-chip program memory. Then start execution from address 0.

The ADSP-2100 series development software (version 5.02 and later) fully supports the BDMA boot function and can generate byte memory space compatible boot code. Idle instructions can also be used to allow the processor to suspend execution while continuing to boot over the BDMA interface.

IDMA boot

The ADSP-2183 can also be booted through its internal DMA port. If BMODE=1, MMAP=0, the ADSP-2183 boots from the IDMA port. The IDMA function can load as much on-chip memory as needed. Program execution is delayed until the onchip program memory location 0 is written.

The ADSP-2100 series development software (version 5.02 and later) can generate IDMA-compatible startup code.

Bus Application and Bus Grant

The ADSP-2183 can hand over control of the data and address bus to an external device. When an external device needs to access memory, it asserts the bus request (BR) signal. If the ADSP-2183 does not perform external memory accesses, during the following processor cycles it responds to active BR inputs by: three descriptive data and address buses and PMS, DMS, BMS, CMS, IOMS, RD, WR outputs The driver, asserts the bus grant (BG) signal, and stops program execution.

If Go mode is enabled, the ADSP-2183 does not halt program execution until it encounters an instruction that requires external memory access.

If the ADSP-2183 is performing an external memory access when the external device asserts the BR signal, it will not assert the memory interface three times or assert the BG signal until the processor cycle after the access is complete. When the bus is granted, there is no need to complete the instruction. If an instruction requires two external memory accesses, the bus will be granted between the two accesses. When the BR signal is released, the processor releases the BG signal, re-enables the output driver, and resumes program execution from where it left off.

The bus request function always works, including when the processor is started and reset is active.

When the ADSP-2183 is ready to execute an instruction, the BGH pin is asserted, but stopped because the external bus has been granted to another device. Another device can release the bus by releasing the bus request. Once the bus is released, the ADSP-2183 will deassert the BG and BGH and perform external memory accesses.

Label I/O pins

The ADSP-2183 has eight general-purpose programmable input/output flag pins. They are controlled by two memory mapped registers. The PFTYPE register determines the direction, 1=output, 0=input. The PFDATA register is used to read and write values on the pins. Data read from pins configured as inputs is synchronized to the clock of the ADSP-2183. Bits programmed as outputs will read the value being output. The PF pin defaults to an input at reset.

In addition to the programmable flags, the ADSP-2183 has five fixed mode flags, FLAG-In, FLAG-OUT, FL0, FL1, and FL2. FL0-FL2 are dedicated output flags. FLAG_IN and FLAG_OUT are provided as an alternative configuration for SPORT1.

Instruction set description

The ADSP-2183 assembly language instruction set has an algebraic syntax designed for ease of coding and readability. Assembly language takes full advantage of the processor's unique architecture and provides the following benefits:

(1), algebraic syntax does not need to remember password assembly mnemonics. For example, a typical arithmetic addition instruction (such as AR=AX0+AY0) resembles a simple equation.

(2) Each instruction is assembled into a 24-bit word, which can be executed in one instruction cycle.

(3) The syntax is a superset ADSP-2100 series assembly language, which is fully compatible with other series members in source code and object code. Programs may need to be relocated to utilize on-chip memory and conform to the ADSP2183's interrupt vector and reset vector maps.

(4) Provide 16 condition codes. For conditional jump, call, return, or arithmetic instructions, the condition can be checked and the operation performed in the same instruction cycle.

(5) The multi-function instruction allows parallel execution of an arithmetic instruction in one instruction cycle, fetching at most two times or writing to the processor memory space once.

Design of EZ-ICE Compatible System

The ADSP-2183 has on-chip emulation support and ICEPort, a special set of pins that interface with the EZ-ICE. These features allow in-circuit emulation without replacing the target system processor by using only the 14-pin connection from the target system to the EZ-ICE. The target system must have a 14-pin connector to accept the EZ-ICE's in-circuit probe, a 14-pin header.

The ICE port interface consists of the following ADSP-2183 pins: EBR EBG ERESET; EMS EINTECLK; ELIN ELOUT EE.

These ADSP-2183 pins can only be connected to the EZ-ICE connector in the target system. These pins have no function except during simulation and do not require pull-up or pull-down resistors. The traces of these signals between the ADSP2183 and the connector must be as short as possible, no more than 3 inches.

The EZ-ICE also uses the following pins: ;BR BG; RESETGND.

EZ-ICE uses the EE (Emulator Enable) signal to control the ADSP-2183 in the target system. This causes the processor to use its ERESET, EBR, and EBG pins instead of its RESET, BR, and BG pins. The BG output is three states. These signals do not require jumper isolation in the system.

The EZ-ICE connects to the target system via a ribbon cable and a 14-pin female plug. The ribbon cable is 10 inches long and one end is attached to the EZ-ICE. The female header plugs into the 14-pin connector (one pin header) on the target board.

EZ-ICE probe target board connector EZ-ICE connector (standard pin with header) is shown in Figure 7. This connector must be added to the target board design if the EZ-ICE is to be used. Make sure there is enough space in the system to mount the EZ-ICE probe to the 14-pin connector.

The 14-pin, double-column pin strap header is keyed at pin 7, which you must remove from the header. Pins must be 0.025 inches square and at least 0.20 inches long. Pin spacing should be 0.1 x 0.1 inches. There must be at least 0.15" clearance on all sides of the pin header to accommodate the EZ-ICE probe plug. Pin leads are available from suppliers such as 3M, McKenzie, and Samtec.

target memory interface

For a target system to be compatible with the EZ-ICE emulator, it must meet the memory interface guidelines listed below.

PM, DM, BM, IOM and CM

Design Program Memory (PM), Data Memory (DM), Byte Memory (BM), I/O Memory (IOM), and Composite Memory (CM) external interfaces to comply with worst-case device timing requirements and DSP datasheets Switching characteristics specified in . EZ-ICE performance may be close to published worst-case specifications for certain memory access timing requirements and switching characteristics.

Note: If your target does not meet the worst-case chip specification for memory access parameters, it may not be possible to simulate your circuit at the desired CLKIN frequency. Depending on the severity of the specification violation, you may have problems manufacturing your system because of the statistical differences in switching characteristics and timing requirements of DSP components within the published limits.

Restriction: All memory strobe signals on the ADSP-2183 (RD, WR, PMS, DMS, BMS, CMS, and IOM) used in the target system must be connected to 10 kΩ pull-up resistors when using EZ-ICE. The pull-up resistor is necessary because there is no internal pull-up to guarantee its state under prolonged tri-state conditions caused by a typical EZ-ICE debug session. When the EZ-ICE is not in use, these resistors can be removed at your choice.

target system interface signals

After installing the EZ-ICE board, the performance of some system signals will change. Design your system to be compatible with the following system interface signal changes introduced by the EZ-ICE board:

(1) The EZ-ICE simulation introduces a propagation delay of 8 ns between the target circuit and the digital signal processor on the reset signal.

(2) The EZ-ICE simulation introduces a propagation delay of 8 ns between the target circuit and the digital signal processor on the BR signal.

(3), EZ-ICE simulation ignores reset and BR when single-stepping.

(4), EZ-ICE simulation ignores reset and BR in simulator space (DSP pause).

(5) EZ-ICE simulation ignores the state of the target BR in some modes. Therefore, the target system can control the DSP's external memory bus only when the EZ-ICE board's DSP asserts a bus grant (BG).

target schema file

EZ-ICE software allows you to load programs in linked (executable) form. The EZ-ICE PC program cannot load the executable section located in the startup page (via the linker). All parts of the executable that are mapped to the boot page are not loaded except boot page 0 (loaded into PM RAM).

When using EZ-ICE, the target architecture file is written to indicate that only PM RAM is available for program storage software load functions. Data can be loaded into PM RAM or data mining memory.

Timing parameters

General Instructions

Use the given precise timing information. Do not try to derive parameters from other additions or subtractions. While addition or subtraction will yield meaningful results for a single device, the values given in this data sheet reflect statistical variation and worst-case scenarios. Therefore, the parameters cannot be meaningfully added to obtain longer times.

Timing Considerations

Switch characteristics specify how the processor changes its signals. Timing circuits outside of the processor that you cannot control must be designed to be compatible with these signal characteristics. Switch characteristics tell you what the processor will do in a given situation. You can also use the toggle feature to ensure that any timing requirements of devices attached to the processor, such as memory, are met. Timing requirements apply to signals controlled by circuits external to the processor, such as data inputs for read operations. Timing requirements ensure that the processor works properly with other devices.

output drive current

Figure 19 shows the typical IV characteristics of the output driver of the ADSP-2183. The curve represents the current ability to drive the output driver as a function of output voltage.

Power consumption

To determine the total power dissipation in a specific application, the following equations should be applied for each output:

c = load capacitance, f = output switching frequency.

Example: When using external data memory and no other outputs are active, the power consumption calculation follows: Assumption: 50% of the address pins toggle each time the external data memory is cycled. External data memory writes perform a 50% data pin toggle every other cycle. The total load on each address and data pin is 10 pF. The application runs at VDD=3.3 V and tCK=30.0 ns. Total power consumption=PINT+(C×VDD2×f)

PINT = Internal power consumption graph of power versus frequency (Figure 20).

The total power dissipation in this example is PINT+50.7 mW.

capacitive load

Figures 22 and 23 show the capacitive load characteristics of the ADSP-2183.

Test Condition Output Disable Time

An output pin is considered disabled when it stops driving and begins to transition from the measured output high or low voltage to a high impedance state. The output disable time (tDIS) is the difference between tMEASURED and tDECAY, as shown in the output enable/disable graph. Time is the interval from when the reference signal reaches a high or low voltage level to when the output voltage changes 0.5 V from the measured output high or low voltage. The decay time tDECAY depends on the capacitive load CL and the current load iL on the output pin. It can be approximated by the following equation:

is calculated. If multiple pins (such as a data bus) are disabled, the measurement is the measurement of the last pin that stopped driving.

Output enable time

An output pin is considered enabled when it transitions from a high-impedance state to start driving. The output enable time (tENA) is the time interval from when the reference signal reaches a high or low voltage level until the output reaches the specified high or low trip point, as shown in the output enable/disable diagram. If multiple pins are enabled (such as a data bus), the measurement is the measurement of the first pin to start driving.

environmental conditions

Ambient Temperature Ratings:

TAMB=TCASE–(PD×θCA)

TCASE = case temperature in °C PD = power dissipation in Wθ = thermal resistance (case to ambient) θ = thermal resistance (connected to ambient) θ = thermal resistance (connected to case)