Introduction Innovasic Semiconductor IA186EB and IA188EB microcontrollers are form, fit and function replacements for the original Intel® 80C186 EB, 80C188EB, 80L186EB and 80L188EB 16-bit highly integrated embedded processors.
The devices were produced using Innovasic's Managed IC Life Extension System (MILES™). This cloning technique produces replacement chips that go beyond simple emulation, ensuring full compatibility with the original device, including any-undocumented features. ―Furthermore, the MILES process captures clone designs in such a way that clone production can continue even as silicon technology advances.
The IA186EB and IA188EB microcontrollers replace the obsolete Intel 80C186EB and 80C188EB devices, allowing users to retain their existing board designs, software compiler/assembler and simulation tools, thus avoiding costly redesign efforts.
Overview
Innovasic Semiconductor IA186EB and IA188EB microcontrollers are upgrades to the 80C186EB/80C188EB microcontroller design with integrated peripherals to provide more functionality and reduce system cost. The IA186EB and IA188EB devices are designed to meet the requirements of embedded products designed for telecommunications, office automation and storage, and industrial control.
The IA186EB and IA188EB microcontrollers feature a basic set of peripherals that benefit many embedded applications, including standard digital interfaces, interrupt control unit, chip select unit, DRAM refresh control unit, power management unit, and three 16-bit timer/counters.
The IA186EB and IA188EB microcontrollers are capable of operating at 5.0 or 3.3 volts. This data sheet discusses two modes of operation. Where applicable, specific characteristics for 3.3V or 5.0V operation are identified separately in this data sheet.
In addition, the IA186EB and IA188EB include two integrated serial ports that support synchronous and asynchronous communication, simplifying inter-processor and display communication. The IA186EB and IA188EB also have an enhanced chip select unit and two multiplex I/O ports. The enhanced chip select unit provides 10 general-purpose chip selects, each capable of addressing up to 1 megabyte. This enhanced unit enables memory bank swapping to expand the IA186EB/IA188EB's 1-megabyte address space. Input/output ports allow basic functions such as scanning keyboard input. These ports can also be used to control system power consumption and disable unneeded components.
Serial ports, I/O capabilities, and enhanced chip selection make the IA186EB/IA188EB an excellent processor for portable data acquisition or communications applications.

feature
The main features of the IA186EB and IA188EB microcontrollers are as follows:
Low-Power Operating Modes – Idle (freeze CPU clock; peripherals remain active) – Power Down (freeze all internal clocks)
Low power CPU cores (static)
Direct Addressability - Memory: 1 MB - I/O: 64 KB
I/O Ports - 2 each, 8-bit Multiplexed Clock Generator Chip Select - 10 each, Programmable - Integrated Wait State Generator Memory Refresh Control Unit Programmable Interrupt Controller Counter/Timer - Every 3, 16-bit - Programmable Serial Channels - 2 each, UART - Integrated Baud Rate Generator Operating Frequency (System Clock Input) - 50 MHz @ 5V - 32 MHz @ 3.3V Functional Description, Provides Details of the IA186EB and IA188EB microcontrollers, including the features listed above.

Packaging, Pinout, and Physical Dimensions Packaging and pinout information for the IA186EB and IA188EB are provided separately.
Packaging and Pinouts
Innovasic Semiconductor IA186EB and IA188EB microcontrollers have the following components:
84-pin Plastic Leaded Chip Carrier (PLCC), equivalent to the original PLCC package 80-pin Plastic Quad Flat Package (PQFP), equivalent to the original PQFP package 80-pin Thin Quad Flat Package (LQFP), equivalent to the original SQFP package

IA186EB 84 PLCC package
The pinout of the IA186EB 84 PLCC package is shown in Figure 1. The corresponding pinouts are provided in Table 1.

IA188EB 84 PLCC package
The pinout of the IA188EB 84 PLCC package is shown in Figure 2. The corresponding pinouts are provided in Table 2.

PLCC physical size
84 Physical dimensions of PLCC

IA186EB 80 PQFP package

IA188EB 80 PQFP package

Signal description
Description of the IA186EB microcontroller PIN and signal functions.
The IA186EB PINS has several different functions depending on how the device is operated. Each of the different signals supported by pine trees is listed and defined in Table 7, listed alphabetically in the first column of the table. In addition, the name of the PIN associated with the signal and the PIN number are provided for PLCC, LQFP, and PQFP packaging. Signals not used in a specific wrapper type are specified as signal descriptions
Several functions of the IA188EB PINS depend on how the unit is operated. Each of the different signals supported by pine trees is enumerated and defined, in alphabetical order in the first column of the table. In addition, the name of the PIN associated with the signal is provided, as well as the PIN number for the PLCC, LQFP, and LQFP packaging of the PIN.

Maximum Ratings, Thermal Characteristics and DC Parameters, Absolute Maximum Ratings, Thermal Characteristics and DC Parameters for Stepless Semiconductor IA186EB and IA188EB Microcontrollers

Architecturally, the IA186EB and IA188EB microcontrollers include the following functional blocks:
Bus Interface Unit Clock Generator Interrupt Control Unit Timer/Counter Unit Serial Communication Unit Chip Select Unit I/O Port Unit Refresh Control Unit Power Management Unit
Functional block diagram of the IA186EB/IA188EB. See the following subsections for descriptions of the function modules.
bus interface unit
The IA186EB/IA188EB bus controller, generates local bus control signals and shares the local bus with other bus masters using the hold/hlda protocol. The bus controller generates 20 address bits, read and write control signals, and bus cycle status information. The ready input is used to extend the bus cycle beyond at least four clock cycles.

clock generator
The IA186EB/IA188EB use an on-chip clock generator to provide internal and external clocks. The clock generator utilizes a crystal oscillator and includes a divide-by-two counter.
The clock circuit can use a parallel resonant fundamental mode crystal network (a) or a third overtone mode crystal network (B), or can be driven by an external clock source (C).
When choosing a crystal, the following parameters are recommended:
Temperature Range - Specific Purpose - ESR (Equivalent Series Resistance): 40 max – C0 (Crystal Shunt Capacitance): 7.0 pF max – CL (Load Capacitance): 20 pF ± 2 pF – Drive Level: 1 mW max

interrupt control unit
The IA186EB/IA188EB can receive interrupts from multiple internal and external sources. The interrupt control unit is used to combine these requests on a priority basis for individual service by the CPU. Each interrupt source can be masked independently by the Interrupt Control Unit (ICU), or all interrupts can be masked globally by the CPU.
Internal interrupt sources include timers and serial channel 0. External interrupt sources come from five input pins int0–int4. The NMI interrupt pins are not controlled by the ICU and are passed directly to the CPU. Although the timer and serial channel each have only one request input to the ICU, separate vector types are generated to service a single interrupt within the timer and serial channel units.
Timer/Counter Unit
The IA186EB/IA188EB Timer/Counter Unit (TCU) provides three 16-bit programmable timers. Two of them are highly flexible and connect to external pins for control or clock. The third timer is not connected to any external pins and can only be clocked internally. However, it can be used to time the other two timer channels. The TCU can be used to count external events, time external events, generate non-repetitive waveforms, generate timed interrupts, and more.
Serial communication unit
The Serial Control Unit (SCU) of the IA186EB/IA188EB contains two independent channels. Each channel operates the same except that the integrated interrupt controller only supports channel 0 (channel 1 has external interrupt pins). Each channel has its own baud rate generator, which is independent of the timer/counter unit and can be clocked internally or externally at up to half the operating frequency of the IA186EB/IA188EB.
Provides independent baud rate generators for each serial channel. For asynchronous mode, the generator provides an 8x baud clock to the receive and transmit register logic. 1x baud clock is provided in synchronous mode.
chip select unit
The IA186EB/IA188EB chip select unit (CSU) integrates logic to provide up to 10 programmable chip selects to access memory and peripherals. In addition, each chip select can be programmed to automatically insert an additional clock (wait state) into the current bus cycle and automatically terminate the bus cycle, regardless of the condition of the ready input pin.

I/O Port Unit
The I/O Port Unit (IPU) on the IA186EB/IA188EB supports input, output or input/output operations of two 8-bit channels. Port 1 is multiplexed with the chip select pin, output only. Most of port 2 is multiplexed with serial channel pins.
Refresh Control Unit The Refresh Control Unit (RCU) automatically generates periodic memory read bus cycles to keep dynamic or pseudo-static memory refreshed. A 9-bit counter controls the number of clocks between refresh requests.
A 12-bit address generator is maintained by the RCU and displayed on the a1-a12 address lines during the refresh bus cycle. The address bits are programmable, allowing the refresh address block to be located on any 8 kilobyte boundary.
power management unit
The IA186EB/IA188EB Power Management Unit (PMU) is used to control the power consumption of the device. The PMU provides three power modes: active, idle and powered down.
Active mode means that all units on the IA186EB/IA188EB are functioning properly and the device consumes maximum power (depending on the operating level of the peripherals). Idle mode freezes the execution and clocks to the bus unit at a zero logic state (all peripherals continue to function normally).
Power-down mode freezes all internal clocks at logic zero and disables the crystal oscillator. All internal registers retain their values as long as VCC is maintained. Current consumption is reduced to transistor junction leakage.
Peripheral Architecture
The IA186EB/IA188EB integrates several common system peripherals and a CPU core to create a compact and powerful system. The integrated peripherals are designed to be flexible and provide logical interconnections between support units (for example, the interrupt control unit supports interrupt requests from timers/counters or serial channels). The list of integrated peripherals includes:
7 Input Interrupt Control Unit 3 Channel Timer/Counter Unit 2 Channel Serial Communication Unit 10 Output Chip Select Unit I/O Port Unit Refresh Control Unit

The power management unit's registers associated with each integrated peripheral are contained in a 12816 register file called the Peripheral Control Block (PCB). The PCB can be located in memory or I/O space on any 256-byte address boundary.

Reset Operation The IA186EB/IA188EB performs a reset operation as long as the resin pin is active. Reset sequence when the IA186EB/IA188EB is powered up. The external clock connected to clkin must not exceed the VCC threshold applied to the processor. This is usually not a problem if the clock driver is the same as the VCC supplying the processor. When connecting the crystal to the device, the resin must remain active until both VCC and clkout are stable (the length of time depends on the specific application and depends on the startup characteristics of the crystal circuit). The resin pins are designed to work correctly with an RC reset circuit, but the designer must ensure that the ramp time of VCC is not too long, and that the resin tube is never sampled at a logic low level when VCC reaches the minimum operating condition.
NOTE: Failure to assert resin when the device is powered on will result in unpredictable operation.
Warm reset timing, showing the timing sequence when resin is applied after Vcc has stabilized and the device has run. Any bus operations in progress when resin is asserted will terminate immediately.
When the resin is active, the bus signals lock, a19/once, and a18–a16 are configured as inputs and are weakly held high by the internal pull-up transistors. Only 19/once/once_n can be overdrawn to low to enable once mode.
Number 7. The bus timing figures 18 through 26 on the next page show the various bus cycles generated by the processor. The figure shows the relationship of various bus signals to clkout. Together with the information in the AC characteristics, these graphs allow the user to determine all the critical timing analysis required for a given application.