feature

User configurable for 9, 10, 11 or 12 bit resolution Accurately calibrated to ±1°C, 0°C to 100 °C Typical temperature range: -40°C to 125°C Low operating current (less than 250µA ) Low self-heating (up to 0.2°C in still air) Operating voltage range: 2.7V to 5.5V

application

Battery ManagementFax ManagementPrintersPortable Medical DevicesHVAC SystemsPower ModulesDisk DrivesComputersAutomotive Components

illustrate

The FM75 contains a high-accuracy CMOS temperature sensor, a Delta-Sigma analog-to-digital converter, and an SMBus-compatible serial digital interface at 40°C to 125°C and ±1°C9 to 0°C to 100°C 12-bit resolution (default 9). Thermal Alarm Output, Out of Limit Signal (OS) Support Interrupt and Comparator Mode The OS activates if a user programmable trip temperature is exceeded. When the temperature is below the trip temperature, plus a user programmable hysteresis limit, the operating system is disabled. Surface mount SOIC-8 (SOP-8) package.

Basic Operation The FM75 temperature sensing circuit operates continuously to generate an analog voltage proportional to the temperature of the device. At regular intervals, the FM75 converts the analog voltage to a 2's complement digital value, which is placed into the temperature register. The FM75 has an SMBus compatible digital serial interface that allows access to temperature data registers at any time. In addition, the serial interface provides access to all other FM75 registers to customize the operation of the device. The FM75 temperature-to-digital conversion can have 9, select 10, 11 or 12 bit resolution, provide 0.5°C, 0.25°C, 0.125°C and 0.0625°C temperature resolution, respectively, when powered, the default conversion resolution is 9 bit. The conversion resolution is determined by the R0 and R1 bits in the configuration register. Table 1 gives the output digital data and external temperature. The 9-bit, 10-bit, 11-bit and 12-bit columns in Table 1 represent the rightmost bit in the output data stream, which can contain temperature information for each conversion accuracy because The output digital data is in binary format, and the most significant temperature bit is the "sign" bit. If the sign bit is zero, the temperature is positive; if the sign bit is 1, the temperature is negative. The FM75 has a shutdown mode that reduces the operating current to 150nA. This mode is controlled by the SD bit in the configuration register. Power-Up Default Conditions The FM75 powers up in the following default states:

Thermostat Mode: Comparator Mode

OS Polarity: Active Low

Fault Tolerance: 1 Fault (i.e. Configuration Register) TOS: 80°C Temperature: 75°C Register Pointer: 00 (Temp Register) Conversion Resolution: 9 bits (i.e. R0=0 and R1=0 in Configuration Register) Power On Later, these conditions can be reprogrammed through the serial interface. See the Operation section of the serial data bus FM75 programming instructions.

Thermal Alarm Function The FM75 thermal alarm function provides a programmable thermostat function and allows the FM75 to work as a stand-alone thermostat without using the serial interface overrun signal (OS) output as an alarm output. This signal is an open-drain output, and at power-up, this pin is configured to be active with low polarity. Table 1 Temperature relationship and digital output

OS polarity is controlled by the POL bits in the configuration register. The programmable upper trip point temperature for thermal alarms is stored in the TOS register. The programmable hysteresis temperature (ie., the lower trip point) is stored in the THYST register. Thermal Alarm has two modes of operation: Comparator Mode and Interrupt Mode. On power-up, the default is the comparator mode alarm mode determined by the CMP/INTR bits in the configuration register. Fault Tolerance For Comparator and Interrupt modes, the alarm "Fault Tolerance" is set to determine when the OS output is activated. Fault tolerance refers to the number of consecutive times an error condition must be detected before the user is notified. Higher fault tolerance settings help eliminate alarms caused by noise in the system. Fault tolerance is controlled by the F0 and F1 bits in the configuration register. These bits can be used to set fault tolerance to 1, 2, 4, or 6, as shown in Table 4. At power-up, these two bits default to 0 (tolerance = 1).

Comparator Mode In Comparator mode, each time a temperature-to-digital (T-to-D) temperature conversion occurs, the new digital compares the temperature to the value stored in the TOS and THYST registers. If the tolerance number for successive temperature measurements is greater than The value stored in the TOS register, the operating system output is activated. For example, if bits F1 and F0 are equal to "10" (fault tolerance = 4), four consecutive temperature measurements must exceed TOS to activate the OS output. Once the OS output is active, it will remain active until the first measured temperature drops to an alarm in the temperature surgery comparator mode stored in the THYST register, fault tolerance = 2 as shown. Interrupt Mode In interrupt mode, the operating system output first becomes active after the tolerant number of continuous temperature measurements exceeds the value stored in the TOS register (similar to comparator mode). Once the operating system is activated, it can only be done by the user from the FM75 registers (temperature, configuration, TOS or THYST) or by putting the FM75 into shutdown mode (ie., by setting the shutdown bit in the configuration register to '1'). Once cleared, the OS output can only be activated the next time the number of consecutive temperature measurements falls below the value stored here. Once activated, the OS output can only be deactivated by user reading or closing. In interrupt mode, the activation/clearing cycle of the operating system is as follows mode: temperature > TOS, transparent, temperature Operational diagrams for TOS, clearing, etc. show alerts in interrupt mode with a fault tolerance of 2.

Register FM75 contains the following five registers:

command register

temperature register

configuration register

Overrun signal temperature register (TOS)? ? Hysteretic Temperature Registers (THYST) Users can readily provide a digital serial interface (see Serial Interface Operating Instructions) detailed descriptions of these registers and their functions are provided in the following sections. The register hierarchy diagram is shown in the following figure.

Command Register The Command Register is a single-byte (8-bit) write-only register. The data stored in the Command Register indicates the upcoming action in the Command Register "points to" the selected register, as shown. The command register is shown in the figure. The P0 bit of the P1 command register determines the access register, as shown in Table 2. The valid bits (MSBs) of up to six command registers must always be zero. A write to any of these bits causes the current operation to terminate. The command register retains pointer information between operations; therefore, this register only needs to be updated once for the same register for successive read operations. All bits in the command register default to zero at power-on.

Temperature Register The temperature register is a double-byte (16-bit) read-only register. The digital temperature from the T-to-D converter is stored in the temperature register in 2's complement format, and the contents of this register are updated at regular intervals, every The T-to-D conversion is complete. Users can at any time. Load new data into comparator buffer for calculation when T to D conversion is complete If a fault occurs, the update temperature register read cycle is not in progress. The FM75 is continuous regardless of the read and write conditions, and evaluates fault conditions on the bus's activity. If reading is in progress, read temperature. The read temperature is updated at the completion of the next T-to-D conversion not masked by the read cycle. The temperature register is shown in Figure 7. Depending on the resolution of the T to D conversion, 9, 10, 11 or 12 MSBs of the register contain temperature data. All unused bits after the digital temperature are zero The MSB position register of the temperature always contains the sign bit of the digital temperature, and bit 14 contains the temperature MSB bit in the temperature register, which defaults to zero at power-up.

SB=2's complement sign bit

TMSB = Temperature MSB

T = temperature data

9-bit LSB = 9-bit converted temperature LSB

10-bit LSB = 10-bit converted temperature LSB

11-bit LSB = 11-bit converted temperature LSB

12-bit LSB = 12-bit converted temperature LSB

Configuration Register The Configuration Register is a single-byte (8-bit) read/write register (see figure). This register allows the user to control the FM75 shutdown mode and the following thermal alarm functions: polarity, operating mode and fault tolerance. The configuration register contains two bits that set the fault tolerance trip point. The fault tolerance trip point is when the internal circuitry reads the temperature and finds that the temperature is outside the programmed limit. The programming limit consists of an upper limit and a lower limit specified by the THYST register. Table 4 shows F1 and F0 with the desired number of consecutive errors or "trips" to initiate an alarm The configuration register also contains two bits that set the T to D conversion resolution to 9, 10, 11 or 12 bits Table 3 shows R1 and T0 vs. Conversion Resolution All bits in the configuration register default to zero at power-up.

R1 = Resolution bit 1 (see Table 3).

R0 = Resolution bit 0 (see Table 3).

F1=Tolerance bit 1 (see Table 4).

F0=Tolerance bit 0 (see Table 4).

POL=OS output polarity: 0=active low, 1=active high.

CMP/INT=thermostat mode: 0=comparator mode, 1=interrupt mode.

SD=shutdown: 0=normal operation, 1=shutdown mode.

Out of Limit Signal Temperature Register (TOS) The TOS register is a two-byte (16-bit) read/write register that stores the user-programmable upper trip point temperature for thermal alarms in two's complement format. At power-up, this register defaults to 80°C (i.e. 01010000). The format of the TOS register is the same as that of the temperature register (see figure). The four LSBTOS registers are hard-wired to zero, so data writes ignore the MSB position of these register bits. The TOS register contains the sign bit for the digital temperature, and bit 14 contains the temperature MSB. The resolution setting for the T to D conversion determines the thermal alarm. For example, for a 9-bit conversion the trigger point temperature is ignored by the TOS register and all remaining bits. Hysteresis Temperature Register (THYST) The THYST register is a two-byte (16-bit) read/write register that stores the programmable lower trigger point temperature for thermal alarms in two's complement format. At power-up, this register defaults to 75°C (i.e. 0100101100000000). The THYST register is shown in the figure. The format of this register is the same as that of the temperature register. The four lsbs of the register THYST register are hardwired to zero, so data written to these bits is ignored. The resolution setting for T-to-D conversion determines the number of bits used for the THYST register thermal alarm. For example, for a 9-bit conversion, the hysteresis temperature is defined by the nine MSBs ignoring all remaining bits of the THYST register.

Serial data bus operation General operation Complete the writing and reading of the FM75 register through a two-wire serial interface compatible with SMBus. The SMBus protocol requires the bus to start and control all read and write operations. This device is called the "master" device. The master device also generates the SCL signal, which is the signal to all other devices on the clock bus. All other devices on the bus are called "slave" devices. FM75 is the slave device. Both master and slave devices can send and receive data on the bus. During SMBus operation, every clock cycle all SMBus operations follow a repeating 9-octet (one byte) clock cycle pattern with an acknowledgment (ACK) or no acknowledgment (NACK) from the receiving device after sending data. Note that there is no data flow and ACKs/nacks during any data transfer. Conversely, too few clock cycles can result in incorrect operation if 8 bits are accidentally read from a 16-bit register. For most operations, the SMBus protocol requires a stable (immovable) line when SDASCL is high - that is, only when SCL is low. The exception to this rule is when a device signals a start or stop. The slave device cannot issue a start or stop signal. Start Condition: Line transitions from high to low when SDASCL is high. The master device uses this condition to indicate that a data transfer is about to begin. Stop Condition: Line transitions from low to high when SDASCL is high. The master device uses this condition to signal the end of the data transfer. Acknowledged vs Unacknowledged: When data is transferred to the slave, it sends an acknowledgement (ACK) after each byte of data is received The master sends an acknowledgement (ACK) only after the first byte read from the double-byte register The receiving device sends an ACK by pulling SDA low for one clock cycle. After the last byte, the master sends a "not acknowledgment" (NACK) followed by a stop condition. A NACK is indicated after the last byte by holding SDA high for the duration of the clock.

The four msbs of the FM75 address are hardwired to 1001. The three lsb are user connected to VDD or ground by bonding the A0, A1 and A2 pins. This provides 8 different FM75 addresses, allowing up to eight FM75s to be connected to the same bus. All read and write operations from the FM75 must start with a start signal generated by the master device. Immediately after startup, the master must send the slave address (7 bits) followed by a read/write bit. If the slave address matches the FM75, the address of the FM75 provides a timing diagram for all FM75 operations by pulling the SDA line low for one clock cycle after receiving the read/write bit. Setting the pointer For all operations, the pointer register stored in the command must point to or read from a register (temperature, configuration (TOS or THYST) to be written to. To change the pointer value in the command register, the read/write bit after the address must is 0. This indicates that the master will write new information into the command register. After the FM75 sends an ACK to acknowledge the received address and read/write bits, the master must send the appropriate 8-bit pointer value in the register section as previously described The FM75 is receiving new pointer data. The pointer set operation is as shown. Whenever a pointer set is performed, it must be performed immediately followed by a read or write operation. Note that the MSBs of the six pointer values must be zero. If the six MSBs are not zero, The FM75 does not send an ACK and terminates the operation internally. The command register retains the current pointer value between operations; therefore, once the register is instructed, subsequent reads do not require a pointer set cycle and writes always require a pointer reset.

Read if the pointer already points to the desired register, by setting the read/write bit (after the slave address) to 1. When sending an ACK afterwards, the FM75 starts sending data on the next clock cycle. If the configuration register is being read, the FM75 transfers one byte of data (see diagram). The master should respond with a NACK, followed by a STOP condition. If the temperature, TOS, or system registers are being read, the FM75 sends two bytes of data (see Figure 12). The master must respond with the first byte of data with an ACK, and the second byte followed by a NACK data byte with a stop condition. The required register must be set to read from a register other than the one currently indicated by the command register. Immediately after the pointer is set, the host must execute the Repeated Start condition, which indicates that a new operation is about to take place on the FM75.

If the Repeated Start condition does not occur, the FM75 assumes that a write is in progress, and the selected register is overwritten by the incoming data on the data bus. After the Start condition, the host must send the device address and the read/write bit again. This time, the read/write bit Must be set to 1 to indicate read. The rest of the read cycle is the same as previously described for the segment read from the preset pointer position. Writes All writes must be made by the pointer set, even if the pointer already points to the desired register. Immediately after the set of pointers, the master must start transmitting the data to be written If the master is writing to the configuration register, one byte of data must be sent (see diagram) If the TOS or THYST register is being written, the master must send two words Section data (see figure) After each byte of transmitted data, the host must release the serial data (SDA) line for one clock cycle to allow the FM75 to acknowledge the received byte. Write operations should be terminated by a stop signal from the host. NOTE: An 8-bit D7 bit that is accidentally read from a 16-bit register accidentally low can cause the FM75 to stall where the SDA line is pulled low by the output data and cannot receive a Stop or Start condition from there. The only way to do this is from The state will continue to clock for nine cycles until SDA goes high, at which point a STOP condition is issued to reset the FM75 as shown.