feature

256 bits; replace 1, 2 or 4 potentiometers; 1 kV, 10 kV, 50 kV, 100 kV; power outages less than 5 mums; 3-wire SPI compatible serial data input; 10 MHz update data loading speed; +2.7 V to +5.5 V single-supply operation mid-scale preset.

application

Mechanical potentiometer replacement; programmable filter, delay, time constant; volume control, panning; line impedance matching; power supply adjustment.

General Instructions

The AD8400 /AD8402/AD8403 offer a single, dual, or quad, 256-bit digitally controlled variable resistor (VR) device. These devices perform the same electronic adjustment functions as a potentiometer or variable resistor. The AD8400 operates in a compact SO- A variable resistor is included in the 8 package. The AD8402 contains two independent variable resistors in a space-saving SO-14 surface mount package. The AD8403 contains four independent variable resistors in 24-lead PDIP, SOIC, and TSSOP packages. Each section contains a fixed resistor and a wiper contact that taps the fixed resistance value at a point determined by a digital code loaded into the control serial input register across the wiper and fixed resistor The resistance in between varies linearly with the digital code transferred into the VR latch. Each variable resistor provides a fully programmable resistance value between the a terminal and the wiper or between the B terminal and the wiper. 1 kΩ, 10 kΩ, 50 The fixed A-to-B terminal resistors of kΩ or 100 kΩ have a ±1% channel-to-channel matching tolerance with a nominal temperature coefficient of 500 ppm/°C. The unique switching circuit minimizes the high faults inherent in traditional switching resistor designs, avoiding making before making or breaking before making.

Each VR has its own VR latch that holds its programmed resistance values. These VR latches are updated from an SPI-compatible serial-to-parallel shift register loaded from a standard 3-wire serial-in digital interface. . The 10 data bits make up the data word that goes into the serial input register. The data word is decoded, where the first two bits determine the address of the VR latch to be loaded, and the last eight bits are the serial data output reference at the other end of the data serial register. The pins allow simple daisy-chaining in multiple VR applications without the need for additional external decoding logic. The reset (RS) pin forces the wipers to the mid-scale position by loading 80 hours into the VR latch. The SHDN pin forces the resistor to an end-to-end open state at the A terminal and shorts the wiper to the B terminal for a microwatt power-off state. When SHDN returns to logic high, the previous latch setting places the wiper before shutdown. The same resistance setting of the digital interface is still active at shutdown, so code changes can be made that result in new wiper positions when the device is taken out of shutdown.

The AD8400 is available in SO-8 surface mount and 8-lead plastic dip packages.

The AD8402 is available in surface mount (SO-14) and 14-lead plastic dip packages, while the AD8403 is available in narrow body 24-lead plastic dip and 24-lead surface mount packages. The AD8402/AD8403 are also available in the PCMCIA ap's 1.1 mm low profile TSSOP-14/TSSOP-24 package - application All parts are guaranteed to operate over the extended industrial temperature range of -40°C to +85°C.

operate

The AD8400/AD8402/AD8403 offer a single, dual and quad, 256-bit digitally controlled variable resistor (VR) device that is changed by entering a 10-bit serial data word into the SDI (serial data input) pin Programmed virtual reality setup. The format of this data word is two address bits, MSB first, followed by eight data bits, MSB first. Table 1 provides the serial register data word format. The AD8400/AD8402/AD8403 have the following address assignment for ADDR decoding, which is used to determine the location of the virtual reality latch that receives the serial register data (bits B7 to B0): VR# = A1 × 2 + A0 + 1 Equation 1

The single-channel AD8400 requires A1=A0=0, and the dual-channel AD8402 requires A1=0. Virtual reality settings can be changed one at a time in random order. The serial clock runs at 10 MHz and can load the AD8403 in under 4 microseconds (10 × 4 × 100 nanoseconds) for all 4 VRs. The precise timing requirements are shown in Figures 1a, 1b, and 1c.

The AD8402/AD8403 simplifies initial conditions at power-up by asserting the RS pin to reset to midscale with both parts

Shutdown SHDN pin puts VR into zero power state where terminal Ax is open circuited and wiper Wx is connected to Bx, resulting in only leakage current being consumed in VR structure In shutdown mode, VR latch setting is maintained for shutdown from power Returning to operating mode, the VR settings return to their previous resistance values. The digital interface is still active at shutdown, but a code change in the SDO disabled register can result in a new wiper position when the device comes out of shutdown.

Variable Resistor Rheostat Operation Programming

The nominal resistance values of VR (RDAC) between terminals A and B are 1 kΩ, 10 kΩ, 50 kΩ and 100 kΩ respectively The last digit of the part number determines the nominal resistance value, eg 10 kΩ=10; 100 kΩ= 100. The nominal resistance (RAB) of the VR has 256 contacts connected through the wiper terminal and the B terminal contact. The 8-bit data word in the RDAC latch is decoded to select one of 256 possible settings. The first connection of the wiper starts from the B terminal of the data 00H. The wiper contact resistance of this B terminal connection is 50Ω The second connection (10 kΩ part) is the first tap point of data 01H located at 89Ω[=RBA(nominal resistance)/256+RW=39Ω+50Ω]. The third connection is the next tap point for data 02H representing 78+50=128Ω. For each additional LSB data value, the wiper moves up the resistor ladder until the last tap point reaches 8486 at 10011;. The wiper cannot be directly connected to the B terminal. A simplified diagram of the equivalent RDAC circuit is shown in Figure 37.

The AD8400 contains one RDAC, the AD8402 contains two independent RDACs, and the AD8403 contains four independent RDACs The general transfer equation to determine the digitally programmed output resistance between Wx and Bx is: RWB(Dx) = (Dx)/256×RBA + RW Equation 2, where Dx is the data contained in the 8-bit RDAC latch and RBA is the nominal end-to-end resistance.

For example, when VB=0 V and the terminals are open, the following output resistance values (for a 10 kΩ potentiometer) would be set for the following RDAC latch code:

NOTE: At zero scale condition there is a finite wiper resistance of 50Ω It should be noted that in this state the current between W and B is limited to a maximum of 5mA to avoid degradation or possible damage to the internal switch contacts .

Just like the mechanical potentiometer the RDAC replaces, it is perfectly symmetrical. The resistor between wiper W and terminal A also produces a digitally controlled resistor RWA. When using these terminals, the B terminal should be tied on the wiper to set the resistance value of RWA starting at the maximum value of the resistance and decreasing as the value of the data loaded in the RDAC latch increases. The general transfer equation for this operation is: RWA (Dx) = (256–Dx)/256×RBA + RW Equation 3, where Dx is the data contained in the 8-bit RDAC latch and RBA is the nominal end-to-end resistance . For example, when VA = 0 V and the B terminal is open, the following output resistance values (for a 10 kΩ potentiometer) will be set for the following RDAC latch code:

The typical distribution of RBA is within ±1%. However, device-to-device matching is process batch dependent with ±20% variation. RBA has a positive 500 ppm/°C temperature coefficient as a function of temperature.

The wiper-to-tip resistance temperature coefficient has the best performance over the 10% to 100% adjustment range, where the internal wiper contact switch does not produce any noticeable temperature-dependent errors The graph in Figure 11 shows RWB tempco vs. code performance, using a spinner with a code below 32 results in a larger temperature coefficient being drawn.

Program Potentiometer Divider Voltage Output Operation

Digital potentiometers tend to generate an output voltage proportional to the input voltage applied to a given terminal. For example, with one terminal connected to +5 V and the B terminal connected to ground, the wiper produces an output voltage of less than 1 LSB of +5 V at the start of zero volts. The voltage at each LSB is equal to the voltage applied on terminal AB divided by the 256 position resolution of the potentiometer divider. For any given input voltage applied on terminal AB, the general equation defining the output voltage with respect to ground is: VW (Dx) = Dx/256×VAB + VB Equation 4.

The operation of the digital potentiometer in voltage divider mode allows for more precise operation when the temperature is too high. Here, the output voltage depends on the ratio of the internal resistance, not the absolute value; therefore, the temperature drift increases to 15ppm/°C.

At lower wiper position settings, the potentiometer divider temperature coefficient increases as the CMOS switch wiper resistance contributes a sizable portion of the total resistance from terminal B to the wiper. Plot of potentiometer tempco performance versus code setting.

digital interface

The AD8400/AD8402/AD8403 contain a standard SPI com-three-wire serial input control interface. The three inputs are clock (CLK), CS, and serial data input (SDI). Positive feedback GE-sensitive CLK inputs require clean transitions to avoid converting Incorrect data into the serial input register For best results, use faster logic transitions than 1 V/µs. Standard logic families work well. If mechanical switches are used for product evaluation, they should be de-noised using flip-flops or other suitable methods. The block diagram of Figure 38 shows more details on the internal digital circuitry. When CS is active low, the clock loads data into the 10-bit serial register on each positive clock edge.

Note: P=positive side, X=don’t care, SR=shift register.

The Serial Data Out (SDO) pin contains an open-drain N-channel FET. This output requires a pull-up resistor in order to transfer data to the SDI pin of the next package. The pull-up resistor termination voltage may be greater than the VDD supply of the AD8403 SDO output device (but less than the maximum VDD of +8 V), for example, the AD8403 can operate at VDD=3.3 V and the pull-up of the next device interface can be set to + 5V. This allows multiple RDACs to be daisy-chained from a single-processor serial data line. When a pull-up resistor is used to connect to the SDI pin of the following devices in series, a capacitive load on SDO on the daisy-chain node of the clock cycle needs to be increased – SDI between devices must be considered for successful data transfer. When daisy-chaining is used, CS Should be held low until all bits of each packet are clocked into their respective serial registers to ensure that the address and data bits are in the correct decoding positions. If two AD8403 quad RDACs are daisy-chained, 20 bits of address and data are required in the word format provided in Table I.

Note that only the AD8403 has an SDO pin. SHDN forces the SDO output pin to off (logic high state) during shutdown to disable power dissipation in the pull-up resistor. An equivalent SDO output circuit schematic is shown in Figure 40. The data set and data hold times in the specification table determine the data valid time requirement. The last 10 bits When CS re- goes high, CS goes high and it goes to the address decoder, enabling two (AD8402) or four (AD8403) One of the positive edge-triggered RDAC latches is detailed in Figure 39 and the address decoding table in Table 3.

The target RDAC latch is loaded with the last 8 bits of the serial data word, completing a DAC update. In the case of the AD8403, four separate 10-bit data words must be clocked to change all four VR settings.

All digital pins are protected with series input resistors and parallel Zener ESD structures, as shown in Figure 41a, for digital pins CS, SDI, SDO, RS, SHDN, CLK Digital input ESD protection allows mixed power applications where +5 V CMOS logic can be used to drive the AD8400/AD8402 or AD8403 operating from a +3 V supply. The analog pins A, B, and W are protected by 20Ω series resistors and a parallel Zener, see Figure 41b.

The –3 dB bandwidth of the AD8403AN10 (10 kΩ resistor), measured as 600 kHz at half scale, is used as a potentiometer divider. Figure 23 provides a large-signal BODE plot for the three available resistor versions, 10 kΩ, 50 kΩ, and 100 kΩ, characteristic gain flatness versus frequency, and Figure 26. A parasitic simulation model has been developed to predict filter application performance, as shown in Figure 42. Show. Listing I provides a list of macromodel nets for the 10 kΩ RDAC:

In an inverting op amp circuit using a biased ground and rail-to-rail OP279 amplifier, total harmonic distortion plus noise (THD+N) was measured to be 0.003%, as shown in Figure 33. Thermal noise is primarily Johnson noise, for f = 10kΩ version at 1k Hz, typically 9nv/√Hz. For a 100 kΩ device, the thermal noise becomes 29 nV/√Hz. At f=100 kHz, the inter-channel crosstalk is measured to be less than -65 dB. To achieve this isolation, the additional ground pins provided on the package to isolate the individual RDACs must be connected to circuit ground. The AGND and DGND pins should be at the same voltage potential. Any unused potentiometers in the package should be grounded at 10 kHz and the power supply rejection is typically -35 dB (in high precision applications care needs to be taken to minimize power supply ripple).

application

Digital potentiometers (RDACs) allow many trimmer potentiometer applications to be replaced by a solid-state solution that is small and immune to vibration, shock, and open contact problems encountered in harsh environments. A major advantage of a digital potentiometer is its programmability. Any settings can be saved in system memory for later recall.

The two main configurations of the RDAC include the potentiometer divider (basic 3-terminal application) and rheostat (2-terminal configuration) connections shown in Figure 29 and Figure 30.

Certain boundary conditions must be met for proper AD8400/AD8402/AD8403 operation. First, all analog signals must remain within the 0 to VDD range used to operate the single-supply AD8400/AD8402/AD8403 products. For standard potentiometer divider applications, the wiper output can be used directly. For low resistive loads, buffer the wiper with a suitable rail-to-rail op amp such as the OP291 or OP279. Second, for AC signals and bipolar DC regulation applications, a virtual ground is often required. Whatever method is used to create the virtual ground, the result must be to provide the necessary sink and source currents for all connected loads, including adequate bypass capacitors. Figure 33 shows one channel of the AD8402 connected in an invertible programmable gain amplifier circuit. The virtual ground is set to +2.5 V, allowing the circuit output to span a range of ±2.5 V relative to the virtual ground. For maximum output swing, rail-to-rail amplifier capability is necessary. When the wiper is adjusted from its scale reset position (80H) to terminal A (code FFH), the voltage gain of the circuit is successfully increased in larger increments. Or, when the wiper is adjusted to the B terminal (code 00H), the signal becomes weak. The curves in Figure 43 show wiper settings over a voltage gain (V/V) range of 100:1. Note the ±10dB of false log gain around 0dB (1V/V). This circuit is mainly used for gain adjustment in the range of 0.14v/V to 4v/V; beyond this range, the step size becomes very large, and the resistance of the drive circuit can become an important term in the gain equation.

Active filter

One of the standard circuits used to create low pass, high pass or band pass filters is a state variable active filter digital potentiometer allows full programmability of the frequency, gain and Q of the filter output Figure 44 shows the use of +2.5V Filter circuit with virtual ground, allowing ±2.5VP input and output swing. RDAC2 and 3 set the LP, HP and BP cutoff and center frequencies, respectively. These variable resistors should be programmed with the same data (as the combined potentiometers) to maintain optimal circuit Q. Figure 45 shows the measured filter response at the bandpass output as a function of the RDAC2 and RDAC3 settings, which produce a center frequency range of 2 kHz to 20 kHz. The filter gain response at the bandpass output is shown in Figure 46 Shown at a center frequency of 2kHz, the gain is adjusted from -20dB to +20dB as determined by RDAC1. Circuit Q is regulated by RDAC4. For more detailed readings of state variable active filters, see Application Note for Analog Devices, AN-318.