feature

Fast (2.2 seconds) 14-bit ADC; 400 kSPS throughput; 0.3s track/hold acquisition time; single-supply operation; input range selection: 10 V, 5 V, and 2.5 V; 0 V to 2.5 V and 0 V to 5 V ; High-speed parallel interface, also allows interfacing with 3V processors; Low power, 80mW (typ); Power save mode, 20W typical; Analog input overvoltage protection; Power down mode via STBY pin.

General Instructions

The AD7899 is a fast, low power, 14-bit A/D converter that operates on a single 5-volt supply. This part contains a 2.2-bit successive approximation ADC, a track/hold amplifier, 2.5 V reference, and an on-chip clock oscillator. , signal conditioning circuits and high-speed parallel interfaces. The part accepts analog input ranges of ±10 V, ±5 V, ±2.5 V, 0 V to 2.5 V, and 0 V to 5 V. Overvoltage protection on the part's analog inputs allows the input voltage to be exceeded without damaging the part. Conversion speed can be controlled by an internally trimmed clock oscillator or an external clock.

The conversion start signal (CONVST) puts the track/hold into hold mode and starts conversion. The BUSY/EOC signal indicates the end of the conversion. Using standard CS and RD signals, the AD7899 has a maximum throughput of 400 kSPS to read data from the part over a 14-bit parallel data bus. The AD7899 is available in 28-lead SOIC and SSOP packages.

Product Highlights

1. The AD7899 has a fast (2.2 microsecond) ADC that allows throughput up to 400 kSPS.

2. The AD7899 is powered by a 5V power supply and consumes only 80mW, making it ideal for low power and portable applications.

3. This part provides a high-speed parallel interface interface that can work in 3v and 5v modes, allowing easy connection to 3v or 5v microprocessors, microcontrollers and digital signal processors.

4. There are three versions of this part with different analog input ranges AD7899-1 provides standard industrial ranges of ±10 V and ±5 V; AD7899-2 provides unipolar ranges of 0 V to 2.5 or 0 V to 5 V, AD7899 -3 has an input range of ±2.5 V.

term signal-to-noise ratio

This is the signal-to-noise ratio (noise + distortion) measured at the output of the A/D converter. The signal is the rms of the fundamental. The amplitude noise is the rms sum of all non-fundamental signals up to the sampling frequency (fS/2 ), except for DC. This ratio depends on the number of quantization levels in the digitization process; more levels result in less quantization noise. The theoretical signal-to-noise ratio of an ideal N-bit converter with a sine wave input is:

So for a 14 bit converter this is 86.04db.

total harmonic distortion

Total Harmonic Distortion (THD) is the ratio of the root mean square sum of harmonics to the fundamental. For the AD7899, the definitions are as follows:

where V1 is the rms amplitude of the fundamental and V2, V3, V4 and V5 are the rms amplitudes of the second to fifth harmonics.

Peak harmonics or spurious noise

Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component (up to fS/2, excluding dc) in the ADC output spectrum to the rms value of the fundamental. Typically, the value of this specification is determined by the largest harmonic in the spectrum, but for the part of the harmonic buried in the noise floor, it will be the noise peak.

Intermodulation Distortion

When the input consists of two sine waves of frequencies fa and fb, any active device with nonlinearity will produce distortion products at the sum and difference frequencies of mfa±nfb, where m, n = 0, 1, 2, 3 Wait. Intermodulation terms are terms for which neither m nor n is equal to zero. For example, second-order terms include (fa+fb) and (fa-fb), and third-order terms include (2fa+fb), (2fa-fb), (fa+2fb ) and (fa-2fb).

The AD7899 is tested with two input frequencies. In this case, the meanings of the second- and third-order terms are different. The second-order term is usually farther away in frequency from the original sine wave, while the third-order term is usually at a frequency close to the input frequency. Therefore, the second- and third-order terms are specified separately. Intermodulation distortion calculations are performed according to the THD specification. , where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental in dBs.

Differential nonlinearity

This is the difference between the measured value and the ideal 1 LSB change between any two adjacent codes in the ADC.

Positive Gain Error (AD7899-1, AD7899-3)

This is the deviation of the last code transition (01..110 to 01..111) from ideal 4 × VREF – 3/2 LSB (AD7899 at ±10 V), 2 × VREF – 3/2 LSB (AD7899 within ±5 V) or VREF – 3/2 LSB after adjusting for bipolar offset error (with AD7899 within ±2.5 V).

Positive Gain Error (AD7899-2)

This is the deviation of the last code transition (11. . . 110 to 11. . . 111) from the ideal 2 × VREF – 3/2 LSB (AD7899 at adjusted for unipolar offset error, ±10 V), 2 × VREF–3/2 LSB (AD7899 from 0 V to 5 V) or VREF–3/2 LSB (AD7899 from 0 V to 2.5 V).

Unipolar Offset Error (AD7899-2)

This is the deviation of the first code transition (00). .. 00 to 00 points. . 01) from ideal AGND + 1/2 LSB.

Bipolar Zero Error (AD7899-1, AD7899-2)

This is the deviation of the mesoscale transformation (all 0s to all 1s) from ideal AGND – 1/2 LSB.

Negative Gain Error (AD7899-1, AD7899-3)

This is the deviation of the first code transition (10..000 to 10..001) ideal – 4 × VREF + 1/2 LSB (AD7899 at –10 V after adjusting for bipolar zero error), –2 ×VREF+1/2 LSB (with AD7899 within ±5 V) or –VREF+1/2 LSB (with AD7899 within ±2.5 V).

Track/Hold Acquisition Time

Track/hold capture time is the time it takes for the output of the track/hold amplifier to reach its final value (within ±1/2 LSB) after the conversion ends (the point at which the track/hold returns to track mode). It also applies when there is a step input change in the input voltage applied on the selected VINA/VINB input of the AD7899. This means that the user must wait for the track/hold acquisition time after the conversion ends or after the step input changes to VINA/VINB. duration before another conversion can begin to ensure the part is operating to specification.

Converter Details

The AD7899 is a high-speed, low-power, 14-bit A/D converter powered by a 5-volt supply. This section contains a 2.2µs successive approximation ADC, track/hold amplifier, internal 2.5 V reference, and a high-speed parallel interface. The part accepts analog input ranges of ±10 V or ±5 V (AD7899-1), 0 V to 2.5 V or 0 V to 5 V (AD7899-2), and ±2.5 V (AD7899-3). Overvoltage protection on part analog input allows input voltages up to ±18 V (±10 V for AD7899-1), -9 V to +18 V (±5 V for AD7899-1), -1 V to +18 V (AD7899-2) and -4 V to +18 V (AD7899-3) without damage.

By pulsing the CONVST input, a conversion is initiated on the AD7899. On the rising edge of CONVST, the on-chip track/hold is placed in the hold position and a conversion begins. The BUSY/EOC output signal is toggled high on the rising edge of CONVST and remains high during the conversion sequence. The conversion clock for this part is generated internally using a laser trimmed clock oscillator circuit. An external non-continuous clock can also be optionally applied to the CLKIN pin. If this input is high on the rising edge of CONVST, the external clock should start 100 ns after the rising edge of CONVST. The clock see gets the best throughput. The BUSY/EOC signal indicates the end of the conversion, at which time Track and Hold returns to the tracking mode. The conversion result can be read through the 14-bit parallel data bus at the end of the conversion (indicated by BUSY/EOC going low), standard CS and RD signals see Timing and Control.

The AD7899 has a conversion time of 2.2 microseconds and a track/hold capture time of 0.3 microseconds. To get the best performance from the part, read operations should not be performed during conversions or during the 150 ns period before the next CONVST rising edge. This allows the part to operate at throughputs up to 400 kHz and meet datasheet specifications.

Circuit Description Track/Hold Section

The track/hold amplifier on the AD7899 allows the ADC to accurately convert an input sine wave of full-scale amplitude to 14-bit precision even when the ADC is at its maximum throughput rate of 400 kSPS (i.e., the track/hold can handle input frequencies in excess of 200 kHz) ), the track/hold input bandwidth is greater than the Nyquist rate of the ADC.

The track/hold amplifier acquires the input signal to 14-bit accuracy in less than 300ns. The operation of the track/hold is basically transparent to the user The track/hold amplifier samples the input channel on the rising edge of CONVST The aperture time of the track/hold (i.e. the delay time between the external CONVST signal and the track/hold that actually enters the hold ) is typically 15ns, and more importantly, well matched between devices it allows multiple AD7899s to sample multiple channels simultaneously. At the end of the conversion, the part returns to its tracking mode. The acquisition time of the track/hold amplifier starts at this point.

Reference chapter

The AD7899 includes a reference pin, labeled VREF, that provides access to the part's own 2.5V reference, or allows the connection of an external 2.5V reference to provide the part's reference voltage source. This part is specified for a 2.5 V reference voltage.

To use the internal reference as the reference source for the AD7899, simply connect a 0.1µF capacitor from the VREF pin to AGND. The voltage appearing on this pin is buffered internally before being applied to the ADC. If the reference needs to be used external to the AD7899, it should be buffered because the part has a FET switch in series with the reference output, resulting in a source impedance of 6 for this output The internal reference tolerance is ±10 mV at 25°C nominal for kΩ, the typical temperature coefficient is 25 ppm/°C, and the maximum error is ±20 mV.

If the application requires a reference with tighter tolerances or the AD7899 needs to be used with a system reference, the user can choose to connect an external reference to this VREF pin. The external reference will effectively drive the internal reference, providing a reference source for the ADC. The reference input is buffered before being applied to the ADC, with a maximum input current of ±100µA. Suitable reference sources for the AD7899 include the AD680, AD780, RIF192, and ReF43 precision 2.5 V references.

Analog input section

The AD7899 is divided into three types: AD7899-1, whose input is configurable for a ±10 V or ±5 V input voltage range; AD7899-2, whose input is configurable for a 0 V to 5 V or 0 V to 2.5 V input voltage range ; AD7899-3, which handles an input voltage range of ±2.5 V. The amount of current flowing into the analog input depends on the analog input range and the analog input voltage. Maximum current flows when negative full scale is applied.

AD7899-1

Figure 2 shows the analog input portion of the AD7899-1. This input can be configured for ±5 V or ±10 V operation on the AD7899-1. For ±5 V operation, the VINA and VINB inputs are connected together and the input voltage is applied across both superior. For ±10 V operation, the VINB input is tied to AGND and the input voltage is applied to the VINA input. The VINA and VINB inputs are symmetrical and fully interchangeable.

For the AD7899-1, R1=4 kΩ, R2=16 kΩ, R3=16 kΩ, and R4=8 kΩ. Following the resistive input stage is the high input impedance stage of the track/hold amplifier.

The designed transcoding occurs in the middle of consecutive integer LSB values (ie 1/2 LSB, 3/2 LSB, 5/2 LSB, etc.). The LSB size is given by Equation 1 LSB=FSR/16384. For the ±5 V range, 1 LSB = 10 V/16384 = 610.4 μV. For the ±10 V range, 1 LSB=20 V/16384=1.22 mV. The output encoding is 2's complement binary, and the ideal input/output transfer function of LSB=FSR/16384AD7899-1 is shown in Table 1.

notes

FSR is the full-scale range, 20 V over ±10 V, 10 V over ±5 V, and VREF=2.5 V.

1. LSB=FSR/16384=1.22 mV (±10 V–AD7899-1) and 610.4 microV (±5 V–AD7899-1), VREF=2.5 V.

AD7899-2

Figure 3 shows the analog input section of the AD7899-2. Each input can be configured for 0 V to 5 V operation or 0 V to 2.5 V operation. For 0 V to 5 V operation, the VINB input is tied to GND and the input voltage is applied to the VINA input. For 0 V to 2.5 V operation, the VINA and VINB inputs are tied together and the input voltage is applied to both the VINA and VINB inputs are symmetrical and completely interchangeable.

For the AD7899-2, R1=4 kΩ and R2=4 kΩ. Again, the designed transcoding occurs on consecutive integer LSB values. For the 0 to 2.5 V and 0 to 5 V options, the output is encoded as direct (natural) binary of 1 LSB=FSR/16384=2.5 V/16384=0.153 mV and 5 V/16384=0.305 mV. Table II shows the ideal input and output transfer functions for the AD7899-2.

notes

FSR is the full-scale range, 0 to 2.5 V and 0 to 5 V for the AD7899-2 with VREF=2.5 V.

1. LSB=FSR/16384, 0.153 mV (0-2.5 V) and 0.305 mV (0-5 V) for AD7899-2 with VREF=2.5 V.

AD7899-3

Figure 4 shows the analog input portion of the AD7899-3 on the VINA input. The analog input range is ±2.5 V. The VINB input can be left unconnected, but if it is connected to a potential, that potential must be grounded.

For the AD7899-3, R1 = 4 kΩ, R2 = 4 kΩ resistor The input stage is followed by the high input impedance stage of the track/hold amplifier.

The designed transcoding occurs in the middle of consecutive integer LSB values (ie 1/2 LSB, 3/2 LSB, 5/2 LSB, etc.). The LSB size is given by Equation 1 LSB=FSR/16384 The output encoding is 2's complement binary, 1lsb=FSR/16384=5v/16384=610.4μV. The ideal input/output transfer function of the AD7899-3 is shown in Table 3.

Timing and Controlling Start Conversion

Conversions are initiated by applying a rising edge to the CONVST signal. This puts the track/hold into hold mode and begins switching the switching state indicated by the dual function signal BUSY/EOC. The AD7899 can operate in two conversion modes, EOC (end of conversion) mode and busy mode. The operating mode is determined by the CONVST state at the end of the conversion.

Select conversion clock

The AD7899 has an internal laser trimmed oscillator that can be used to control the conversion process. Alternatively, an external clock source can be used to control the conversion process. The highest allowed external clock frequency is 6.5MHz which means the conversion time is 2.46µs compared to 2.2µs using the internal clock. However, in some cases, when high throughput is not required, it may be useful to use an external clock. For example, two or more AD7899s can be synchronized by using the same external clock for all devices. This way, there is no delay between output logic signals due to the different frequencies of the internal clock oscillators.

On the rising edge of CONVST, the AD7899 will check the state of the CLKIN pin. If this pin is low, it will use the internal laser trimmed oscillator as the conversion clock. If the CLKIN pin is high, the AD7899 will wait for an external clock to be supplied to this pin before using it as the conversion clock. The first falling edge of the external clock should not occur for at least 100 ns after the rising edge of CONVST to ensure proper operation Figure 5 shows how the BUSY/EOC output is synchronized with the CLKIN signal. Each conversion requires 16 clocks. The result of the conversion is transferred to the output data register on the falling edge of the 15th clock cycle. When the internal clock is selected, the state of the CLKIN pin is free to change during conversion, but the CLKIN setup and hold times must be respected to ensure that the correct conversion clock is used. If the internal conversion clock is to be used, the CLKIN pin can also be permanently fixed at low.

EOC mode

The CONVST signal is usually high. Pulse CONVST low will check the state of the CONVST signal at the end of the conversion initiated by its rising edge. Since a conversion when this happens, the AD7899 BUSY/EOC pin will perform its EOC function and keep the BUSY/EOC line low for one clock cycle, then return high again. In this mode, EOC can be combined with RD and The CS signal is bound to automatically read the conversion results when needed. The timing diagram for operation in EOC mode is shown in Figure 6.

busy mode

The CONVST signal is normally low pulsed converter high will start the conversion on its rising edge and check the state of the CONVST signal at the end of the conversion. Since CONVST will be low when this happens, the AD7899 BUSY/EOC pin will assume its BUSY function, allowing BUSY/EOC is low, indicating that the conversion is complete BUSY/EOC will remain low until the next rising edge of CONVST BUSY/EOC returns high. The timing diagram for operation in busy mode is shown in Figure 7.

Continuous conversion mode

When the AD7899 is used with an external clock, connecting the CLKIN and CONVST signals together will cause the AD7899 to continuously perform conversions. Each time a conversion is complete, the BUSY/EOC pin will pulse low for one clock cycle (EOC function), indicating that the conversion results are available. Figure 8 shows the timing and control sequence of the AD7899 in continuous conversion mode.

Read data from AD7899

Reading data from the part via a 14-bit parallel data bus with standard CS and RD signals The CS and RD inputs are gated internally to transfer the conversion result onto the data bus. When both CS and RD are logic low, the data lines DB0 to DB13 remain in a high impedance state. Therefore, if desired, CS can be permanently tied to logic low and the RD signal used to access the conversion result. Figures 6 and 7 show a timing specification called "quiet time", which is the amount of time that should be left after a read operation and before starting the next conversion. Quiet time is highly dependent on the data bus capacitance, But the typical case is 50 ns to 100 ns, and the worst case is 150 ns.

Standby Mode Operation

The AD7899 has a standby mode, so the device can be put into a low current consumption mode (5µA typical). AD7899 Standby by taking the logic input low The AD7899 can be powered up again with the STBY logic high for normal operation. When the AD7899 is in standby, the output data buffer is still working. This means that the user can still continue to access the conversion results when the AD7899 is in standby. This feature can be used to reduce average power consumption in systems using low throughput. To reduce average power consumption, the AD7899 can be placed in standby at the end of each conversion sequence and taken out of standby again before the next conversion sequence begins. The time it takes for the AD7899 to come out of standby is called the "wake-up" time. This wake-up time will limit the maximum throughput at which the AD7899 can be operated when powered down between conversions. When the AD7899 is used with an internal reference, the reference capacitor will begin to discharge during standby. The residual voltage on the capacitor upon wakeup will depend on the standby time, affecting the wakeup time. The minimum wake-up time is usually 2 seconds. The maximum wake-up time is when the reference capacitor is fully discharged when the capacitor has been in standby long enough. In this case, the wakeup time is typically 15ms. When using an external reference, the AD7899 will wake up in about 1 second, regardless of sleep time.

Significant power savings can be achieved when operating the AD7899 in standby mode between conversions. For example, with a throughput of 10 kSPS and an external reference, the AD7899 will power up every 100 microseconds for 4.2 microseconds (2 microseconds for wakeup and 2.2 microseconds for transition). Therefore, the average power consumption drops to 80 MW x 4.2% or approximately 3.36 mW.

AD7899 Dynamic Specifications

The AD7899 is specified, 100% tested for dynamic performance specifications as well as traditional DC specifications such as integral and differential nonlinearity. These AC specifications are required for signal processing applications such as phased array sonar, adaptive filters and spectrum analysis. The application requires information about the effect of the ADC on the spectral content of the input signal. Therefore, the parameters specifying the AD7899 include signal-to-noise ratio, harmonic distortion, intermodulation distortion, and peak harmonics. These terms are discussed in detail in the following sections.

signal to noise ratio

SNR is the signal-to-noise ratio signal measured at the ADC output that is the rms value of the fundamental wave. Noise is the rms sum of all non-fundamental signals, excluding DC, and has a maximum value of half the sampling frequency (fS/2). The signal-to-noise ratio depends on the number of quantization levels used in the digitization process; the more levels, the less quantization noise. The theoretical SNR of a sine wave input is given by: SNR=(6.02N+1.76)dB(1), where N is the number of bits.

So, for an ideal 14-bit converter, the signal-to-noise ratio is 86.04db.

Figure 9 shows the histogram of 8192 dc input conversions using the AD7899 with a 5 V supply. The analog input is set at the center of the code transition. It can be seen that most of the codes appear in one output bin, which indicates that the ADC has very good noise performance.

The output spectrum of the ADC is evaluated by applying a very low distortion sine wave signal to the analog input. Fast Fourier Transform (FFT) plot generation can yield signal-to-noise data. Figure 10 shows a typical 4096-point FFT plot of the AD7899 with an input signal of 100 kHz and a sampling frequency of 400 kHz. The resulting signal-to-noise ratio from this plot is 80.5db. Harmonics should be considered when calculating the signal-to-noise ratio.

significant digits

The formula given in Equation 1 relates the signal-to-noise ratio to the number of bits. Rewriting the formula, as in Equation 2, can obtain a performance metric expressed in effective number of bits (N).

A device's effective number of bits can be calculated directly from its measured signal-to-noise ratio. Figure 11 shows a typical graph of the AD7899's effective number of bits versus frequency.

Intermodulation Distortion

When the input consists of sine waves of two frequencies (fa and fb), any active device with nonlinearity will produce distortion products at the sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2 , 3...etc. The intermodulation term refers to the intermodulation term for which both m and n are not equal to zero. For example, the second-order term includes (fa+fb) and (fa-fb), and the third-order term includes (2fa+fb), (2fa-fb), ( fa+2fb) and (fa-2fb).

The AD7899 is tested with two input frequencies. In this case, the second and third order terms have different meanings. The second-order term is usually farther away in frequency from the original sine wave, while the third-order term is usually at a frequency close to the input frequency. Therefore, the second- and third-order terms are specified separately. Intermodulation distortion calculations are performed according to the THD specification. , where it is the ratio of the rms sum of the single distortion product to the rms amplitude of the fundamental in dBs. In this case, the input consists of two equal amplitude low distortion sine waves. Figure 12 shows a typical IMD diagram for the AD7899.

AC Linear Graph

The graph in Figure 13 shows the typical DNL and INL of the AD7899.

Microprocessor interface

The high-speed parallel interface of AD7899 can easily interface with most DSPs and microprocessors. The AD7899 interface of AD7899 consists of data lines (DB0 to DB13), CS, RD and BUSY/EOC.

AD7899–ADSP-21xx interface

Figure 14 shows the interface between the AD7899 and the ADSP-21xx. The CONVST signal can be generated by the ADSP-21xx or other external sources. Figure 14 shows the CS generated by the combination of the DMS signal and the address bus of the ADSP-21xx. In this way, the AD7899 is mapped into the data memory space of the ADSP-21xx.

When a conversion is complete, the AD7899 BUSY/EOC line provides an interrupt to the ADSP-21xx. The conversion result can then be read from the AD7899 using a read operation. The AD7899 is read using the following instruction: MR0 = DM(ADC), where MR0 is the ADSP-21xx MR0 register, ADC is the AD7899 address.

AD7899–TMS320C5x interface

Figure 15 shows the interface between the AD7899 and the TMS320C5x. As with the previous interface, conversions can be initiated from the TMS320C5x or from an external source, and when the conversion sequence is complete, the processor interrupts the CS signal to the AD7899 derived from decoding of the DS signal and address bus. This maps the AD7899 into external data memory. The RD signal from the TMS320 is used to enable the ADC data on the data bus The AD7899 has a fast parallel bus, so no wait states are required AD7899 address.