1. Features

3V to 5.5V VCC range

The minimum output voltage is as low as 0.6 volts

1V to 35V input voltage range

Constant constant Topology on time

Quick load transient

0.6V, ± 1%vREF

optional sink mode

non -destructive current limit, available also under the bottom Sinking mode

Remote sensing

OVP, UVP atresia protection

600μA typical static current

Good power and OVP signal

Light underload The efficiency of the pulse jump

from 3.3V to 2.5V is 94%

2. Application

DC/DC module

[ 123] Distributed power supply

Mobile application

chipset, CPU, DSP, and memory

Equipment is an efficient networking solution DC/DC module and mobile applications compatible with 3.3V bus and 5V bus. It can adjust the output voltage as low as 0.6 volts. Constant time topology ensure fast load transmission response. Embedded voltage feedback provides almost constant switching frequency operations, although the input voltage range is wide. In the control loop, the integral device can be introduced to reduce the static output voltage error. Remote sensing improves static and dynamic performance regulation, and restores the voltage drop. The pulse jump technology reduces the power consumption under the negative load. The driver's current ability allows the output current to exceed 20A.

Table 5. Electrical characteristics

(VCC u003d VDR u003d 3.3V; ambient temperature u003d 0 ° C to 85 ° C, unless there are other regulations)

Table 5. Electrical characteristics (continued)

(VCC u003d VDR u003d 3.3V; ambient temperature u003d 0 ° C to 85 ° C, unless there are other regulations)

Device description

Constant Dit Pwm topology

Figure 5. The loop frame diagram

This device implements a constant pitch time control scheme, where TON is the duration of the duration of the high -side MOSFET by a disposable generator. The connection time and vsenseThe pins voltage is proportional, and the voltage of the osc pin is inversely proportional, such as EQ1:

in the formula, kosc u003d 180ns, τ is the delay time of internal communication (typical value. 40. 40. Nad second seconds). The system stabilizes the minimum connection time corresponding to VOSC u003d 1V. In fact, if VOSC voltage increases above 1V, the response time will not decrease. Connect the OSC pin to a voltage partition from VIN to GND, which allows the steady -state switch frequency FSW that is not related to the vehicle recognition number. The result is:

The above formula allows to set frequency frequency alphaosc after setting the output voltage; Note that these equations are established only when Vosc LT; 1V. In addition, EQ2 also explains how the system has an ideal switching frequency of input voltage. Delays the introduction of light related to VIN. In order to ensure the switching frequency after the capacitor charging and restricting the load, and the shielding PWM comparator output noise and peak.系统没有内部时钟，因为这是一个迟滞控制器，所以如果三个开启脉冲就会启动同时满足条件：FB引脚电压低于参考电压，最小关断时间通过，电流限制比较器未触发（即， Electric sensor current is lower than the current limit value). The voltage at the OSC pin must be between 50mv and 1V to ensure the system linear.

Closed circuit

The loop is closed, connecting the output voltage (or the midpoint of the output compressor) to the FB pin. The internal connection of the FB pin is connected to the comparator's negative pole pins, and the positive poles are connected to the reference voltage (0.6V typical value) as shown in Figure 5. When the FB is lower than the reference voltage, the PWM comparator output becomes higher and sets the trigger output to open the high side MOSFET. This situation is locked to avoid noise. After the connection time (as described in the previous section), the system reset the trigger, turn to close the high side MOSFET, and open the low side MOSFET. For more details, see Figure 4. The voltage drop of the grounding capacitors and loads and the voltage on the power supply metal path is DC electricity errors. In addition, the system adjusts the output voltage valley value instead of the average, as shown in Figure 6. Therefore, the voltage ripples on the output capacitor are the source of DC static errors (and PCB trajectories). In order to compensate the DC error, the integral network voltage must be introduced in the control loop through the connection output to the INT pin through the capacitor. The FB pin is directly connected to the int pin, as shown in Figure 7. Internal integrals and external capacitors CINT1 introduced a DC in the control loop. Cint1 also provides a communication path for output ripples.

The current of the integral amplifier generates a proportion of the proportion of the DC error, increasing the output capacitor to compensate for the total static error. The voltage pliers in the device forced the tube foot to generate an internal voltage range (VREF-50MV, VREF+150mv). This helps to avoid the output voltage during or smooth the load. At the same time, this means that the integrator can restore the output error caused by ripples in a steady state, when its peak-peak amplitude is less than 150mv. When the ripple amplitude is greater than 150mV, the ripple amplitude at the int at the int pin and ground can be reduced, otherwise the integror will work outside its linear range. Select CINT1 according to the following directions:

Among them, Gint u003d 50 μs is the cross -guided point of the integror, αout is the output division ratio given by EQ4, and the FU is a closed loop bandwidth. If CINT2 is connected between int pin and ground, this formula is established. Cint2 passes:

Among them, #8710; Vout is the output ripple, #8710; vint is the ripple required at the int (100mv typical value).

For the traditional PWM controller, it has an internal oscillator to set the switch frequency. In the physical system, the frequency can change with the change of certain parameters. For example, in the standard fixed switch frequency topology, the increase in loss (such as increasing the output current) will generate changes to the switching time. In the fixed connection time topology, the increase in loss will only generate changes in the turnover time, change the switching frequency Essence The device uses a voltage feedback circuit to keep the switch frequency constant during steady -state work and change within the input range. In the steady -state operation, there are many factors that affect the frequency accuracy of the switch. Some of them are internal dead areas, depending on the high side MOSFET drive. Others such as high -sides such as high -sides MOSFET grid charge and grid resistance, power supply voltage decrease and ground track, low -voltage and high -voltage side RDSON and electrocontrol parasites. During the positive load transient period (increased output current), the converter resumes the output voltage drop at its maximum frequency switch (the cycle is TON+TOFFMIN). The current is reduced during the negative load transient state), and the device stops switching (the high -voltage side MOSFET is closed).

The conversion from PWM to PFM/PSK

In order to achieve high efficiency under light load conditions, the PFM mode was provided. The PFM mode is basically related to different modes of PWM; the opening is the same. In PFM, after the circulation is connected, the system connects the low -side MOSFET until the inductance current drops to zero, and the low -side MOSFET is turned off as a zero comparator. In the PWM mode, after the power -on cycle, the system keeps the low -side MOSFET in the connection state until the next connection cycle, so the energy stored in the output capacitor will flow to the ground through the low -pressure side MOSFET. This PFM mode is naturally implemented in the lagging controller. By turning on the zero current comparator, in fact, in the PFM mode, the system uses the comparator to read the output voltage, and then turn on the high level as the output voltage to drop to the ginseng to the ginseng to the ginseng.During the test value, the side MOSFET. The device is light and high -load continuous working mode in the intermittent mode. When the load current is about half an inductor current ripple. This threshold depends on VIN, L and Vout. Please note that the higher the inductance value, the smaller the threshold. On the other hand, the greater the inductance value, the slower the speed of the transient response. PFM waveforms may be more noise and asynchronous than normal operations, but this is normal, mainly because the load is very low. If PFM is not compatible with the application, it can be disabled to connect with the Noskip of VCC.

Soft start

After the device is turned on, the SS pin voltage begins to increase, and the system begins to switch. Soft activation is achieved by gradually increasing the current limit threshold to avoid output overvoltage. Active soft starting VSS voltage range (output current limit linear increase) is 0.6V to 1V. In this range, the internal current source (5μA typical values) are charged on the capacitor on the SS pin; reference current (for current limit comparator) for compulsory through ILIM pins and SS pin voltage proportions, at 5μA (typical value) Under saturation. When the SS voltage is close to 1V maximum current restriction activation. Output protection OVP and UVP are disabled until the SS pin voltage reaches 1V (see Figure 8). Once the SS pin voltage reaches 1V, the voltage on the SS pin no longer affects the operation of the system. If the SHDN pin is opened before the power supply, the power supply must be opened before logic. If the power supply is applied under the disconnection of the SHND pins, the start order will not be taken time.

Since the system is achieved by controlling the inductance current, the soft startup capacitor should be VSS) Selection. In order to choose a soft startup capacitor, the output voltage must be reached to the final value of the starting voltage (1V). After this UVP and OVP are enabled. The time required to charge the SS capacitor to 1V is given by the following formulas:

In order to calculate the charging time of the output voltage, the inductor current function should be considered to assume that the linear function of time is assumed Essence

Therefore, considering that the output load is zero, the output voltage is:

current limit

] The current limiter compares the inductive electromot sensing current through the low side MOSFET RDSON, and compares this value with the voltage value of the ILIM pin. When the current is higher than the current limit value, the control

inhibits the opening of the high side MOSFET. To correctly set the current limit threshold, it should be noted that this is a valley current limit. The average current depends on the inductance value, VIN VOUT and switching frequency. The average output current in the current limit is drawn from the bottom formula:

Therefore, to set the current threshold, please select Rilim according to the following formula:

Under overcurrent conditions, the system keeps the current constant until the output voltage meets the underwriting threshold. For the Sink mode, the negative valley current limit is automatically set to the same value as the orthopedic current limit. The difference between the average negative current limit and the positive average current limit is that the ripple current; this difference is caused by the valley value control technology. The accuracy of the current restriction system is the RDSON accuracy connected to the ILIM pin and the low -side MOSFET. In addition, the voltage on the ILIM pin must be between 10mv and 1V to ensure the linearity of the system.

Protection and failure

Loading protection is achieved with vSense pins. Both OVP and UVP are locked, and the failure state is indicated by the PGOOD and OVP pin. If the output voltage is in the specified value between 89%(typical values) and 110%(typical values), PGOOD is high. If a hard overvoltage or owed voltage occurs, the device is locked: low side MOSFET and high side MOSFET are closed, and PGOOD becomes low. If the system detects the high voltage OVP pin. To restore the function, you must turn off the device and restart the SHDN pin, or re -start the device in the correct order by unloading the power.

The integrated large current driver allows the use of different sizes of power MOSFET to keep fast switch transformation. The driver of the high -voltage side MOSFET uses a starting pin to power, and the phase pins are used to return (floating driver). The low -end MOSFET driver uses VDR pins as a power supply, and PGND pins are used for circuit. This driver has adaptive anti -cross -conducting protection, which can prevent high -current from high and low -side MOSFETs at the same time, avoiding high currents from VIN to GND. When the high -sided MOSFET is closed, the voltage on the phase of the feet starts to decrease; only when the voltage on the feet reaches 250 millollers, the low side MOSFET is opened. When the low -voltage side is closed, the high -voltage side keeps off until the LGATE pin voltage reaches 500 millivolves. This is important because the driver can work normally with the large -scale external power MOS FET. Switch external MOSFET currently flows device, and it charges the switch frequency and drive voltage with the MOSFET grid. Therefore, the power consumption of the device is a function of the external power MOSFET gate charge and the switch frequency.

The maximum grid charge value of the low -voltage and high -voltage side is given by the following formula:

Among them Essence The above -mentioned square program is suitable for TJ u003d 150 ° C. If the system temperature is low, QG can be higher. For low -side drives, due to the degradation of the internal trajectory, the maximum loserOut of charge to meet another limit; in this case, the maximum value is qmaxls u003d 125nc. The low -side driver is designed as a low -resistant downward pull -up transistor, about 0.5 ohm. This can prevent the LS-MOSFET unexpectedly at the rapid rise of the pins. When using the 3.3V bus to power the driver, you should choose a super -logic MOSFET to ensure that the MOSFET work is normal.

Application information

5A demonstration board description

Demonstration board shows the equipment operation in this case: VIN from 3.3V to 5V, IOUT u003d 5A VOUT u003d 1.25V The assessment board allows two systems with different voltage (VCC is powered by IC, VIN is the power input so when the input capacitor is replaced, the power input voltage can also be 35V input voltage (VIN) equal to VCC, it is best to put it with 10 #8486; The resistor is connected to filter the input voltage. There are two different jumpers in the upper demonstration of the platform: a jump line, close to OVP and POW ER Good test points for closing the device; when the jump appears, the device is in the aircraft is in the jump line, the device is in the aircraft, the device is in the line, the device is in it, Turn off the status mode and run the device, please remove the jumper. Another cross -connected wire is close to the VREF test point to set the PFM/PSK mode. When the jumper exists, the system will enter the PFM mode; if the system will enter the PFM mode; if There is no jump line, when light load, the system will keep the PWM mode. There are two different jumps at the bottom of the demonstration. They are used to set or delete the integration of the integration. The jump of the label is opened and the integration configuration is set. Sometimes the integration of the integration requires a low -frequency filter to reduce noise interference. In this case, it is replaced by the closed INT jump, where a resistor is placed, and the capacitor is grounded (such as a schematic diagram. Show); the extreme value is about 500kHz, but it should be higher than the switch frequency (ten times). Open when the jump line named NOINT is closed, and when the jump line named NOINT is opened, the non -integral configuration is selected. Cross -wire connection, please refer to Table 1 and Table 2.