FM24C04U/05U –...

  • 2022-09-23 11:23:50

FM24C04U/05U – 4K-bit standard 2-wire bus interface serial EEPROM

General Notes: FM24C04 U/05U devices are 4096 -bit CMOS non-volatile devices Electrically Erasable Memory These devices meet all specifications in the standard IIC 2-wire protocol They are designed to minimize device pin count and simplify PC board layout requirements. The upper half of the memory of the FM24C05U (upper 2Kbit) is write protected by connecting the WP pin to VCC in this section. Then, the memory cannot be changed unless the WP is switched to VSS. This communication protocol uses a clock (SCL) and data I/O (SDA) lines to synchronize clock data between a host (such as a microprocessor) and a slave EEPROM device. Standard IIC protocol allows up to 16K EEPROM memory supported by the Fairchild family 2K, 4K, 8K and 16K devices allow user to configure the memory EEPROMs required by the application In order to achieve higher EEPROM memory density on the IIC bus, extended IIC must be used protocol. Fairchild EEPROMs are designed and tested for applications requiring high endurance, high reliability and low power consumption. block diagram

Features: Extended Operating Voltage 2.7V–5.5V 400 KHz Clock Frequency (F) at 2.7V-5.5V 200µA Typical Active Current Typical 10µA Backup Current Typical 1µA Backup Current (L) 0.1µA Typical Standby Current (LZ) IIC Compatible Interface – Provides Bidirectional Data Transfer Protocol Sixteen Bytes Page Write Mode – Minimizes Total Write Time per Byte Automatically Timed Write Cycle Typical Write Cycle Time is 6ms Upper Half Hardware write protection (FM24C05U only) Endurance: 1,000,000 data changes Data retention over 40 years Packages offered: 8-pin Dip, 8-pin SO, and 8-pin TSSOP Three temperature ranges - Commercial: 0° to +70°C - Extension (E): -40° to +85C - Auto (V): -40° to +125°C

Background Information (IIC Bus) The IIC bus allows simultaneous bidirectional communication between the transmitter and receiver using clock signals (SCL) and data signals (SDA) and three additional address signals (A2, A1, and A0) collectively referred to as "Chip Select" signal" to a device on the IIC bus (such as an EEPROM). All communications on the IIC bus must begin with a valid start condition (by the master), followed by a transfer (by the information byte (address/data). For each byte of information received, the address receiver provides a valid acknowledgment pulse to Communication continues further unless the receiver intends to abort the communication. Depending on the transfer direction (write or read), the receiver can be either a slave or a master. Typical IIC communication ends with a stop condition (by the master). Addressing an EEPROM memory location involves sending a Command string for the following information: [Device Type]-[Device/Page Block Select]-[R/W Bits]{Ack Pulse}-[Array Address]Slave Address The slave address is an 8-bit information field consisting of the device type (4 bits), Device/Page Block Select field (3 bits), and Read/Write bit (1 bit).

Device Type The IIC bus is designed to support various devices such as RAMs, EPROMs, etc., as well as EEPROMs so to correctly identify various devices on the IIC bus, the 4-digit "device type" identifier uses a string. For eeprom, this 4-digit character The string is 1-0-1-0 Each device on the IIC bus internally compares this 4-bit string to its own "device type" string to ensure correct device selection. Device/Page Block Select occurs on the IIC bus when there are multiple devices of the same type (such as multiple eeproms), then the A2, A1 and A0 address information bits are also used as part of the slave address. Each IIC device on the bus is on the IIC bus. Internally this 3-bit string is compared to its own physical configuration (pins A2, A1 and A0) to ensure correct device selection This comparison is a type of "compare" outside of "device" In addition to selecting EEPROM, this 3 bits are also used in selected EEPROMs. Each page block is 2Kbit (256Bytes) in size. Depending on the density, an EEPROM can contain at least 1 and up to 8 page blocks (in multiples of 2) And selection of page blocks within the device is achieved by using the A2, A1 and A0 bits. Read/Write Bit The last bit of the slave address indicates whether the intended access is a read or a write. If the bit is '1', it is a read access, while if the bit is '0', the access is a write.

Acknowledgment is on the SDA line from the addressed receiver to the addressed transmitter to indicate that the receiver is receiving 8-bit data The handshake mechanism has been completed for each 8-bit data received as follows: After sending 8-bit data, the transmitter releases the SDA line and waits for ACK Pulse address at 9th clock if receiver present, then release SDA line (to transmitter). See Fig. Array Address The array address is the memory location that contains the page block to be selected in the device.

16K-bit addressing limit: The standard IIC specification limits the maximum size of EEPROM memory on the bus to 16K-bits. This limit is due to the addressing protocol consisting of 8-bit slave addresses and an additional 8-bit field called the array address. This The array address is selected from 1 of 256 locations (28=256) Since the data format of the IIC specification is 8 bits wide, a total of 256 x 8=2048=2K bits can now be addressed by this 8-bit array address. These 2K bits are usually called "page blocks". Combining this 8-bit array address with a 3-bit device/page address (part of the slave address) allows up to 8 pages (23=8) of addressable memory since each page is 2K bits in size, 8 x 2K bits = 16K Bits are the maximum size of memory. This 16Kb of memory can be addressed on the standard IIC bus can be a single 16Kb EEPROM device or multiple variable densities (multiples of max) to a maximum of a total of 16Kb to meet the needs of more than 16Kb used on the IIC bus, but Another specification called "Extended IIC Specification".

Pin Description Serial Clock (SCL) The SCL input is used to clock all data to and from the device. Serial Data (SDA) SDA is a bidirectional pin used to transfer data to the device. It is an open-drain output that can be used with any number of open-drain or open-collector outputs. Write Protection (WP) (FM24C05U only) If bound to VCC, program operations are bound to the upper half (the upper half will not execute 2 bits of memory) Read operations are possible If bound to VSS, Normal operation is then enabled, and reading/rewriting the entire memory is possible. This feature allows the user to allocate the upper half of the memory to prevent accidental programming of the ROM. When writes are disabled, the slave address and word address will be acknowledged, but data will not be acknowledged.

This pin has an internal pull-down circuit. However, if write protection is not required on the system, it is recommended that the pin be tied to VSS. Device Select Inputs A2, A1, and A0 (as appropriate) These inputs are collectively referred to as the "Chip Select" signals. When there are multiple EEPROMs on the same IIC bus, these inputs, if present, should be connected to VCC or in a unique manner VSS is done to allow correct selection of EEPROMs in multiple eeproms In a typical addressing sequence, each EEPROM on the IIC bus compares the configuration of these inputs to the corresponding 3-bit "device/page block" selection" information (part of the slave address) to determine the selection e.g. if the 3-bit "Device/Page Block Select" is 1-0-1, then the EEPROM and A0 for the "Device Select Input" (A2, A1) are connected to VCC-VSS-VCC, is selected. Depending on the density, only the appropriate number of "device" select inputs are provided on the EEPROM for each "device" "select input" is used if not present on the device "device/page block select" ” field to select a “page block” inside the device, not the device itself.

Device Operation The FM24C04U/05U supports a bidirectional bus protocol. The protocol defines any device that sends data to the bus as a transmitter and a receiving device as a receiver. The device that controls the transmission is the master device that is controlled by the slave. The master will always initiate data transmission and provide transmission and received clock operations. Therefore, the FM24C04U/05U will be considered a slave in all applications. Clock and Data Conventions The data state on the SDA line can only change when SCL is low. SDA state changes during SCL high are reserved for indicating start and stop conditions. Start Condition All commands are preceded by a start condition, which is the high-to-low transition of SDA when SCL is high. The FM24C04U/05U continuously monitors the SDA and SCL lines for start conditions and will not respond to any commands until the condition is met. STOP CONDITION All communications are terminated by a STOP condition, i.e. a low-to-high transition of SDA while SCL is high to stop the FM24C04U/05U also use conditions to place the device in standby power mode unless a write operation is in progress, in which case A second stop condition is required to place the device in standby mode after the tWR period.

The FM24C04U/05U device will always respond with an acknowledgment after recognizing the start condition and its slave address. If the device has been selected and a write operation, the FM24C04U/05U will receive on each subsequent 8-bit byte. In read mode, the FM24C04U/05U slave will send 8 bits for data, release the SDA line and monitor whether there is a response on the line. If a response is detected, the FM24C04U/05U will continue to transmit data. If no response is detected, the FM24C04U/05U will Terminate further data transfers and wait for a stop condition to return to standby power mode. Device Addressing After a Start condition, the master must output the slave slave it is accessing. The most significant four-bit address is the address of the device type identifier. This is a fixed 1010 for all EEPROM devices.

All IIC EEPROMs use an internal protocol block size of 2K bits that defines pages (for word addresses 0x00 to 0xFF). Therefore, using address bits A0, A1 or A2 (if designated as "P") along with the word address to access the page block is used to access any single data byte. The last bit of the slave address defines whether a write or read condition is requested by the host with a "1" indicating that the operation will be performed, and a "0" initiating the write mode. A brief review: Under the condition that the FM24C04U/05U recognizes the post-start, the device connected to the IIC bus waits for the address transmitted by the slave device through the SDA line. If the sending slave address matches the address of one of the devices, the designated slave The SDA line is pulled low to signal and wait for further transmissions. Write Operation Byte Write For write operations, a second address field is required, which is an eight-bit word address that provides access to any of the 256 bytes in the selected memory page. After receiving the byte address, the FM24C04U/ 05U confirms again and waits for the next 8 bits of data, responds with confirmation and then the host terminates the transmission by generating a stop condition. At this time, the FM24C04U/05U starts the internal write cycle to the non-volatile memory. When the internal write cycle In progress, the FM24C04U/05U input is disabled and the device will not respond to any requests from the captain address during tWR see Figure 4, acknowledgment and data transfer sequence.

Page Write To minimize the write cycle time, the FM24C04U/05U provides a page write feature up to 16 consecutive bytes. Locations can be programmed all at once (instead of 16 individual byte writes). To facilitate this feature, memory arrays are organized in "pages" starting at every 16-byte address boundary (e.g. from array address 0x00, 0x10, 0x20, etc.) page writes restrict access to byte locations within a page. In other words, a single page write operation will not cross over to a location on another page, but will "roll over" to whenever the end of the page is reached and Display page continues to be accessed when other locations are displayed. Page write operations can start anywhere in the page (the starting address for a page write operation does not have to be page 1). Page writes are initiated in the same way as byte writes; but instead of terminating the loop after sending the first data byte, the host can send up to 15 further bytes. After each byte is received, the FM24C04U/05U will In response to using the acknowledge pulse, increment the internal address counter to the next address, and prepare to accept the next data. If the host should send more than 16 bytes before generating the stop condition, the address counter will "roll over" and the previously written data will be Overwrites operate like byte writes, with internal write cycles of address, acknowledgement, and data transfer sequence done.

Ack Polling Once a STOP condition is issued to indicate a write operation from the master, the FM24C04U/05U starts an internal write loop. ACK polling can start immediately. This involves issuing a START condition followed by the slave address for a write operation. If the FM24C04U/05U is still Busy write operation does not return acknowledgment If the FM24C04U/05U has completed a write operation, an ACK will be returned, and then the host can proceed with the next read or write operation. Write protected (FM24C05U only) programming of the upper half of the memory (upper 2Kbit) will not happen if the WP pin of the FM24C05U is connected to VCC. The FM24C05U will respond to the slave and byte address; however if the memory being accessed is write protected by the WP pin, the WP pinFM24C05U will not generate an acknowledgement after the first byte of data received so the program cycle will not occur when the stop condition is asserted start up.

Read operation The read operation starts in the same way as the write operation, except that the R/W bit address of the slave is set to 1, there are three basic read operations: current address read, random read and sequential read. Current Address Read The FM24C04U/05U contains an address counter internally to maintain the address of the last byte accessed, incremented by one. Therefore, if the last access (read or write) was at address n, the next read operation will start from address n +1 When receiving the slave address that R/W is set to first, the FM24C04U/05U sends an acknowledgment and sends an octet. The master does not acknowledge the transfer but does generate a stop condition, so the FM24C04U/05U stops transmitting address, acknowledgment and data transmission The sequence is shown in Figure 6. Random Read A random read operation allows the master to access any memory located in a random fashion Before issuing the slave address When the R/W bit is set to 1, the master must first perform a "dummy" write operation The master issues a start condition, the slave address , the R/W bit is set to zero, then the byte address has been read. After the byte address is confirmed, the master immediately sends another start condition and the slave address R/W bit is set to 1. Next is the confirmation of the FM24C04U/05U, Then the octet word The master does not acknowledge the transfer, but generates a stop condition, so the FM24C04U/05U stops the transfer regarding address, acknowledgement and data transfer sequence. Sequential reads Sequential reads can be initiated as current address reads or random access reads. The first word is transmitted in the same way as the other read modes; however, the host now responds with an acknowledgment that it The FM24C04U/05U requires additional data to continue for each acknowledgment read operation received by the host without an acknowledgment or generating a STOP condition. Data output is contiguous with data from address n followed by data from address n+1 Address counter operation for read increments all word address bits, allowing memory contents to be read contiguously in one operation after the entire memory has been read fetch, the counter "rolls over" to the beginning of the memory FM24C04U/05U continues to output the received data for each confirmation, see Figure Address, Confirmation and Data Transmission Sequence.