Features Industry Standard Pins Miller Plateau 4a High Current Drive Capability ±
Efficiently constant current source even at low supply voltages Supply voltage independent TTL/CMOS compatible input 20 ns typical rise time and 15 ns typical fall time under 1.8 nF load Typical propagation delay time: 25 ns when input falls ns, 35 ns for input rising
4-V to 15-V Supply Voltage Supply Current 0.3 mA Dual Output Parallelable Drive Current Provides Thermally Enhanced MSOP PowerPAD Components with 4.7C/W jc Trademark °θ
Temperature Rating - 40C to 85C°°
Application of switching power supply using TrueDrive output structure with bipolar and CMOS transistors in parallel
DC/DC Converter Motor Controller Line Driver
Class D Switching Amplifier Description
The UCC37323 /4/5 family of high-speed dual MOSFET drivers can source large peak currents into capacitive loads. Three standard logic options are available: dual inverting, dual non-inverting, and one inverting and one non-inverting driver. Thermally enhanced 8-pin PowerPADMSOP package (DGN) greatly reduces thermal resistance and improves long-term reliability. It is also standard Available in SOIC-8(D) or PDIP-8(P) packages. Trademarks These drivers feature an inherently minimal penetration current design, delivering 4 A of current block diagrams where the mill needs it most

Application Information General Information High-speed power supplies typically require high-speed, high-current drivers such as the UCC37323/4/5 family. A major application is where high power is required between the PWM output of a control IC and the gate of a main power MOSFET or IGBT switching device. Buffer Stage In other cases, the driver IC used to drive the gate synchronously rectified power supply of the power device through the drive transformer also needs to drive multiple devices at the same time, which can place a very heavy load on the control circuit.
When the main PWM regulator IC cannot directly drive the switching device for one or more reasons, using the driver IC PWM IC may not have the strong drive capability required to switch the MOSFETs expected, limiting the switching performance in the application. In other cases, It may be desirable to minimize the effects of high-frequency switching noise by placing high-current drivers physically close to the load. Additionally, newer ICs targeting the highest operating frequencies may not include onboard gate drivers at all. Their PWM outputs are only used to drive the drivers ( High impedance inputs such as the UCC37323/4/5) Finally, the control IC can be thermally stressed due to power dissipation, and an external driver can help by moving heat from the controller to the external package.
The input stage input threshold has 3.3-V logic sensitivity over the entire V voltage range; however, it is equally compatible with 0 V to V signals. due diligence due diligence
The inputs of the UCC37323/4/5 family of drivers are designed to withstand 500 mA of reverse current without any damage to the IC. The input stage of each driver should be driven by a signal with a short rise or fall time for this condition Satisfied in typical power supply applications where the input signal is driven by a PWM controller with fast transition times (<200ns) or logic gates. The input stage acts as a digital gate, they are not suitable for logic when reaching the input section threshold, applications that use a slowly varying input voltage to produce a switching output While this may not be detrimental to the driver, the driver's output may switch repeatedly at high frequency.
The user should not attempt to alter the input signal of the driver in order to slow down (or delay) the speed of the output signal. If it is necessary to limit the rise or fall time of the power device, the rise or fall time of the power device can be limited at the output of the driver and the load device. Adding an external resistor between (usually the power MOSFET gate) can also help eliminate power dissipation in the IC package, as described in the Thermal Factors section.
output stage
The inverted output of the UCC37323 and the output of the UCC37325 are designed to drive an external P-channel mosfet The non-converted output of the UCC37324 and the output of the UCC37325 are designed to drive an external N-channel mosfet.
Each output stage is capable of supplying ±4-A peak current pulses to VDD and GND and the oscillator driver's up/down circuit consists of a bipolar transistor and a MOSFET transistor in parallel. The peak output current rating is derived from the bipolar transistor and the MOSFET transistor. Combined current When the voltage on the driver output is less than the saturation voltage of the bipolar transistor, the output resistance is the R of the MOSFET transistor. Due to the body diode of the internal MOSFET, each output stage also provides very low overshoot and overshoot impedance. In many cases, external Schottky clamp diodes are not required. DS (on)
The UCC37323 family provides 4-A gate drive, which is most needed during MOSFET switching transitions in the Miller Plateau region, thereby improving efficiency. A unique bipolar and MOSFET hybrid output stage in parallel also allows efficient current sourcing at low supply voltages.
Source/Sink Capability During Miller Plateau High Power MOSFETs Put a Heavy Load on Control Circuits Efficient, Reliable Operation Requires Proper Drive UCC3323/4/5 Drivers have been optimized to provide maximum during the Miller Plateau region of switching transitions power to the power MOSFET. This interval occurs when the drain voltage swings between the voltage levels dictated by the power topology, requiring the drain-gate capacitance to be charged/discharged with current supplied or removed by the driver IC [1]
Two circuits were used to test the current capability of the UCC37323 driver. In each case, an external circuit was added to clamp the output close to 5 volts, while the IC was sinking or sourcing current. 250 ns input pulses were applied at 1 kHz at the corresponding On the appropriate polarity of the test In each test, there was a transient, the current peaked and then stabilized to a steady state value. The recorded current measurements were taken 200 ns after the input pulse was applied, at the initial transient after.
The first circuit is used to verify the current sink capability when the driver output is clamped around 5V, which is a typical gate-source voltage value in the Miller plateau region. The UCC37323 is found to sink 4.5A at V=15V and 4.28A at V=12V . due diligence due diligence

The application information circuit is used to test the capability of the current source, the output is clamped at around 5V, using a set of Zener diodes UCC37323 is 4.8A at VDD=15V and 3.7A at VDD=12V.

It should be noted that at lower VDD, the current sink capability is slightly stronger than the current source capability. This is due to the different structure of the bipolar MOSFET power output section, where the current source is a P-channel MOSFET and the current sink is an N-channel channel MOSFET.
In most applications, it is advantageous for the driver to have a stronger ability to turn off than to turn on. This helps to ensure that the MOSFET remains off during common supply transients, which may turn the device back on.
Parallel outputs By connecting the INA/INB inputs and the OUTA/OUTB outputs together, the A and B drivers can be combined into a single driver. A single signal can then control the parallel combination

It should be noted that at lower VDD, the current sink capability is slightly stronger than the current source capability. This is due to the different structure of the bipolar MOSFET power output section, where the current source is a P-channel MOSFET and the current sink is an N-channel channel MOSFET.
In most applications, it is advantageous for the driver to have a stronger ability to turn off than to turn on. This helps to ensure that the MOSFET remains off during common supply transients, which may turn the device back on.
Parallel outputs By connecting the INA/INB inputs and the OUTA/OUTB outputs together, the A and B drivers can be combined into a single driver. A single signal can then control the parallel combination

Operating Waveforms and Circuit Layout Circuit performance achievable with one driver (1/2 of an 8-pin IC) driving a 10nF load Input pulse width (not shown) set to 300 ns to show two transitions in the output waveform Note the switching waveform The linear rising and falling edges are due to the constant output current characteristic of the driver, rather than the resistive output impedance of traditional MOSFET-based gate drivers.

In power drivers operating at high frequencies, getting a clean waveform without overshoot/overshoot and ringing is a big challenge. The low output impedance of these drivers produces high di/dt waveforms which tend to be inductive in parasitic In the circuit layout, extra care must be taken to connect the driver IC as close as possible to the leads. The layout of the driver chip has a ground on the other side of the output, so the ground should be connected as wide as possible to the bypass capacitors and tape copper. Line loads on these connections should also be connected with a small closed loop area to minimize inductance.
Video Displays Although the quiescent VDD current is low, the total supply current will be higher, depending on the OUTA and OUTB currents and the programmed oscillator frequency. The total VDD current is the sum of the quiescent VDD current and the average output current. The operating frequency and the MOSFET gates are known. Charge (Qg), the average output current can be calculated by the following formula:
I=Qg xf, where f is the frequency out. For best high-speed circuit performance, two V bypass capacitors are recommended to prevent noise problems. Surface mount components are highly recommended. 0.1 micron ceramic capacitors should be located closest to the VDD ground connection. In addition, a larger capacitor with relatively low ESR (eg 1-µF) should be connected in parallel to help deliver high current peaks to the load. In driver applications, the parallel combination of capacitors should exhibit low impedance characteristics for the expected current levels. Due Diligence Drive Current and Power Requirements
The UCC37323/4/5 family of drivers are capable of delivering 4-A of current to the MOSFET gate for hundreds of nanoseconds. High peak currents are required to quickly turn the device on. Then, to turn off the device, the driver is required to bring a similar amount of current to ground. This is in the power supply device. This discussion is repeated on the operating frequency of the MOSFET because it is the most commonly used switching device in high frequency power conversion equipment.
References 1 and 2 discuss the current required to drive power MOSFETs and other capacitive input switching devices Reference 2 includes information on previous generation bipolar IC gate drivers.
When a driver chip is tested under a discrete capacitive load, it is a fairly simple matter to calculate the power required by the bias supply. The energy that must be transferred from the bias supply to charge the capacitor is given by:
Class E CV, where C is the load capacitor and V is the bias voltage that powers the driver.
When the capacitor discharges, an equal amount of energy is transferred to ground which results in power loss due to:
Page 2 CVf, where f is the switching frequency.
This energy is dissipated in the resistive elements of the circuit. Therefore, there is no external resistance between the driver and the gate. This power is dissipated inside the driver. Half of the total power is dissipated when the capacitor is charged, and the other half is dissipated when the capacitor is discharged. Use on A practical example of gate drive waveform conditions should help clarify this.
When V==10nF, f=300kHz, the power loss can be calculated as: due diligence 12V, C load
P=10nF x (12) x (300kHz)=0.432W2
For a 12 volt supply, this is equivalent to:
0.036 volts 12 volts P 0.432 watts The actual current measured from the power supply is 0.037A, which is very close to the predicted value. However, the I current due to internal IC consumption should be considered. When no load, the IC's current consumption is 0.0027A. In this case, the output rises and falls faster than the load due to cross-conduction in the output stage of the driver, which can result in barely significant but measurable currents. However, these tiny current differences are hidden in high-frequency switching spikes, Exceeding the measurement capability of a basic lab setup The current measured at a load of 10 nF is fairly close to the expected value. Due diligence The switching load created by a power MOSFET can be converted into an equivalent capacitance by sensing the gate charge required by the switching device. This gate charge consists of the input capacitance plus the additional charge required to swing the device drain between switching states. Affects specifications provided by most manufacturers, providing typical and maximum gate charge, in NC, switching devices under specified conditions. Using the gate charge, Qg, it is possible to determine the power that the capacitor must dissipate to charge. This is achieved by using the equivalent Qg=CeffV to provide the following power equation:
PCV 2 f Qg f type This equation allows the power designer to calculate the bias power required to drive a specific MOSFET gate at a specific bias voltage.
The usage range of thermal information drivers is greatly affected by the driving power requirements of the load and the thermal characteristics of the IC package. In order for the power driver to function within a specific temperature range, the package must be able to efficiently remove the heat generated while reducing the junction temperature. Stay within ratings The UCC37323/4/5 family of drivers is available in three different software packages to meet a range of application requirements.
As shown in the power dissipation rating table, both SOIC-8(D) and PDIP-8(P) packages have a power rating of around 0.5W at T=70°C. This limit is imposed along with the power derating factor given in the table. Note that in our previous example, the power loss was 0.432w, the load was 10nf, 12vdd, and the switching frequency was 300khz. Therefore, even with two onboard drivers in parallel, Also only one load of this size can be driven with a D or P package. Thermal difficulties limit the availability of drives in older packages. An MSOP PowerPAD-8 (DGN) package greatly alleviates this concern by providing an efficient way to remove heat from the semiconductor junction. As shown in Reference 3, the PowerPAD package provides a leadframe die exposed on the bottom of the package. Pad This pad is soldered directly to the copper on the PC board directly below the IC package, reducing Θjc to 4.7°C/W. The data presented in Reference 3 shows that in the PowerPAD configuration, the power dissipation can be increased by a factor of four compared to the standard package. The PC board must be designed with heat sinks and thermal vias to complete the thermal subsystem, as described in Reference 4. This results in a significant improvement in thermal performance over that of the D or P packages, and shows that the power performance of the D and P packages is more than doubled.
Note:
The power board  is not directly connected to any leads of the package, however, it is electrically and thermally connected to the substrate which is the ground for the device.
references
1. Power Symposium SEM-1400 Topic 2: Design and Application Guidelines for High Speed MOSFET Gate Drive Circuits, by Laszlo Balogh, Texas Instruments Literature Number: SLUP133.
2. Application Note, Practical Considerations for High-Performance MOSFET, IGBT, and MCT Gate Drive Circuits, by Bill Andreycak, Texas Instruments Literature Number: SLUA105
3. Technical Brief, PowerPad Thermally Enhanced Assembly, Texas Instruments Literature Number SLMA002
4. Application Brief, PowerPAD Make Easy, Texas Instruments Literature Number: SLMA004

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Lead-free (RoHS): The term "lead-free" or "lead-free" for titanium refers to semiconductor products that are compatible with current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in a homogeneous material if Designed for high temperature soldering, titanium-lead-free products are suitable for specified lead-free processes.
Lead-Free (RoHS Exempt): This assembly is RoHS exempt for 1) lead-based flip-chip solder joints used between the die and the package, or 2) lead-based die adhesives used between the die and the leadframe as described above By definition, this component is considered lead-free (RoHS compliant).
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MSL, Maximum Temperature - Moisture Sensitivity Rating according to JEDEC Industry Standard Classification and Peak Solder Temperature.
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