Features: Logically 4-Kbit Ferroelectric Random Access Memory (F-RAM) organized by 512 × 8 High Endurance 100 Trillion (1014) Read/Write 151 Year Data Retention Period (see Data Retention and Endurance Table) NoDelay 8482 ; Direct hardware replacement for writing to advanced high reliability ferroelectric process Fast 2-wire serial interface (I2C) serial (I2C) EEPROM at frequencies up to 1 MHz Active current at 4μA (typ.) Standby current Voltage operation: VDD=4.5 V to 5.5 VAEC-Q100 Grade 3 qualified industrial temperature: –40°C to +85°C? ? 8-pin Small Outline Integrated Circuit (SOIC) package compliant with Restriction of Hazardous Substances (RoHS)

Function description: FM24C04 B is a 4-Kbit non-volatile memory, using advanced ferroelectric process Ferroelectric random access memory or F-RAM is non-volatile and performs read and write operations similar to rams. It provides 151 years of reliable data retention eliminates the complexity, overhead, and reliability issues caused by non-volatility such as eeprom at the system level. Unlike eeprom, fm24c04b is at bus speed. No write delays are incurred. Data is successfully written to the device after each byte of the memory array is transferred to the device. The next bus cycle can start without data polling. In addition, the product offers memory with considerable write persistence compared to other non-volatiles.

Also, F-RAM shows lower power consumption during write operation because write operation does not require supply voltage boost for internal write circuit FM24C04B is able to support 1014 read/write cycles, i.e. 100 million write cycles more than eeprom times. These features make the FM24C04B ideal for non-volatile memory applications that require frequent or fast writes. Examples include data logging, where long write times to EEPROMs where cycles are critical for industrial control requirements can result in data loss. This combination of features allows more frequent data writes to reduce system overhead. The FM24C04B is a serial (I2C) EEPROM as a hardware replacement. Unit specifications are AEC-Q100 qualified and guaranteed for an industrial temperature range of -40°C to +85°C.

Functional overview: FM24C04B is a serial F-RAM memory memory array logically organized as 512 x 8 bits, and operates F-RAM similar to serial (I2C) EEPROM using the functions of the industry standard I2C interface. The main difference between FM24C04B and serial ( The same pin assignment between I2C) EEPROM is f-ram's superior write performance, high durability, and low power consumption. Memory structure When accessing the FM24C04B, the user address is 512. Each 8 data bit position. These eight data shift bits are continuously in and out. The I2C access address protocol is used, including a slave address (used to distinguish other non-memory devices), page Address bits and word addresses. The word address consists of 8 bits, and the page address is 1 bit to specify 256 addresses, so there are 2 pages of 256 locations. The 9-bit full address specifies that each byte address is unique. Access times for memory operations are essentially zero, exceeding those required by serial protocols. That is, the memory is read or written at the speed of the I2C bus, unlike serial (I2C) EEPROM, there is no need to poll the device ready status, because the write occurs at the speed of the bus when a new bus transaction can be transferred to the device The write operation is done in the interface section. Note that the FM24C04B does not contain power management circuitry other than a simple internal power-on reset. It is the user's responsibility to ensure that VDD is within the datasheet tolerances to prevent erroneous operation. I2C Interface The FM24C04B uses a bidirectional I2C bus protocol that uses very little pins or board space. Figure 2 shows a typical system based on a microcontroller fm24c04b configuration system. The industry standard I2C bus is familiar to many users but is described in this section. By convention, any device that sends data to the bus is a transmitter when the target device for this data is a receiver. The device that controls the bus is the master device The master is responsible for generating the clock signal for all operations. Any controlled device on the bus is a slave device. The FM24C04B is always a slave device. The bus protocol consists of sda and SCL signals with four conditions including start, stop, data bit or acknowledgment.

Stop Condition (P) When the bus master drives SDA, it indicates a stop state from low to high when the SCL signal is high. All operations using the FM24C04B should end in a stop state. If the operation is in progress when the assertion stop will be aborted for the assertion stop condition. START CONDITION When the bus master drives SDA, a START condition is indicated. SCL signal is high from high to low. All commands should be preceded by a START condition. The process can abort the operation at any time by using the START condition. The FM24C04B is ready for a new operation. If during operation, the supply falls below the specified VDD minimum, the system should be doing another.

Data/Address Transfer All data transfers (including addresses) are on SCL signal high except for the above three cases, when SCL is high, the SDA signal should not change. Confirmed/Unconfirmed Confirmation occurs when the 8th data bit is transferred in any transaction. In this state, the transmitter should release the SDA bus to allow the receiver to drive it. This receiver drives the SDA signal low to acknowledge receipt of a byte. If the receiver does not drive SDA low, a "no" acknowledgement is made and the operation is aborted. The recipient will deny it for two different reasons. The first is the byte transfer failure. In this case, no acknowledgement stops the current operation so that the device can address again which allows in the event of a communication error. Second, and most common, the receiver does not acknowledge intentionally ending the operation. For example, when operating during a read, the FM24C04B will continue to put data on the bus as long as the receiver sends an acknowledgment (and clock). When the read operation is complete and no more data is needed, the receiver cannot acknowledge the last byte. If the receiver acknowledges the last byte, this will cause the FM24C04B to try to drive the bus on the next clock while the master is sending a new command like stop.

Memory Operation The FM24C04B is designed to work very similarly to other I2C interface memory products. The main differences are due to the higher performance write capability of F-RAM technology. These improvements have resulted in some differences when writing and writing between the FM24C04B and a similarly configured EEPROM. The full operation of reading is explained below. WRITE OPERATIONS All writes begin with the slave address, followed by the word address the bus master does by setting the slave address (r/w bit) to "0". After addressing, the bus master sends each byte of data to the memory and the memory generates an acknowledge condition. Any number of sequences of bytes can be written. If the end of the address range is reached internally, the address counter will wrap from 1FH to 000h. Unlike other non-volatile memory technologies, there is no effective write latency of F-RAM. The access time to the underlying memory from read and write is the same, and the user has no delay on the bus. The entire memory cycle occurs in less than a single bus clock. Therefore, any operation involving a read or write can occur immediately afterward. Confirmation polling, a technique used with eeprom to determine whether a write is complete is unnecessary and always returns a ready state. Internally, the 8th data bit is shifted. It will be done before the acknowledgment is sent. Therefore, if the user wishes to do this without changing the memory contents, this should be done using start or stop before the 8th data bit condition FM24C04B does not use page buffering. The memory array can be write protected using the WP pin. Setting the WP pin to a high state (VDD) will write protect all addresses. The FM24C04B does not acknowledge data bytes written to protected addresses. Also, the address counter will not increment if an attempt is made to write to these addresses. Setting WP to a low state (VSS) will disable the write protection WP is pulled down internally.

There are two basic types of read operations. They are the latest address read and the selective address read. The read in the current address, the FM24C04B uses the internal address latch to power the lower 8 address bits in the selective In a read, the user performs the process of setting these lower address bits to a specific value. Current Address and Sequential Read As mentioned above, the FM24C04B uses an internal latch to provide a lower 8-bit address current for read operations. Address reads use the existing value in the address latch as the starting location for the read operation. The system starts from the address immediately following the last operation. To perform a current address read, the bus master provides the slave address with the LSB set to "1". This represents a read request operation. The page select bits in the slave address specify the memory block used for read operations. After receiving the complete slave address, the FM24C04B will start shifting out data from the current address on the next clock. The current address is the 8 bits of the slave address in the internal address latch. The bus master can read any number of bytes starting at the current address. So a sequential read is just a current read address through a multibyte transfer. The internal address counter will increment after each byte. Note that each time the bus master acknowledges a byte instructs the FM24C04B that the next sequential byte should be read.

There are four ways to properly terminate a read operation. If a read is not properly terminated, a bus will likely be created when the FM24C04B attempts to read additional data onto the bus. Four valid methods are: 1. The bus master issues a disable response at 9 o'clock on the 10th clock cycle Inner loop and stop as shown in the diagram below which is preferred. 2. The bus master issues an inhibit response at 9 o'clock to start the cycle on the 10th. 3. The bus master issues a stop command in the ninth clock cycle. 4. The bus master issues a start on the 9th clock cycle. If the internal address reaches 1FH, it wraps around to 000h on the next read cycle. Figures 9 and 10 below show the correct operation of the current address read.

Selective (random) read There is a simple technique that allows the user to randomly select an address location as the starting point for a read operation. This involves using the first two bytes of a write operation to set the internal address followed by a subsequent read operation. To perform a selective read, the bus master sends an address specifying the write operation with the slave LSB (R/W) set to 0. According to the write protocol, the bus master sends a load to the internal address latch. After the FM24C04B acknowledges the word address, the bus master issues a START condition which will simultaneously abort the write operation and allow reads issued when the slave address LSB is set to "1" Order. The operation is now to read the current address.

Endurance FM24C04B operates internally with read and restore function mechanism. Therefore, endurance loops apply to read or write loops. Memory structures are based on row and column arrays. Each read or write access results in a full row of endurance loops. In the FM24C04B, a row is 64 points wide. Each 8-byte boundary marks the A new pass frequently ensures that the accessed data is in a different row. In any case, F-RAM at 1 MHz, read and write endurance is practically unlimited at I2C speed Even with 3000 accesses to the same row per second, 1 trillion endurance cycles will not appear after 10 years.