The UC3902 Load Sharing Controller is an 8-pin device used to balance the current drawn from independent parallel power supplies. Load sharing is achieved by adjusting the output current of each power supply to a level proportional to the voltage on the shared bus.

The main supply is automatically designated as the supply regulated to the highest voltage, driving the shared bus at a voltage proportional to its output current. The uc3902 trims the output voltages of the other parallel power supplies so that they each support their share of the load current. Typically, each power supply is designed for the same current level, although this is not required for use with the UC3902. By properly adjusting the current sense resistor, power supplies with different output current capabilities can be supplied with the same percentage output current for a particular load capability of each power supply in parallel.

Application information must determine the values of the five passive components to configure the UC3902 load sharing controller. The output and return lines of each converter are connected together at the load, and a current sense resistor rsense is inserted into each negative return line. Another resistor, r, is also inserted into each positive sense line. The differential shared bus terminals (shared+ and shared-) of each UC3902 are connected together separately, and the shared node is also connected to the system ground. A typical application is shown in Figure 1. The design of the adjuvant disease load-sharing controller can be performed through the following steps:
first step.
Five shares (maximum)
RSENSE ACSA IO (max) (1)
When A is 40, the gain of the current sense amplifier CSA is at full load and the voltage drop across the R resistor is I × R. Taking into account the gain of the current sense amplifier, the voltage at full load on the current share bus, feel O(max) feel a CSA O(max)
VSHARE (max) RSENSE (2)
The voltage must be kept 1.5 volts below VCC or below 10 volts, whichever is less VStor represents the upper limit, but the designer should choose a fully scaled shared bus voltage, remember that every volt on the load shared bus will add Supply current increases by about 100 mA times the number of slave units connected in parallel.
Step two.
Five Adjustments (Max)
rg iadj (max) (3)
Care must be taken to ensure i is low enough so that both drive current and power dissipation are within the capabilities of the device. For most applications, I currents between 5-10 mA are acceptable. In a typical application, a 360 Ω RG resistor from the ADJR pin to ground sets IADJ(max) to about 5 mA. Adjust (max) Adjust (max)
third step.
VO (max) IO (max) RSENSE
RADJ IADJ (max) (4)
R must be low enough to not interfere with the proper operation of the converter's voltage feedback loop. Typical values of r are between 20Ω and 100Ω, depending on v, ∏v and the chosen value of i. Adjuvant Disease Adjuvant Disease O (max) Adjusted (max)
the fourth step.
kermi right adjective meaning right
CC 2 RG load ACSA APWR fC (5)
Calculate the shared loop compensation capacitor C to produce the desired shared loop unity gain crossover frequency f. The transconductance g of the shared loop error amplifier is nominally 4.5ms. The values of the resistors are known. Typically, f is set to be at least an order of magnitude lower than the closed-loop bandwidth of the converter. The load-sharing circuit is primarily used to compensate for each converter's initial output voltage tolerance and temperature drift, not for differences in its transient response. The term A is the gain of the power supply measured at the desired shared loop crossover frequency f. This gain can be measured by injecting a measurement signal between the positive output terminal of the power supply and the positive sense terminal.
Right Class C 2 First Floor Class C Class C Class C (6)
A resistor in series with C is required to improve the phase margin of the load sharing loop. The zero point is at the load sharing loop crossover frequency f.
When the system is powered on, the converter with the highest output voltage tends to supply the maximum current and controls the other converters on the shared bus to increase their output voltage until their output current is proportional to the shared bus voltage minus 50 mV due to the warm-up drift of each converter , load and line transient response differences, the converter as the main circuit may change.