feature

Conversion time: 6 microseconds; total unadjusted error: ±1/2LSB or ±1LSB; sample and hold: 375ns acquisition; 2, 4 or 8 input multiplexer options; 0 to 5V analog input range, single 5V; Power supply; scaled operation or up to 5V; voltage reference; no zero or full scale required; ML2281 capable of digitizing 5V, 40kHz sine waves; low power: 12.5mW max; advanced pin-compatible replacement for ADC0831; ADC0832, ADC0834 and ADC0838; analog input protection: 25mA (min) per input; now in 8-pin SOIC package (ML2281, ML2282).

General Instructions

The ML2801 family are 8-bit successive approximation A/D converters with serial I/O and configurable inputs for up to 8 input channels of multiplexers. All sample and cargo errors contained in the ML2281 series are in the analog-to-digital converter accuracy specification. The voltage reference can be set externally to any value between GND and VCC, thus allowing full conversion if desired over a relatively small voltage range.

The ML2281 series are enhanced dual poly CMOS pin compatible second sources for ADC0831, ADC0832, ADC0834 and ADC0838 A/D converters. The ML2281 series enhancements are faster conversion time, true sample and hold function, superior power supply rejection, improved AC common mode rejection, faster digital timing, low power consumption for all parameters with power supply guaranteed over temperature over voltage 5V ± 10% .

Function description

Multiplexer addressing

The design of these converters utilizes a sampled data comparator structure that provides differential analog inputs converted by successive approximation routines.

The actual converted voltage is always the difference between the specified "+" input terminal and "–" input terminal. The polarity of each input terminal of the pair being switched indicates the most positive line expected by the converter. If the specified "+" input is less than the "–" input, the converter will respond with an all-zero output code.

A unique input multiplexing scheme has been used to provide multiple analog channels with software-configurable single-ended, differential, or pseudo-differential options. Pseudo-differential option will convert the voltage difference between any analog input and the common terminal. A single converter assembly can now accommodate ground-referenced and true differential inputs as well as signals with arbitrary reference voltages.

A specific input configuration is assigned during the mux addressing sequence before starting a conversion. The MUX address selects which analog input to enable, and whether that input is single-ended or differential. In the differential case, it also assigns the polarity differential inputs of the analog channels to adjacent channel pairs only. For example, channel 0 and channel 1 may be selected as different pairs, but channel 0 or channel 1 cannot behave differently from any other channel. In addition to selecting the differential mode, the symbol can also be selected. Channel 0 can be selected as a positive input, channel 1 can be selected as a negative input, and vice versa. This programmability is illustrated by the mux addressing codes shown in Tables 1, 2, and 3.

The mux address is transferred into the converter via the di input. Since the ml2281 contains only one differential input channel with fixed polarity assignment, addressing is not required.

The common input line on the ml2288 can be used as a pseudo differential input. In this mode, the voltage on the COM pin is treated as the "–" input of any other input channel. This voltage does not have to be analog ground; it can be any reference voltage common to all inputs This feature is most useful in single-supply applications where analog circuits may be biased towards potentials other than ground and the output signals are all referred to as for this potential.

Since the input configuration is software controlled, it can be modified on each conversion as needed. One channel can be treated as a single-ended, ground-referenced input for one conversion; it can then be reconfigured to be part of a differential channel for another conversion. Figure 7 illustrates these different input modes.

digital interface

The block diagrams and timing diagrams in Figure 2-5 illustrate how the conversion sequence is performed. Conversion starts when cs is pulsed low. This line must be held low throughout the conversion. The converter is now waiting for the start bit and its MUX assignment word.

The clock is applied to the CLK input. On each rising edge of the clock, the data on DI is recorded into the MUX address shift register. The start bit is the first logical '1' that appears on the DI input (all leading zeros are ignored). After the start bit, the device allocates word timing for the mux in the next 2 to 4 bits.

When the start shift moves to the start of the MUX register, the input channel is assigned, and the conversion is about to begin. The interval 1/2 clock cycle is used for sample and hold settling through the selected mux channel. At this point, the sar state output goes high, indicating that a transition is in progress, ignoring the di input.

The DO output comes from high impedance and provides leading zeros for this one clock cycle.

When a conversion begins, the output of the comparator (indicating whether the analog input is greater or less than each successive voltage from the internal DAC) appears at the DO output on each falling edge of the clock. This data is the result of conversions being shifted out (msb first) and can be read immediately by external logic or the µp.

After 8 clock cycles, the transition is complete and the sar status line returns low to indicate a later 1/2 clock cycle.

During conversion, serial data is always shifted out msb first. After the transformation is complete, you can use lsb first to move the data out a second time, depending on the level of the SE input. For ml2288, if SE=1, data is first shifted out of msb only during conversion. If SE is brought low before the end of the transition (which is signaled by the high-to-low transition of SARS), then the data is shifted out again immediately after the end of the transition; this time LSB first If se goes low after the transition ends, then the data is shifted out again at the end of the transition. After se goes low, the lsb first data is shifted on the falling edge of the clock. For the ml2282 and 2284, the SE is internally clamped to the low-order bits, so the data is first shifted out of the msb, and then the first time out of the lsb at the end of the conversion. For the ML2281, SE is internally tied high, so data is only shifted out MSB once first.

When the CS input is high, all internal registers are cleared. If another transition is required, CS must do a high-to-low transition followed by the address information.

The DI input and DO output can be tied together and controlled via a bidirectional µP I/O bit with one connection. This is possible because the di input is only locked during the mux addressing interval, while the do output remains in a high impedance state.

refer to

The voltage applied to the reference input of these converters defines the voltage range (difference between V and V) of the analog input to which 256 possible output codes are applied. This device can be used in both ratiometric measurement applications as well as systems requiring absolute accuracy. Must connect reference pin max min

Typically 10K for a voltage source capable of driving a reference input resistor. This pin is the top of the resistor divider string used for successive approximation conversions.

In a ratiometric measurement system, the analog input voltage is proportional to the A/D reference voltage. This voltage is usually the system power supply, so the VREF pin can be tied to VCC. This technique relaxes the stability requirements of the system reference when the analog input and A/D reference move simultaneously, maintaining the same output code for a given input condition.

For absolute accuracy, the reference pin can be biased with a time and temperature stable voltage source when the analog input varies between specific voltage limits.

The maximum reference value is limited to the V supply voltage. However, the minimum value may need to be small to allow direct conversion of inputs with voltage spans less than 5V. Due to the increased sensitivity of the converter, special attention must be paid to noise pickup, circuit layout, and system error voltage sources when operating at reduced spans. cocos islands

Analog Input and Sample/Hold

An important feature of the ml2281 series devices is that they can be located at the analog signal source and then communicate with the control μp using only a few wires. This avoids long bus connections for the analog inputs, thereby reducing noise pickup on these analog lines. However, in some cases the analog inputs have large common-mode voltages and even some noise along with the valid analog signal.

The differential inputs of these converters reduce the effects of common-mode input noise. Therefore, if a common mode voltage exists at the "+" and "–" inputs, say 60Hz, the converter will reject this common mode voltage because it only converts the difference between the "+" and "–" inputs.

The ML2281 series has a true sample-and-hold circuit that samples both the "+" and "–" inputs. This simultaneous sampling with true S/H will give common mode rejection and AC linearity performance that is better than a device that does not sample both input terminals at the same time, and there is no true sample and hold capability. Therefore, the ML2281 series devices can reject the AC common mode signal from DC-50kHz, and maintain the linearity of the signal from DC-50kHz.

Before the start of the conversion, when the sampling switch is closed, the signal at the analog input is sampled during the interval The sampling window (s/h acquisition time) is 1/2 clk period wide, and it changes from high impedance state to low active state at do 1/2 clk cycle occurs before. When the sampling switch is closed at the beginning of the S/H acquisition time, the 8pF capacitor is put into the analog input terminal after 1/2 clock cycle, the sampling switch is turned on, and the signal of the analog input terminal is stored. When the s/h acquisition time ends, the analog input Any errors on will result in additional conversion errors. Care should be taken to allow sufficient charge or settling time from the power supply. If more charge or settling time is required to reduce these analog input errors, longer CLK periods can be used.

The ML2281X family improves atresia immunity. Each analog input has dual diodes to the power rail, and can inject at least ±25mA (typically ±100mA) into each analog input without causing latch-up.

Dynamic performance

signal to noise ratio

The signal-to-noise ratio (snr) is the signal-to-noise ratio measured at the output of the converter. The signal is the rms magnitude of the fundamental wave. Noise is the rms sum of all non-fundamental signals, up to half the sampling frequency. The signal-to-noise ratio depends on the number of quantization levels used in the digitization process; the more levels, the lower the quantization noise. The theoretical signal-to-noise ratio of a sine wave is given by

where N is the number of bits So for an ideal 8-bit converter, the signal-to-noise ratio is 49.92db.

Harmonic Distortion

Harmonic distortion is the ratio of the root mean square sum of harmonics to the fundamental. The total harmonic distortion (THD) of the ML2281 series is defined as:

Where V is the rms amplitude of the fundamental wave, and V, V, V are the rms amplitudes of the harmonics.

Intermodulation Distortion

When the input consists of sine waves of two frequencies (f and f), any active device with nonlinearity will produce distortion products of order (m+n) at the sum and difference frequencies of mf+nf, where m, n=0, 1, 2, 3 intermodulation terms refer to the intermodulation terms where m or n is not equal to zero. (IMD) Intermodulation Distortion Specification includes only second order terms (f+f) and (fA-fB) and third order terms (2fA+fB), (2fA-fB), (f+2f) and (f-2f) .

Zero error adjustment

The zero point of the A/D does not need to be adjusted. A zero offset is possible if the minimum analog input voltage value (VIN minimum) is not grounded. The converter can output a digital code of 00000000 for this minimum input voltage by biasing any V input at this V value. This takes advantage of the differential mode operation of the A/D. At minimum the zero error of the A/D converter is related to the position of the first riser in the transfer function, which can be measured by grounding the V- input and applying a small positive voltage to the V+ input. It is the transition of the output digital code from 00000000 The difference between the actual DC input voltage required to reach 00000001 and the ideal 1/2 LSB value (1/2 LSB=9.8mV at VREF=5.000VDC).

full scale adjustment

Full-scale adjustment can be done by applying a differential input voltage of 1-1/2 lsb from the desired analog full-scale voltage range, then adjusting the size of the vref input or vcc for the digital output code that has just changed from 11111110 to 11111111.

Adjustment of any analog input voltage range

If the A/D's analog zero voltage is moved away from ground (for example, to accommodate an ungrounded analog input signal), the new zero reference should first be adjusted properly. A V+ voltage equal to the desired zero reference voltage plus 1/2 LSB at (where LSB is calculated for the desired analog span, 1 LSB = analog span/256) is applied to the selected "+" input and should then be adjusted Zero reference voltage at the corresponding "-" input to get only a code transition of 00000000 to 00000001. Full scale adjustment should be done by forcing the V+ input voltage as follows:

where vmax = high end of analog input range; vmin = low end of analog range (offset zero), then vref or vcc voltage is adjusted to provide a code change from 11111110 to 11111111.

Parallel regulator

A unique feature of the ML2288 and ML2284 is the inclusion of a shunt regulator connected from the V+ terminal to ground, which is also connected through a silicon diode to the V terminal (ie, the actual converter supply), as shown in Figure 8. When When the regulator is on, the V+ voltage is limited to 11V set by the internal resistance ratio. A typical IV for a shunt regulator is shown in Figure 9. It is important to note that a resistance of 35kW is observed between v+ and gnd before the v+ voltage is high enough to turn on the shunt regulator (which happens around 5.5v). When the shunt regulator is not used, the V+ pin should be left floating or tied to GND. The temperature coefficient of the regulator is -22mV/°C.

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