Features: Wide input voltage range (2 to 24 volts) for mobile systems Superior dynamic response and voltage feedforward Average current mode control Low-side mosfet or precision overcurrent using sense resistor VCC Undervoltage lockout mode maximizes efficiency QSOP16, TSSOP16 300kHz or 600kHz operation

Application: Mobile PC Regulator Handheld Computer Power Supply

General Description: 5234 -ic/" title="FAN5234 Product Parameters, Documentation and Sourcing Information" target="_blank">FAN5234 PWM Controller Provides High Efficiency and Adjustable Output 0.9V to 5.5V Regulation Required for I Peripherals in /O, chipsets, memory banks or high performance laptops and internet devices. Synchronous rectification light load hysteretic operation results in efficiency under various loads. Hysteretic mode Operation can be disabled if PWM mode is required for all devices Load level. By using the rds(on) of the mosfet as the current sensing element. Feed-forward ramp modulation, average current mode control and internal feedback compensation provide fast response to load transients. The FAN 5234 monitors these when the soft start is complete, the output at Its set point. Built-in overvoltage protection prevents output voltage from exceeding 120 % of set value. When the overvoltage condition disappears, normal operation resumes automatically. Undervoltage protection latches off when output falls below 75% of set value After the chip is disconnected to complete the soft-start procedure, the adjustable overcurrent function monitors the output current by sensing the voltage drop across the lower mosfet.

Circuit Description Overview: The FAN5234 is a low voltage PWM controller for modern laptops, desktops and sub-notebooks. The output voltage of the controller can be set in the range of 0.9V to 5.5V by an external resistor separator. Synchronous buck converters can be used from uncontrolled DC sources (such as laptop batteries) with voltages ranging from 2V to 24V, or from regulated rail systems. In either mode of operation, the IC deviates from the +5V source. The pwm modulator employs input voltage feedforward control using average current mode, which simplifies feedback loop compensation and improves line regulation. This controller includes integrated feedback loop compensation which greatly reduces the number of external components. Depending on the load level, the converter can operate in fixed frequency pwm mode or hysteretic mode. Switching from PWM mode to hysteretic mode improves inverter light load efficiency and extends battery life time. In hysteresis mode, the comparator is connected to the master clock, allowing seamless transitions between operating modes and reduced channel-to-channel interaction. If frequency conversion operation is not required.

When the VIN is from the battery, the oscillator ramp amplitude is proportional to the VIN, providing voltage feedforward control to improve loop response. When in fixed mode, the oscillator ramp amplitude is fixed. Then, the operating frequency is determined based on the connection on the VIN pin (Table 1). Initialization and soft start Assuming en is high, initialize fan5234 when vcc exceeds the rising uvlo threshold. An internal power-on reset function disables the chip if VCC falls below the UVLO threshold.

The voltage at the positive input of the error amplifier is limited by the voltage at the SS pin, which is sourced with a 5mA current. Once the CSS is charged to VREF (0.9V) the output voltage will be in regulation. The time it takes for the SS to reach 0.9V is: where T0.9 is in seconds, if CSS is in μF. When SS reaches 1.5V, the power-good output is enabled to allow hysteresis mode. The converter is forced into PWM mode during soft-start.

Operating Mode Control The mode control circuit changes the converter's mode from PWM to hysteretic and vice versa, based on when the voltage polarity is lower the mosfet is conducting, just before the upper mosfet turns on. For continuous inductor current, the sw node is negative when the current mosfet is turned on. As shown in the figure, the inverter operates in a fixed frequency PWM mode. This mode of operation achieves high efficiency under rated load. When the load current drops where the inductor current flows through the lower mosfet in the "reverse" direction, the sw node becomes positive, changing the mode to hysteretic mode, thus achieving higher efficiency at low currents by reducing the effective switching frequency . To prevent accidental mode changes or "mode jitter" when the sw node is positive for eight consecutive clock cycles (see figure) the polarity of the sw node is at the end of the conduction time of the lower mosfet. On transitions between PWM and hysteretic modes the upper and lower mosfet off software nodes will "ring" based on the output inductance and parasitic capacitance of the SW node and settle at the value of the output voltage. The boundary value of the inductor current, where the current becomes discontinuous, can be estimated by the following expression

In contrast to hysteretic mode, the transition from hysteretic mode to pwm occurs when the sw node is negative 8 times in a row mode cycling. A sudden increase in output current also causes a switch from hysteretic mode to PWM mode. This increased load causes the output voltage to drop instantaneously due to the voltage drop esr across the output capacitor. If the load causes the output voltage (as shown by VSEN) to drop below the hysteretic regulation level (20 mV below VREF); on the next clock cycle, the mode changes to PWM. In hysteretic mode, the PWM comparator and its error The amplifier that provides control in PWM mode is disabled. The hysteretic comparator is activated. The hysterical low-side mosfet operates in a synchronous fashion. The voltage across it (VDS(ON)) is monitored, and when VDS (on) becomes positive (current flow), it turns off (return from the load) allowing the diode to block reverse conduction.

The PFM signal is terminated when the output voltage (VSEN) falls below the lower threshold (10mV below VREF) and when VSEN rises above the upper threshold (5mV above VREF). The switching frequency is mainly: 1. Diffusion between the two hysteresis thresholds 2. Illod 3. The output inductor capacitor ESR converts back to PWM (Continuous Conduction Mode or CCM) mode which occurs when the inductor current rises sufficiently large - in Stay positive for 8 consecutive cycles. This happens: In the formula, ∏vhysteresis=15mv, and esr is equal to the series resistance. The load current position for transitioning to pwm operation is usually higher than entering hysteretic mode due to different control mechanisms. Hysteresis mode can be disabled by setting the FPWM pin high. The current of the current processing section through the RSense resistor (ISNS) is sampled shortly after Q2 is turned on. The current is held and added to the output of the error amplifier. This effectively creates a current mode control loop. A resistor connected to the iSNS pin (RSENSE) sets the current gain feedback loop. For stable operation, the current feedback by the PWM comparator input should be set to 30% of the ramp amplitude within the maximum load range. and the line voltage The following expression estimates the recommended value of RSENSE as a function of the maximum load current (iload(max)) and the value of the mosfet RDS(on):

Because the tolerance of the current limit is strongly dependent on the ratio to the external resistor, if the voltage drop on the RSENSE switch node side is an accurate representation of the load current. When using a mosfet as a sensing element, the change in rds (on) results in a proportional change in iSN. This value does not vary only by device, but also has a typical junction temperature coefficient of about 0.4%/°C (refer to the MOSFET datasheet for actual values), so the current limit setting will scale down the mosfet die temperature. A current factor of 1.6 The limit setpoint should compensate for all mosfet rds (on) changes, assuming the mosfet's heat sink will keep its working die temperature below 125°C.

This region is also associated with a phase "bump" or "reduced" phase shift. The amount of phase shift reduction depends on the width of the flat gain region and has a maximum value of 90 degrees. To further simplify converter compensation, the modulator gain is independent of the input voltage by providing the oscillator with a forward varying ramp of the VIN. Zero frequency, amplifier high frequency gain and modulator gain selected to suit most typical applications. The crossover frequency will appear at the point where the modulator attenuation equals the amplifier high frequency gain. The only task the system designer must complete is to specify the location of the output filter capacitors where the dominant pole of the load is somewhere below the zero frequency of the amplifier within a decade. With this compensation due to the pole-zero, it is easy to obtain sufficient phase margin to pair the phase "boost". Only when the main load pole is positioned too far to the left of the axis in frequency due to excessive output filter capacitance. In this case, ESR zeros in the range 10KHz...50KHz give some additional "boost" stage. Fortunately, in mobile applications, the trend is to keep the output capacitor as small as possible. Protection The inverter output is monitored and protected against extreme overload, short circuit, overvoltage and undervoltage conditions.

A sustained overload on the output will set the pgood pin low to lock up the entire chip. Operation is possible by cycling the VCC voltage or by toggling the EN pin. If VOUT falls below the undervoltage threshold, the chip shuts down immediately. Overcurrent Sensing If the circuit's current limit signal ("ILIM DET", as shown) is high at the beginning of the clock cycle, a pulse skipping circuit is activated and HDRV is inhibited. The circuit continues to jump in this manner for 8 clock cycles. If the cycle is at any time between 9 and 16, the "ILIM DET" is reached again, the overcurrent has set the protection latch, the chip is disabled, and if the "ILIM det" is not occurred between cycles 9 and 16, normal operation is resumed, The overcurrent circuit resets itself.

Over-Voltage/Under-Voltage Protection If VSEN voltage exceeds 120% of VREF (0.9V), for upper mosfet failure, or for other reasons, the over-voltage protection comparator will force LDRV high. This action will actively pull down the output voltage and eventually blow the battery fuse if the mosfet above fails. Once the output voltage drops to the threshold, the OVP comparator turns off. This OVP scheme provides a "soft" crowbar function that helps address severe load transients and does not latch the output voltage at startup - a common problem with OVP schemes. Likewise, if an output short circuit or severe load transient causes the output to drop below 75% of its regulation setpoint. If this happens, the regulator will close down. The over temperature protection chip integrates an over temperature protection circuit when the die temperature reaches about 150 degrees Celsius. Normal operation resumes when the mold temperature falls below 125 degrees Celsius and maintains an internal power-on reset, resulting in a full soft-start cycle.