feature

User programmable gain 1 to 10000 ; low gain error: 0.02% max; low gain tc: 5ppm/c (max); low nonlinearity: 0.001% max; low offset voltage: 25 V; low noise 4nv/Hz (1khz ) RTI√; Gain Bandwidth Product: 25 MHz; 16-lead ceramic or plastic dipping package,; 20-terminal LCC package; standard military drawings available; MLL standard parts available; low cost.

Product Description

The AD625 is a precision instrumentation amplifier designed specifically to implement two main application areas: 1) circuits requiring non-standard gains (i.e. gains not easily achieved by devices such as the AD524 and AD624) 2) requiring low-cost, high-precision software Circuit for programming gain amplifiers.

For low noise, high common-mode rejection ratio, and low drift, the AD625JN is the most cost-effective instrumentation amplifier solution. Three additional resistors allow the user to set

1 to 10000. The error contribution of the AD625JN is less than a 0.05% gain error and a gain TC of 5ppm/°C; the performance limit is mainly determined by the external resistors. Common-mode rejection is independent of feedback resistor matching.

A software programmable gain amplifier (SPGA) can be configured by adding a CMOS multiplexer (or other switching network) and a suitable resistor network. Since the on-resistance of the switch is removed from the signal path, an AD625-based SPGA will provide 12-bit accuracy and can be programmed for any gain set between 1 and 10,000, with a completely user-selectable gain order.

For the highest accuracy, the AD625C provides an input bias voltage drift of less than 0.25 V/°C, an output offset drift of less than 15 V/°C, and a maximum nonlinearity of 0.001% at G=1. All grades exhibit excellent AC performance; 25 MHz gain bandwidth product, 5 V/µs slew rate and 15 µs settling time.

The AD625 is available in three accuracy grades (A, B, C) for the industrial (–40°C to +85°C) temperature range and two grades (J, K) for the commercial (0°C to +70°C) temperature range temperature range, one grade (S) is available for extended (–55°C to +125°C) temperature range.

Product Highlights

1. The AD625 provides up to 16 bits of precision for user-selected fixed gains, from 1 to 10,000. Any gain within this range can be programmed by 3 external resistors.

2. A 12-bit software programmable gain amplifier can be configured using an ad625, a cmos multiplexer and a resistor network. Unlike previous instrumentation amplifier designs, the on-resistance of the cmos switch does not affect gain accuracy.

3. The gain accuracy and gain temperature coefficient of the amplifier circuit mainly depend on the external resistor selected by the user.

4. The AD625 provides completely independent input and output cancellation terminals for high-precision applications. This minimizes the effect of bias voltage in gain ranging applications.

5. The proprietary design of the AD625 provides an input voltage of 4 nV/√ at 1 kHz. hertz

6. No external resistor matching is required to maintain high common mode rejection.

Typical Performance Characteristics - AD625

theory of operation

The AD625 is a monolithic instrumentation amplifier based on a modification of the traditional three op amp approach. Monolithic construction and laser wafer trimming allow for tight matching and tracking of circuit components. This guarantees an inherent high performance level of the circuit structure.

The preamp section (Q1–Q4) provides additional gain for A1 and A2. Feedback from the outputs of A1 and A2 forces the collector current of Q1-Q4 to remain constant, affecting the input voltage of RG. This produces a differential voltage at the outputs of a1 and a2 that is multiplied by the gain (2rf/rg+1) by the input The differential portion of the voltage is given. Unity gain subtractor a3 removes any common mode signal from the output voltage, resulting in a single-ended output vout (referenced to the potential at the pin).

The value of rg is the determining factor for the transconductance of the input preamplifier stage. Transconductance increases as rg decreases for greater gain. This has three important advantages. First, this approach allows the circuit to achieve very high open-loop gains (3 × 108 for programmed gains ≥500), thereby reducing gain-related errors. Second, the gain-bandwidth product, determined by c3, c4, and the input transconductance, increases with gain, optimizing the frequency response. Third, the input voltage noise is reduced to a value determined by the collector current of the input transistor (4nv/√).

input protection

Differential input amplifiers often encounter input voltages that exceed their linear operating range. When applying input protection for the AD625, there are two considerations; 1) the continuous input current must be limited to less than 10 mA and 2) the input voltage cannot exceed more than one the diode drops (approximately 0.6 volts @ 25°C).

Under differential overload conditions, (Rg + 100) is connected in series between the positive and negative inputs of two diode drops (about 1.2 V), in either direction. Without external protection and with a very small RG (ie 40Ω), the maximum overload voltage that the AD625 can withstand is approximately ±2.5. Figure 26A shows the external components necessary to protect the AD625 under all overload conditions at any gain.

The diodes of the power supply are only required when encountering input voltages outside the range of the power supply. In high-gain applications where the differential voltage is small, as shown in Figure 26b, a back-to-beek zener diode and a small resistor provide adequate protection. Figure 26C shows a low cost FET, with a maximum on-resistance of 300Ω, configured to provide input protection with minimal noise reduction, (5.2 nV/^ vs. 4 nV/y normal noise performance).

During a differential overload condition, excess current will flow through the gain sense lines (pins 2 and 15). This has no effect on fixed gain applications. However, this current should be considered if the AD625 is being used in an SPGA application with a CMOS multiplexer. The current capability of the multiplexer may be the limiting factor in allowing overflow current. When calculating the necessary input protection resistance, the on-resistance of the switch should be included as part of RG.

Any resistor in series with the input of the AD625 will degrade noise performance. Therefore, if the gains are all greater than 5, the circuit in Figure 26b should be used. For gains less than 5, the circuit in Figure 26a or Figure 26c can be used. The two 1.4 kΩ resistors in Figure 26a will reduce the noise performance to:

Resistor Programmable Gain Amplifier

In resistor programming mode (Figure 27), only three external resistors are required to select any gain between 1 and 10,000. Depending on the application, discrete components or pre-boundary networks can be used. Gain accuracy and gain tc are primarily determined by external resistors, as the AD625C contributes less than 0.02% to gain error with gain tc at 5ppm/°C. The gain-induced current is insensitive to common-mode voltage, making the common-mode rejection ratio of the resistors that program the AD625 independent of the matching of the two feedback resistors, RF.

Choose resistor value

As previously mentioned, each rf provides feedback to the input stage and sets unity gain transconductance. These feedback resistors are provided by the user. The AD625 was tested with a specified RF value of 20 kΩ. Since the magnitude of the rto error increases with the feedback resistance, values much higher than 20 kΩ are not recommended (rf values below 10 kΩ may cause instability). When choosing a feedback resistor, refer to the RTO noise, offset, drift, and bandwidth graph (Figure 28). The gain resistor (rg) is given by:

A list of standard resistors that can be used to set some common gains is shown in Table 1.

For single-gain applications, only one offset zero adjustment is required; in these cases, the rti zero should be used.

Sensing terminal

The sense terminal is the feedback point for the AD625 output amplifier. Usually it is connected directly to the output. If heavy load currents are to be drawn through long leads, the voltage drop across the lead resistance will cause errors. In these cases, the sensing terminal can be connected to the load, thereby bringing the I×R down “in the loop,” virtually eliminating this source of error.

Typically, IC in-amps are rated for a full ±10 volts at 2 kΩ. However, in some applications more current needs to be driven into heavier loads. Figure 29 shows how to connect a high-current amplifier "in the loop" of an instrumentation amplifier. By using an external power boost circuit, the power dissipated by the AD625 will be kept low, thereby minimizing errors due to self-heating. The loop gain of the AD625 output amplifier reduces buffer nonlinearity, offset, and gain errors. Impact.

Reference terminal

The reference terminal can be used to offset the output voltage up to ±10 V. This is useful when the load is "floating" or does not share ground with the rest of the system. It also provides a way to inject precise offsets directly. However, it must be remembered that the total output swing is ±10 volts, from ground, shared between the signal and reference offset.

The AD625 reference terminal must have nearly zero impedance. Any significant resistance, including those caused by pc layout or other connection techniques, will increase the gain of non-vertical signal paths, disrupting the in-amp's common-mode rejection. Accidental thermocouple connections made in the sensor and reference lines should also be avoided as they will directly affect the output bias voltage and output bias voltage drift.

In the AD625, the reference source resistor will unbalance the CMR trim by a ratio of 10 kΩ/rref. For example, if the reference source impedance is 1Ω, the cmr will be reduced to 80 db (10 kΩ/1Ω = 80 db). An op amp can be used to provide a low impedance reference point, as shown in Figure 30. The input bias voltage characteristics of this amplifier will directly increase the output bias voltage performance of the instrumentation amplifier.

The circuit of Figure 30 also shows a CMOS DAC operating in bipolar mode and connected to the reference terminal to provide software controllable offset adjustment. The total offset range is equal to ±(vref/2 × r5/r4), but is symmetrical, approximately is 0 v r3=2×r4.

The offset per bit is equal to the total offset range divided by 2n, where n = the number of bits of dac. The offset range in Figure 30 is ±120 mV, and the offset is incremented in 0.9375 mV/LSB steps.

Using the sense and reference terminals shown in Figure 31, the instrumentation amplifier can be converted into a voltage-to-current converter.

By establishing a reference on the "low" side of a current setting resistor, the output current can be defined as a function of input voltage, gain, and the value of that resistor. Since only a small current is required at the input of the buffer amplifier a1, the forced current il will largely flow through the load. The offset and drift specifications of A2 must be added to the output offset and drift specifications of the input amplifier.

Input and output bias voltage

Offset voltage specification is often considered an advantage of instrumentation amplifiers. While the initial offset can be adjusted to zero, the shift in the offset voltage due to temperature changes will cause errors. Smart systems can often correct for this factor with an auto-zero cycle, but this requires additional circuitry.

Bias voltage and bias voltage drift each have two components: input and output. The input offset is the component of the offset generated during the input stage. When measured at the output, it is proportional to the gain, i.e. the input offset measured at the output at G=100 is 100 times larger than the measurement at G=1. The output offset is generated at the output and is constant for all gains.

The input offset and drift are multiplied by the gain, while the output term is independent of the gain, so the input error dominates at high gains and the output error dominates at low gains. The output offset voltage (and drift) is typically specified as g=1 (input effects are insignificant), while input offset (and drift) is given at high gain (output effects are negligible). All input-related parameters are specified as inputs (rti), i.e. the effect on the output is times "g". The offset voltage to the power supply is also specified as the rti error.

By separating these errors, the total error can be calculated independently of the gain. For a given gain, these two errors can be combined by the following formula to give the total error at the input (rti) or output (rto):

Total error rti = input error + (output error/gain)

Total error rto = (gain × input error) + output error

The AD625 provides input and output bias voltage adjustment. This simplifies nulling in very high precision applications and minimizes offset voltage effects in switching gain applications. In this application, the input offset is adjusted first at the highest programmed gain, and then the output offset is adjusted at g=1. If only one null value is required, the input offset null value should be used. The maximum additional drift using only the input offset zero is 0.9 µV/°C, rto.

Common Mode Rejection

Common-mode rejection is a measure of the change in output voltage when the two inputs change by an equal amount. These specifications are usually given for full range input voltage variation and specified power supply imbalance.

In instrumentation amplifiers, the reduction in common-mode rejection is due to phase differences due to differences in distributed stray capacitance. In many applications, shielded cables are used to reduce noise. This technique can create common mode rejection errors unless the shield is properly driven. Figures 32 and 33 show an active data protection device configured to minimize differential phase shift by "bootstrapping" the capacitance of the input cable to improve AC common-mode rejection.

ground

To isolate low-level analog signals from the noisy digital environment, many data acquisition parts have two or more ground pins. These reasons must eventually be connected at some point. It is convenient to use a single ground wire, however, the current through the ground wire and the circuit card running on the PC can cause errors of hundreds of millivolts. Therefore, a separate ground return should be provided to minimize the trip from sensitive points to system ground. current (see Figure 34). Since the output voltage of the AD625 is developed with respect to the potential on the reference terminal, it can solve many grounding problems.

Bias Current Ground Return

The input bias current is the current necessary to bias the input transistors of the DC amplifier. These currents must have a direct return path, otherwise they can charge external capacitors, causing the output to drift uncontrollably or saturate. Therefore, when amplifying a "floating" input source such as a transformer or AC-coupled source, as shown in Figure 35, There must be a DC path from each input to ground.

Auto-zero circuit

In many applications, high accuracy must be maintained. At room temperature, the offset effect can be eliminated by using an offset trimmer, however, in the operating temperature range, offset nulling becomes a problem. For these applications, the auto-zero circuit in Figure 36 provides a hardware solution.

Other considerations

Offset caused by thermocouples is a relatively overlooked problem when designing ultra-low drift DC amplifiers In circuits composed of two different conductors (i.e. copper, kovar), when the two junctions are at different temperatures, the current flow. When the circuit is broken, a voltage called a "Seebeck" or thermocouple EMF can be measured. Standard ic lead material (kovar) and copper form a thermocouple with a high thermoelectric potential (about 35 μv°c). This means that care must be taken to ensure that all connections, especially those in the AD625 input circuit, are kept constant. This includes input leads (1, 16) and gain sense lines (2, 15). These pins were chosen for symmetry to help reduce the sensitivity of the input circuit to thermal gradients. Also, the user should avoid airflow on the circuit, as the airflow will slowly fluctuate and the thermocouple voltage will have a "flicker" noise. In SPGA applications, both the relay contacts and the cmos mux leads are potential sources of additional thermocouple error.

The base-emitter junction of the input transistor can correct for out-of-band signals (ie, radio frequency interference). When amplifying small signals, these rectified voltages act as small DC offset errors. The AD625 allows direct access to the base of the input transistors and the transmitter, enabling the user to apply some first-order filtering to these unwanted signals. In Figure 37, the RC time constant should be chosen for the desired attenuation of the interfering signal. In the case of a resistive sensor, a capacitance operating only on the sensor's internal resistance is sufficient.

These capacitors can also be used as part of an external input protection circuit (see the Input Protection section). As a general practice, every effort should be made to match the external capacitors at pins 15 and 2 and pins 1 and 16 to maintain high AC CMR.

Software Programmable Gain Amplifier

SPGAs provide the ability to externally program precision gains from digital inputs. Historically, a problem in systems requiring gain electronic switching has been the on-resistance (ron) of the multiplexer, which occurs in series with the gain setting resistor rg. This leads to large gain errors and gain drift. The AD625 eliminates this problem by providing gain drive and gain sense pins (pins 2, 15, 5, 12; see Figure 39). Therefore, the turn-on of the multiplexer Resistors are removed from the signal current path. This converts the on-resistance error into a small adjustable zero-offset error. To illustrate this, an error budget analysis was performed in Table II based on the SPGA configuration shown in Figure 39.

Figure 38 shows an AD625 based SPGA with possible gains of 1, 4, 16, 64. rg is equal to the resistance between the gain sense lines (pins 2 and 15) of the AD625. In Figure 38, RG is equal to the sum of the two 975Ω resistors and the 650Ω resistor or the 2600Ω resistor rf is equal to the resistance between the gain sense and gain drive pins (pins 12 and 15, or pins 2 and 5), That is, rf is equal to the 15.6 kΩ resistor plus the 3.9 kΩ resistor, or 19.5 kΩ. Therefore, the gain is equal to:

When the switches of the differential multiplexers are synchronized, rg and rf change, resulting in various programmed gain settings.

Figure 39 shows a complete SPGA powering a 12-bit DAS with an input range of 0 V–10 V. This configuration is used for the error budget analysis shown in Table 2. The gain used for the RTI calculation is set to 16. When the gain is changed, the on-resistance and feedback resistance of the multiplexer will change, which will slightly change the values in the table.

notes

1. The resistor used for this calculation is the user-supplied feedback resistor (rf). The recommended value is 20 kΩ (see the Resistor Programmable Gain Amplifier section).

2. The leakage currents (Is and Iout) will cause an offset voltage, however, the offset will be determined by the difference between the leakage currents of each "half" of the differential multiplexer. The differential leakage current is multiplied by the feedback resistor (see Note 1) to determine the offset voltage. Since the differential leakage current is not a parameter specified in the multiplexer datasheet, the calculations in Table II using the maximum difference (one most positive, one most negative) typically perform better.

The on-resistance and internal capacitance of the multiplexer can affect frequency response and stability. Figure 40 shows settling time vs. On-resistance of an AD625-based SPGA at different gain settings. Switching resistance and leakage current errors can be reduced by using relays.

Determining SPGA Resistor Network Values

The individual resistors in the gain network can be calculated sequentially using the equations given below. The equation determines the resistance shown in Figure 41. Therefore, the feedback resistor and the gain setting resistor are interacting; the formula must be that the current term depends on the series of the previous term. formula:

Can be used to calculate the feedback resistor required for any set of gains. This formula results in a network with a total resistance of 40kΩ. The dummy variable (j) is used as a counter to keep the total running amount of the preceding feedback resistor. To illustrate how this formula is applied, an example similar to the calculation used for the resistor network in Figure 38 will be studied below.

1), unity gain is handled as a separate case. It is implemented with a separate 20 kΩ feedback resistor, as shown in Figure 41 and then ignored in further calculations.

2) Before doing any calculations, it is recommended to draw a resistor network similar to the network in Figure 41. The network will have (2 x m) + 1 resistors, where m = number of gains. So for Figure 38 m=3 (4, 16, 64), the resistor string will have seven resistors (plus two 20 kΩ "side" resistors for unity gain).

4), finally determine the center resistance (rg of the highest gain setting). Its value is the residual resistance of the 40 kΩ string and can be calculated by the following formula:

5) If different resistor values are required, all resistors in the network can be scaled by some convenient factor. However, increasing the impedance will increase the RTO error, and reducing the total network resistance below 20kΩ will cause the amplifier to become unstable. The RPGA section of the datasheet provides more information on this phenomenon. The scale factor does not affect the unity-gain feedback resistors The resistor network in Figure 38 has a scale factor of 650/625 = 1.04, if this factor is used for rf1, rf2, rf3, and rg, the resistor values will match exactly.

6) Rounding errors can accumulate, so it is recommended to carry as many significant digits as possible before calculating all values.