Description The Vnd670SP is a monolithic device fabricated with STMicroelectronics ViPower technology M0-3 for driving a full-bridge motor configuration. The device integrates two 30mΩ power mosfets in a high-side structure and provides two external MOSFETs that act as low-side switches. The power mosfet provides the gate drive. INA and INB allow selection of clockwise or counter-clockwise drive or braking; DIAGA/ENA, DIAGB/ENB allow to disable a half-bridge and feedback diagnostics. Built-in thermal shutdown, combined with a current limiter, protects the chip from over temperature and short circuit conditions. Externally connected low-side power mosfet for short-to-battery protection.

Current and Voltage Conventions

Typical application circuit for DC to 10khz pwm operation

Typical Application Circuit for 20kHz PWM Operation

Waveforms and Truth Tables (continued)
Under fault conditions, the device treats the DIAGX/ENX pins as output pins. The fault conditions are: one or both sides are too high temperature; output is shorted to battery (saturation detection on externally connected power MOSFETs) Possible causes of failure may be Yes: OUTA is shorted to ground--->A high voltage side overheat detection. OUTA is shorted to VCC--->External power mosfet saturation detection (driven by GATEA). When a fault condition is detected, the user can know which power element is faulty by monitoring the INA, INB, DIAGA/ENA and DIAGB/ENB pins. In any case, when a fault is detected, the faulty half-bridge is locked. To open the corresponding output (gatex or outx) again, the input signal must rise from low to high.

Test Mode - The PWM pin allows testing of the load connection between the two half bridges. In test mode (Vpwm=-2V), the external power supply Mos gate driver is disabled INA or INB input allows to turn on high side A or B respectively to connect side of load at VCC voltage. The continuity of the load connection can be verified by checking the voltage on the other side of the load. With the load disconnected, the DIADX/ENX pin corresponding to the fault output is pulled down.