feature

Guaranteed 16-bit monotonicity; monolithic bimos ii structure; 60.01% typical nonlinearity; 8-bit and 16-bit bus compatibility; 3ms set to 16-bit; low drift; low power; low noise.

application

Robotics; closed-loop positioning; high-resolution analog-to-digital converters; microprocessor-based process control; MIL-STD- 883 compliant versions available.

Product Description

The AD569 is a monolithic 16 digital-to-analog converter (DAC) fabricated using the BIMOS II process for analog devices. Bimos II allows the fabrication of low-power CMOS logic functions and high-precision bipolar linear circuits on the same chip. The AD569 chip includes two resistor strings, selector switching decoding logic, buffer amplifiers and double buffered input latches.

The voltage-segmented architecture of the AD569 ensures 16-bit monotonicity over time and temperature. Integral nonlinearity is maintained at ±0.01%, while differential nonlinearity is ±0.0004%. The on-chip high-speed buffer amplifier provides voltage output settling times of 3 microseconds with full-scale steps within ±0.001%. The reference input voltage that determines the output range can be unipolar or bipolar. The nominal reference range is ±5 V, with separate reference force and sensing connections for high precision applications. In multiplying applications, the AD569 can work with an AC reference. Data is available from 8- and 16-bit buses Double-buffered structure simplifies 8-bit bus interface and allows multiple DACs to be asynchronously loaded and updated simultaneously Four TTL/LSTTL/5 VCMOS compatible signal control latches: cs, lbe, hbe, and The LDACAD569 is available in five grades: J and K versions are specified from 0°C to +70°C and are packaged in 28-pin plastic dip and 28-pin PLCC packages; AD and BD versions are specified from -25°C to +85°C °C, packaged in 28-pin ceramic impregnation. The SD version, also with 28-pin ceramic impregnation, is specified for temperatures from -55°C to + 125 °C.

Product Highlights

1. The voltage segment structure of AD569 ensures 16-bit monotonicity.

2. The output range is proportional to the external reference or AC signal. The gain error and gain drift of the AD569 are negligible.

3. The general-purpose data input structure of AD569 allows loading from 8-bit and 16-bit buses.

4. The on-chip output buffer amplifier can drive capacitive loads up to 1000 pF into 1 kΩ loads.

5. The Kelvin connection to the reference input maintains the gain and offset accuracy of the transfer function, wiring resistance and ground current.

6. AD569 has a MIL-STD compliant version -883. See Analog Devices Military Data Sheet or current AD569/883B data sheet specifications for details.

Function description

The AD569 consists of two resistor strings, each of which is divided into 256 equal segments (see Figure 3). The 8 msbs of the numeric input word select one of the 256 segments of the first string. The top and bottom taps of the selected segment are connected to the inputs of two buffer amplifiers, a1 and a2. These amplifiers exhibit extremely high common-mode rejection ratios and low bias currents, thereby accurately maintaining voltages at the top and bottom of the segment. The buffered voltage at the segment endpoints is applied across the second resistor string, and the 8lsb of the digital input word selects one of the 256 taps that the output amplifier A3 buffers and outputs.

Buffer amplifiers a1 and a2 skip the first string to keep segment boundaries monotonic. For example, when increasing the digital code from 00ffh to 0100h (first segment boundary), a1 remains connected to the same tap on the first resistor, while a2 skips it and connects to the tap that becomes the top of the next segment. This design guarantees monotonicity even if the amplifier is biased. In practice, the offset of the amplifier only contributes to the integral linearity error.

It is generally considered good engineering practice to avoid inserting integrated circuits into powered sockets. This guideline is especially important for the AD569. Empty, powered sockets configure external buffer amplifiers in open-loop mode, forcing their outputs on either the positive or negative rails. This condition can cause large current surges between the reference force and the sense terminals. This current surge can permanently damage the AD569.

definition

Linearity Error: The analog device defines linearity error as the maximum deviation of the actual adjusted DAC output from the ideal output (straight line from 0 to FS-1LSB) for any combination of bits. The linearity of the AD569 is primarily limited by the resistance uniformity in the first divider (upper byte of the 16-bit input). The curves in Figure 4 show the typical linearity error of the AD569 over the entire output range to within ±0.01% of full scale. At 25°C, the maximum linearity error for the AD569JN, AD, and SD grades is specified as ±0.04%, ±0.024% for the KN and BD versions.

Monotonicity: A dac is monotonic if the output increases or stays the same as the digital input increases. All versions of the AD569 are monotonic over their entire operating temperature range.

Differential Nonlinearity: DNL is the change in the analog output, normalized to full scale, with respect to a 1lsb change in the digital input code. Monotonicity requires the differential linearity error to be less than 1lsb over the temperature range of interest. For example, for a ±5 V output range, a 1 LSB change in the digital input code should result in a 152 μV change in the analog output (1 LSB = 10 V/65536) However, if the change is actually 38 μv, the differential linearity error will be –114 μv or –3/4 lsb. By skipping the tap of the buffer amplifier on the first divider, the typical AD569 maintains DNL within ±38 microvolts (±1/4 LSB) (see Figure 5). Within the second divider, DNL is also typically kept below ±38µV, as shown in Figure 6. Since the second voltage divider is independent of the absolute voltage, the dnl is the same in the rest of the 256 segment.

Offset Error: The difference between the actual analog output and the ideal output (–vref), where the input is all zero, is called the offset error. For the AD569, the unipolar offset is specified as 0 V applied to –VREF, and the bipolar offset is specified as –5 V applied to –VREF. The offset is adjusted by adjusting the voltage applied to the –VREF terminal.

Bipolar Zero Error: When the input load is 8000H, the deviation of the analog output from the ideal half-scale output of 0.0000 V is called the bipolar zero error. For the AD569, it is specified that ±5 V is applied to the reference terminal.

Multiply Feedthrough Error: This is the error that the input register is loaded with all zeros due to capacitive feedthrough from the reference to the output.

Full-Scale Error: The voltage divider architecture of the AD569 - this configuration produces a fixed full-scale error independent of the reference voltage. This error is eliminated by adjusting the voltage applied to the +VREF terminal.

Digital-to-Analog Fault Pulse: Charge - When a new input is latched into the DAC register, injected into the analog output produces a digital-to-analog fault pulse.

Faults can be due to time skew between input bits or charge injection from internal switches. The fault pulse of the AD569 is mainly caused by charge injection, and it is measured through a reference connection to ground. It is designated as a failure region in nV secs.

Total Error: The worst-case total error is the sum of the fixed full-scale and offset error and the linearity error.

Supply and Reference Voltage Ranges

The AD569 is specified to operate with a ±10% supply tolerance with a ±12 volt supply, with a maximum reference voltage range of ±5 volts. Reference voltages up to ±6 volts can be used, but if the supply approaches its lower limit of ±10.8 volts (12 volts - 10%), linearity will degrade.

If a ±12V supply is not available in the system, several alternatives can be used to obtain the desired supply voltage. For example, in a system with a ±15V supply, a zener diode can be used to step down one of the supply voltages to 9V, while The remaining one supply voltage remains at 15V. Figure 7a illustrates this scheme. A 1N753A or equivalent diode is an appropriate choice for the task. Asymmetrical supplies can be used because the output of the AD569 is only referenced to –VREF and therefore floats relative to logic ground (GND, pin 18) Assuming a worst-case ±1.5 volt tolerance on both supplies (10% of 15 volts), The maximum reference voltage range will be +6 and 2 volts, +VS = +15 V and VS = 9 V, +2 to 8 volts for +VS = 9 V and -VS = 15 V. Alternatively, two 3 V Zener diodes or voltage regulators can be used to step down each ±15 V supply to ±12 V separately. In Figure 7b, a 1n746a diode is a good choice for this task.

A third method can be used if both ±15V and ±5V supplies are available. Figure 7c shows this method. The combination of +vs=+15v and –vs=-5v can support a reference voltage range of 0 to 6v, while a supply of +vs=+5v and –vs=-15v can support a reference voltage range of 0 to –8v. Again, assume a power supply tolerance of 10%.

NOTE: Operation with +vs=+5v changes the operating conditions of the input latches, resulting in a minimum write pulse width of -tends to 1 microsecond or higher. Control signals CS, HBE, LBE and therefore LDAC should be tied low to make the latch transparent.

There are no timing issues in operation at +VS=9 V and -VS=15 V, however, a 10% tolerance on these supplies yields -Vs=-16.5 V and +VS=+7.5 V (assuming +VS source from +15 V supply) worst-case conditions. Under these conditions, write pulse widths can be extended to 200 nanoseconds, and data setup and hold times are reduced. However, a ±0.75 V tolerance (±5%) has minimal impact on digital timing, and write pulse widths are kept under 100 ns.

Finally, Figure 7d illustrates the use of the AD588 and AD569 combination in a system with ±15 volt supplies. As shown, the AD588 is connected to provide ±5 V to the reference input of the AD569. It does double duty by using a level-shift zener and transistor to simultaneously regulate the supply voltage of the AD569. This scheme utilizes the output of the AD588 to source current and The ability to sink currents can also achieve two other benefits using this approach. First, the AD569 is no longer directly connected to the system power supplies, thus eliminating output sensitivity to these supply changes. The second benefit is that if the zener diode fails (short circuit is the most likely failure), the supply voltage will drop. This is not the case where diodes are used as series regulators. In this case, the fault leaves the supply voltage on the AD569 terminals unregulated.

Analog circuit connection

The AD569 is used in applications where high resolution and stability are critical. The AD569 is designed as a multiplying D/a converter and can be used with a fixed DC reference or an AC reference VREF can be any voltage or combination of voltages at +VFORCE and –VFORCE, which remains at the reference voltage discussed in the Power Supply Range section Since ad569 is a multiplication d/a converter within the set range, its output voltage vout is proportional to the product of the digital input word and the reference voltage. The transfer function is vout=d·vref, where d is the fractional binary value applied to the digital word of the converter using offset binary encoding. Therefore, the output range will be from –vref for an all-zero digital input code (0000h) to +vref for an all-ones input code (ffffh).

For applications where absolute accuracy is not critical, the simple reference connection in Figure 8 can be used. Using only the reference force input, this configuration maintains linearity and 16-bit monotonicity, but introduces small, fixed offset and gain errors. These errors are caused by the voltage drop across resistors ra and rb shown in Figure 9. Gain and offset errors range from 80mV to 100mV at a 10V reference. Resistors RA and RB are included in the first resistor string to avoid loss of linearity due to non-uniform current density at the end of the string. Likewise, Linearity is also reduced if the reference voltage is connected to the reference sense terminal. The resistance between the attention and sense terminals cannot be measured with an ohmmeter; the layout of the thin film resistor string adds approximately 4 K of resistance at the sense tap (RS ).

For precision reference and applications where high precision is critical, buffer amplifiers are used for +vref and –vref shown in Figure 10 to force the voltage between resistors r1 to r256. This ensures that any errors caused by current flow through the package pins, bond wires, aluminum interconnects, and RA and RB resistors are minimized. Suitable amplifiers are the AD517, ADOP07, ADOP27 or the dual amplifier AD712. However, when the bias current of the buffer amplifier flows through rs (4kΩ), an error occurs. If the bias current produces such an error, a resistor can be inserted at the non-vertical termination (rbc) of the buffer amplifier.

Figures 11, 12 and 13 show reference configurations for various output ranges. As shown in Figure 11, the pin-programmable AD588 can be connected to provide a tracking ±5V output with 1-3ppm/°C temperature stability. The buffer amplifier consists of a direct connection to the AD569. Optional gain and balance adjustment trimmers allow for bipolar offset and full-scale error of zero. In Figure 12, the low-cost AD586 provides the +5V reference. The dual op-amp AD712 buffers the reference input terminals, maintaining the absolute accuracy of the AD569. Optional noise reduction capacitors and gain adjustment trimmers can further eliminate errors. The low-cost AD584 is available in 2.5 V, 5 V, 7.5 V, and 10 V options and can be connected to the ±5 V tracking outputs, as shown in Figure 13. Again, the ad712 is used to buffer the reference input terminals.

Multiply performance

Figure 14 shows the gain and phase characteristics of the AD569 when operating in multiplier mode. The full power bandwidth is shown in Figure 14a, and the corresponding phase shift is shown in Figure 14b. Performance is plotted for both full scale input ffffh and input 8080h. The input represents the worst case as it places the buffer tap at the midpoint of the two splitters. Figure 15 illustrates the AD569’s ability to resolve 16 bits (where 1 LSB is 96 dB below full scale) at 200 Hz with an ac reference of 1 V rms while keeping the noise floor below -130 dB.

Multiplying feedthrough is due to capacitive coupling between the reference input and output as shown in Figure 16:

In the worst case (hex input code 0000), the feedthrough remains below -100 dB up to the AC reference frequency up to 10 kHz.

Bypass and Grounding Rules

It is generally considered good engineering practice to use bypass capacitors on the equipment supply voltage pins and insert small value resistors in the supply lines to provide decoupling between circuits in the system. For the AD569, it is recommended to use a bypass capacitor of at least 4.7µF and a series resistor of 10Ω. The supply voltage pin should be disconnected from pin 18.

noise

In high-resolution systems, noise tends to be the limiting factor. The LSB size of a 16-bit DAC with a 10-volt span is 152 microvolts (–96 dB). Therefore, over the frequency range of interest, the noise floor must be kept below this level. The noise spectral density of the AD569 is shown in Figures 17 and 18. The low frequency noise spectrum in Figure 17 represents the 1/f corner frequency at 1.2kHz, and the broadband noise in Figure 18 is as follows:

digital circuit connection

The truth table for the AD569 appears in Table I. High Byte en - When Chip Select (CS) is active (low), the ABLE (HBE) and Low Byte Enable (LBE) inputs load the upper and lower bytes of the 16-bit input. A similar strobe to load dac (ldac) loads the 16-bit input into the dac register and completes the dac update. The dac registers can be loaded with a separate write cycle, or they can be loaded synchronously with the 8-bit registers in the first column. Simultaneous updating of several AD569s can be accomplished by controlling their ldac inputs with a control signal.

All four control input latches are level-triggered and active-low. When the DAC registers are loaded directly from the bus, when CS, LDAC, LBE, and HBE are low, the digital inputs will be reflected in the output. If not ideal, Please turn up LDAC (or HBE or LBE) before changing the data. Alternatively, use a second write cycle to transfer data to the dac register or delay the write strobe until the appropriate data is valid. Make sure to observe proper data setup and hold times (see Timing Characteristics).

Whenever possible, the write strobe signal should be applied to the HBE and LBE where the AD569 decodes addresses. CS, HBE, and LBE have a minimum pulse width of 60 ns, allowing the AD569 to interface with the fastest microprocessors. In practice, data can be locked with narrower pulses, but the data setup and hold times must be extended.

16-bit microprocessor interface

Since a 16-bit microprocessor provides the full 16-bit input to the AD569 in one write cycle, the DAC register is usually not required. If it is, it should be made transparent by grounding the LDAC. The decoded address of the DAC should be applied to CS and applied to HBE and LBE using write strobes, as shown in Figure 19 for the 68000 interface.

8-bit microprocessor interface

Since an 8-bit microprocessor requires two write cycles to provide the 16-bit input to the AD569, the DAC register must be used. It is usually loaded when the second byte enters the first latch sequence. This synchronous loading method, shown in Figure 20, - requires the LDAC to be bound to either the LBE or the HBE depending on the byte loading order. In both cases, the propagation delay through the first rank causes longer timing requirements, as shown in Figure 2. If the DAC register (LDAC) is individually controlled using the third write cycle, the minimum write pulse to turn on the ldac is 70ns, as shown in Figure 1.

There are two basic ways to connect the address and control buses of an 8-bit microprocessor. In both cases, at least one address line is required to distinguish each byte of the up-first level from the lower byte (HBE and LBE). The easiest way is to apply these two addresses directly to the HBE and LBE using CS for data scanning as shown in Figure 20a. However, the minimum pulse width on CS is 70ns and the minimum data setup time is 60ns. If shorter pulse width operation is required, the base address should be applied to CS with a strobe signal strobing the address lines to provide the HBE and LBE inputs (see Figure 20b). However, since the write pulse sees a propagation delay, Therefore the data must still remain valid at least 20 ns after the rising edge of the delayed write pulse.

output regulation

The output buffer amplifier of the AD569 typically settles to within ±0.001% fs of its final value within 3 microseconds for 10 volts. Figure 21 shows the settlement of negative and positive full scale steps with no load. The output buffer is capable of sourcing or sinking 5 mA and can also drive 1 kΩ and 1000 pF loads without loss of stability. Typical settling to 0.001% in these worst-case scenarios is 4µs and is guaranteed to be a maximum of 6μs. The graph of Figure 21 was generated using a sedimentation test procedure developed specifically for the AD569.

Subrange 16-bit ADC

The subranging ADC shown in Figure 22 completes the conversion in less than 20 microseconds, including the sampling time of the sample-and-hold amplifier. The sample-and-hold amplifier is allocated 5µs to settle to 16 bits.

Before the first flash, the analog input signal is quantized to an 8-bit level in 1.4 microseconds with a gain of +1 through the AD630 lower AD7820, the 8-bit result is routed to the AD569 through a digital latch, which is digitally latched The device holds the 8-bit word and output logic for the AD569.

The reference polarity of the AD569 is reversed so that the full-scale output is -5 V and the zero-scale is 0 V, thereby subtracting an 8-bit approximation from the original sampled signal. The remainder of the analog subtraction is then quantized by a second 8bit flash conversion to recover the 8 lsbs. Even if only the 8 high bits of the AD569 are used, the accuracy of the AD569 defines the overall accuracy of the A/D converter and any errors are reflected directly in the output.

Before the second flash, the residual signal must be amplified by a factor of 256. The OP37 provides a gain of 25.6 and the AD630 provides another gain of 10. In this case, the ad630 acts as a gain element as well as a channel control switch. The second flash conversion produces a 9-bit word. This provides an extra bit of overlap for digital correction of any errors that occur in the first flash. Correction bits are digitally added to the first flash before the entire 16-bit output is selected into the output register.