Features

23 8226 ; 8-channel complete analog front end: –LNA, VCA, PGA, LPF and ADC; ultra-low, full channel noise: –0.85nV/√Hz (TGC) –1.1nV/√Hz (CW); low power: – 122mW/channel (40MSPS) – 74mW/channel (CW mode); Low Noise Preamplifier (LNA): -0.75nV/√Hz – 20dB Fixed Gain – 250mV Linear Input Range; Variable Gain Amplifier: – Gain Control Range: 46dB; PGA Gain Settings: 20dB, 25dB, 27dB, 30dB; Low Pass Filter: – Selectable Bandwidth: 10MHz, 15MHz – 2nd Order; Gain Error: ±0.5dB; Channel Matching: ±0.25dB; Distortion , HD2: 65dBfs at 5MHz; clamp control; fast overload recovery: two clock cycles; 12-bit ADC: –10MSPS to 50MSPS – 69.5dB SNR at 10MHz – Serial LVDS interface; integrated CW switch Matrix; 15mm x 9mm, 135-BGA Package: – Pb-Free (RoHS Compliant) and Green.

application

Medical Imaging, Ultrasound - Portable Systems.

illustrate

The AFE5805 is a complete analog front end device designed for ultrasound systems requiring low power and small size.

The AFE5805 consists of eight channels including a Low Noise Amplifier (LNA), Voltage Controlled Attenuator (VCA), Programmable Gain Amplifier (PGA), Low Pass Filter (LPF) and a Low Voltage Differential Signaling (LVDS) data output 12-bit analog-to-digital converter (ADC).

The LNA gain is set to a gain of 20dB, which has excellent noise and signal handling capabilities, including fast overload recovery. The VCA gain can be varied within a range of 46dB, and all channels of the AFE5805 share a 0V to 1.2V control voltage.

The pga programmable gain is 20db, 25db, 27db and 30db. The internal low pass filter can also be programmed to 10MHz or 15MHz.

The ADC's LVDS output reduces the number of interface wires to ASICs or FPGAs, enabling the high system integration density required for portable systems. The ADC can operate with an internal or external reference. ADCs also feature a signal-to-noise ratio (SNR) enhancement mode for high gain.

The AFE5805 is available in a 15mm x 9mm 135-ball BGA package, lead-free (RoHS compliant) and green. Specified for operation at temperatures from 0°C to +70°C.

Please note that important notices regarding the availability, standard warranties and use in critical applications and disclaimers of Texas Instruments semiconductor products appear at the end of this data sheet.

Typical features

AVDD U 5V=5.0V, AVDD1=AVDD2=DVDD=3.3V, LVDD=1.8V, single-ended input LNA, AC coupled 0.1mF, VCNTL=1.0V, fIN=5MHz, clamp disabled, LPF=15MHz, clock= 40MSPS, 50% duty cycle, internal reference mode, ISET=56kΩ, LVDS buffer setting=3.5mA, ambient temperature TA=+25°C unless otherwise specified.

serial interface

The AFE5805 has a set of internal registers that can be accessed through a serial interface consisting of pins CS (chip select, active low), SCLK (serial interface clock), and SData (serial interface data). When cs is low, the following actions occur:

(1), allowing the serial shift of bits into the device;

(2), SData (serial data) is locked on each rising edge of SCLK;

(3) SData is loaded into the register every 24 SCLK rising edges.

If the word length exceeds a multiple of 24 bits, the extra bits are ignored. Data can be loaded in multiples of 24-bit words within an active CS pulse. The first 8 bits constitute the register address, and the remaining 16 bits constitute the register data. The interface can operate at SCLK frequencies from 20MHz to very low speed (several hertz), as well as at SCLK duty cycles other than 50%.

Register initialization

After power-up, the internal registers must be initialized to their default values. Initialization can be done in one of two ways:

1. Through hardware reset, apply a low pulse on the ADS reset pin;

2. Reset via software; using the serial interface, set the first bit high. Setting this bit initializes the internal registers to their default values and then self-resets the low bits. In this case, the ADS_ reset pin remains high (inactive).

It is recommended to program the following registers after the initialization phase to minimize the effects of power supply ripple and clock jitter.

input clock

By default, the AFE5805 is configured to operate with a single-ended input clock; CLKP is driven by the CMOS clock and CLkm is tied to "0". However, the device can be made to work with differential input clocks on clkp and clkm by programming diff_clk to '1'. Using a low-jitter differential clock generally improves signal-to-noise performance.

If the duty cycle of the input clock is outside the 45% to 55% range, it is recommended to enable the internal duty cycle correction circuit by setting the en_DCC bit to '1'.

xref

The AFE5805 can be made to operate in external reference mode by pulling the internal/external pin to '0'. In this mode, the drive voltage of the reft and refb pins should be 2.5v and 0.5v respectively, and there must be enough drive strength to drive the switched capacitor load of each ADC to the reference voltage. The advantage of using external reference mode is that multiple afe5805 units can be made to work with the same external reference, improving parameters such as gain matching across devices. However, in applications without a high drive, differential external reference, the afe5805 can still be driven by a single external reference voltage on the cm pin. When ext_ref_vcm is set to "1" (int/ext pin is set to "0"), the cm pin is configured as an input pin, and the voltages on reft and refb are generated as shown in Equation 1 and Equation 2.

Bit Clock Programmability

The output interface of the AFE5805 is usually a DDR interface, and the LCLK rising and falling edges transition in the middle of the alternate data window. Figure 43 shows this default stage.

The phase of lclk can be programmed relative to the output frame clock and data using bits-phase-ddr<1:0>. Figure 44 shows the lclk phase mode.

In addition to programming the phase of LCLK in DDR mode, the device can also be made to operate in SDR mode by setting the EN-SDR bit to '1'. In this mode, the bit clock (lclk) is clocked at 12 times the input clock speed output, or twice the speed output in ddr mode. Depending on the state of fall_sdr, lclk can be output in one of two ways as shown in Figure 45. As shown in Figure 45, only the rising (or falling) edge of LCLK is used to capture output data in SDR mode.

Since the lclk frequency becomes very high, the sdr mode does not work well beyond 40msps.

Data output format mode

By default, the ADC output is in straight offset binary mode. Programming the BTC_MODE bit to '1' inverts the MSB and the output becomes binary 2's complement mode.

By default the first bit of the frame (after the rising edge of FCLKP) is the LSB of the ADC output programming msb_first mode will reverse the bit order in the word and msb will be output as the first bit after the rising edge of fclkp.

The power-up time shown is based on a 1mF bypass capacitor on the reference pin, twake is the time it takes for the device to fully wake up from shutdown mode. The AFE5805 has two power-down modes: full power-down mode and partial power-down mode.

(1) The time in the complete power-off mode is ≤50ms, and the Twake in the partial power-off mode is ≤2ms (provided that the clock is not turned off during the power-off).

(2) The ADS_PD pin can be configured as a partial power-down mode through register settings.

theory of operation

The AFE5805 is an 8-channel, fully integrated analog front-end device that controls the LNA, attenuator, PGA, LPF and ADC, and implements a number of proprietary circuit design techniques specifically addressing the performance requirements of medical ultrasound systems. It provides unparalleled low noise and low power performance at a high level of integration. For the tgc signal path, each channel consists of a 20db fixed gain low noise amplifier (lna), linear in-db voltage controlled attenuator (vca) and programmable Gain amplifier (pga) and clamp and low pass filter stages. Digitally controlled via the logic interface, the PGA gain can be set to four different settings: 20dB, 25dB, 27dB and 30dB. Therefore, at its highest setting, the total available gain of the AFE5805 is 50dB. To facilitate the logarithmic time gain compensation required by ultrasound systems, the vca is designed to provide an attenuation range of 46db. Here, all channels are controlled by external voltages in the 0V to 1.2V range, while the LNA is designed to be driven by a single-ended source, and the internal signal path is designed to be fully differential to maximize dynamic range while optimizing low , Even-order harmonic distortion.

Processing of the CW Doppler signal is achieved by routing the differential INA outputs to the v/i amplifier stage, and the signal currents generated by each channel are connected to an 8×10 switch matrix that is connected via the serial interface and the corresponding register to control. The CW output is typically routed to a passive delay line that allows coherent summation (beamforming) of the active channel and additional off-chip signal processing, as shown in Figure 46.

Applications that do not use the CW path can simply operate the AFE5805 in TGC mode. In this mode, the CW block (V/I amplifier and switch matrix) remains powered down and the CW output can be left unconnected.

Low Noise Amplifier (LNA)

As with many high-gain systems, the front-end amplifier is critical to achieving a certain level of overall performance. The low-noise amplifier of the AFE5805 uses a new proprietary architecture that operates at very low noise levels compared to CMOS architectures with similar noise performance. Works at quiescent current with excellent low noise performance.

The LNA performs single-ended input to differential output voltage conversion and is configured for a fixed gain of 20dB (10V/V). Ultra-low input-referred noise of only 0.7nV/√Hz, and a linear input range of 250MVPP, the result is a dynamic range that supports demanding PW and CW ultrasound imaging modes. Larger input LNAs can accept the signal, but the distortion increases as the input signal level decreases and the performance degradation increases. The LNA input is internally biased to approximately +2.4V; the signal source should be coupled to the LNA input by an appropriately sized capacitor. Internally, the LNA drives the VCA directly, avoiding the typical drawbacks of AC-coupled architectures, such as slow overload recovery.

Voltage Controlled Attenuator (VCA)

The vca is designed to have a linear in-db decay characteristic; that is, the average gain loss (db) is constant for each equal increment of the control voltage (vcntl). Figure 47 shows a simplified schematic diagram of the VCA stage.

The attenuator is essentially a variable voltage divider consisting of a series input resistor (RS) and eight identical parallel FETs, placed in parallel and controlled by sequentially activated limiting amplifiers (A1 to A8). Each limiting amplifier can be understood as a dedicated voltage comparator with soft transfer characteristics and well-controlled output limiting voltage. The reference voltages v1 to v8 are equally spaced in the control voltage range of 0v to 1.2v. As the control voltage increases across the input range of each limiting amplifier, the amplifier output rises from 0V (FET fully on) to VCM – VT (FET almost off), where VCM is the common supply voltage and vt is the threshold FET voltage The state and control voltages continue to rise as each FET approaches off, and the next limiting amplifier/FET combination takes over the next part of the piecewise linear decay feature.

Therefore, a low control voltage turns most of the FET on, producing the greatest signal attenuation. Similarly, a high control voltage turns off the FET, resulting in minimal signal degradation. Therefore, the role of each FET is to reduce the parallel resistance of the voltage divider formed by rs and the parallel FET network.

Programmable Post Gain Amplifier (PGA)

Following the VCA is a programmable post-gain amplifier (PGA) Figure 48 shows a schematic diagram of a simplified PGA including the clamping stage. The gain of this pga can be configured to 4 different gain settings: 20db, 25db, 27db and 30db, programmable through the serial port; see Table 10. The PGA structure includes a differential, programmable-gain voltage-to-current converter stage followed by transimpedance amplifiers to buffer each side of the differential output. Low input noise is also a requirement for PGA design, since a large amount of signal attenuation can be applied at the previous VCA stage. At minimum VCA attenuation (for small input signals), LNA noise dominates; at maximum VCA attenuation (for large input signals), Attenuator and pga noise dominate.

Programmable Clamping To further optimize the overload recovery behavior of the entire TGC channel, the AFE5805 integrates a programmable clamping stage, as shown in Figure 49, to prevent the filter circuit from being driven into an overload condition, resulting in extended recovery time. Programmable via the serial interface, the clamp level can be set to clamp the signal level to approximately 1.7VPP differential, or disabled. Disabling the clamp function increases the current consumption of the full device's 3.3V analog supply (AVDD2) by about 3mA. Note that the third harmonic distortion increases when clamping is enabled.

low pass filter

The AFE5805 channels in the form of a programmable low pass filter (lpf). The LPF is designed to be a differential, active, second-order filter that approximates Bessel characteristics, typically attenuating 12dB per octave. Figure 49 shows a differential active low-pass filter. Programmable via the serial interface, the -3dB frequency corner can be set to 10MHz or 15MHz. This sets the filter bandwidth for all channels simultaneously.

Analog to digital conversion

The AFE5805 analog-to-digital converter uses a pipelined converter architecture to form an internal practice by combining multiple bits and units. Each stage feeds its data to digital error correction logic, ensuring excellent differential linearity with no missing codes for differential linearity and no missing codes for 12-bit levels.

The 12 bits given by each channel are serialized and sent on a pair of pins in lvds format, all 8 channels of the afe5805 run from a common input clock (clkp/m). The sample clock for each of the eight channels is generated from the input clock using a carefully matched clock buffer tree. The 12x clock required by the serializer is generated internally from the clkp/m using a phase locked loop (PLL). A 6x and a 1x clock are also output in LVDS format, along with the data, for easy data capture. The AFE5805 operates on internally generated reference voltages that are trimmed to improve gain matching between devices and provide the option to operate the devices without the need for external driving and routing of reference lines. The nominal values of REFT and REFB are 2.5V and 0.5V, respectively. References are internally shrunk by a factor of 2. VCM (the common mode voltage of REFT and REFB) is also available externally via a pin, nominally 1.5V.

The ADC output goes to a serializer that uses a 12x clock generated by a phase locked loop. The 12 data bits per channel are serialized and sent lsb first. In addition to serializing data, the serializer also generates 1X clocks and 6X clocks. These clocks are generated in the same way as serialized data, so these clocks are perfectly synchronized with the data. The serializer's data and clock outputs are externally buffered using lvds buffers. Using lvds buffers to transfer data externally has several advantages, such as reducing the number of output pins (saving wiring space on the board), reducing power consumption, and reducing the effect of digital noise coupling into the afe5805's internal analog circuits.

application information

Although the LNA is designed as a fully differential amplifier, it is optimized to perform single-ended input-to-differential output conversion. Figure 50 shows a simplified schematic of one LNA channel. A bias voltage (Vb) of +2.4V is applied internally to the LNA input through an 8KΩ resistor. In addition, the dedicated signal input (In-pin) includes a pair of back-to-back diodes that provide coarse input clamping when the input signal rises to very large levels (over 0.7V PP). This configuration prevents the LNA from being driven into a severe overload state that might otherwise result in extended overload recovery time. The integrated diodes are designed to handle DC currents up to about 5Ma. Depending on the application requirements, the system overload characteristics can be improved by adding an external Schottky diode at the LNA input, as shown in Figure 50.

As shown in Figure 50, the complementary LNA input (V bl pin) is internally decoupled by a small capacitor. Additionally, for each input channel, there is a separate VBL pin for external bypassing. This bypass should be done with a small, 0.1MF (typical) ceramic capacitor placed very close to each VBL pin. Care should be taken to provide a low noise analog ground for this bypass capacitor. A noisy ground potential can cause noise to be picked up and injected into the signal path, resulting in higher noise levels.

The LNA closed-loop architecture internally compensates for maximum stability when external compensation components (inductors or capacitors) are not required, while the total input capacitance is kept to a minimum of only 16pF. This structure minimizes any loading of the signal that might otherwise result in a frequency-dependent voltage divider. And the closed-loop design yields very low offset and offset drift; this consideration is important because the LNA directly drives the subsequent voltage-controlled attenuator.

The LNA of AFE5805 utilizes the advantages of bipolar process technology to achieve extremely low noise voltage of 0.7nV/√Hz and low current noise of 3pa/√Hz. Using these input-referred noise specifications, the AFE5805 achieves a very low noise figure over a wide range of source resistances and frequencies (see Figure 16 for typical characteristics of noise figure versus frequency). The optimum noise power matches the source impedance of approximately 200 ohms. More detailed noise performance of the AFE5805 input is shown in the feature map.

Overload recovery

The AFE5805 is specifically designed for ultrasonic applications where the front-end equipment needs to recover quickly from overload conditions. This overload can be the result of transmit pulse feeds or strong echoes, which can overload the LNA, PGA, and ADC. As mentioned earlier, the LNA input is internally protected by a pair of back-to-back diodes to prevent severe overloading of the LNA. Figure 51 illustrates the ultrasonic receive channel front end, including typical external overload protection components. Here, four high voltage switching diodes are configured in a bridge configuration and form a transmit/receive (T/R) switch. During transmission, high voltage pulses from the pulse generator are applied to the sensor element, and the T/R switch isolates the sensitive LNA input from the high voltage signal. However, it is very common for fast transients up to a few volts to leak through the T/R switch and potentially overload the receiver. So put an extra pair of clamp diodes between the t/r switch and the lna input. To limit overvoltages to small levels, Schottky diodes (such as the BAS40 series from Infineon®) are often used. For example, clamping to ±0.3V can significantly degrade overall overload recovery performance. The T/R switching characteristics are strongly dependent on the bias current of the diode, which can be set by adjusting the 3kΩ resistor value; for example, setting a higher current level may result in improved switching characteristics and reduced noise contribution A typical front-end protection circuit can sequentially add 2nV/√Hz of noise to the signal path. The increase in noise also depends on the value of the termination resistor (RT).

As shown in Figure 51, the front-end circuit should be capacitively coupled to the lna signal input (in). This coupling ensures that the LNA input bias voltage + maintains 2.4V and is biased against any other LNA pre-bias. In the AFE5805, either the LNA or the PGA can be overloaded. The t/r switch feedthrough can cause the LNA to be overloaded, and at higher signal gains, the PGA can be driven into overload by near-field strong echoes. In any case, the AFE5805 is optimized for very short recovery times, as shown in Figure 51.

VCA gain controls the attenuator (VCA) for each of the eight channels

The AFE5805 is controlled by a single-ended control signal input to the VCNTL pin. The control voltage ranges from 0V to 1.2V, referenced to ground. The control voltage changes the linear attenuation characteristics of VCABASE, the maximum attenuation (minimum gain) is VCNTL=0V, and the minimum attenuation (maximum gain) is VCNTL=. 1.2V. Table 17 shows each of the four PGA gain settings. The total gain range is typically 46dB, held constant, with the selected PGA; the maximum gain column reflects the absolute gain of the full signal path including 20dB of fixed LNA gain and programmable PGA gain.

As mentioned earlier, the vca architecture uses eight attenuator segments equally spaced to obtain the gain control slope in dB in an approximately linear fashion. This approximation results in a monotonic slope with gain ripple typically less than ±0.5dB.

The AFE5805 gain control input has a -3dB bandwidth of approximately -15dB. This wide frequency band, while useful in many applications, can allow high frequency noise to modulate the gain control input. In practice, this modulation is easily avoided by additional external filtering (rf and cf) of the control input as shown in Figure 52. Stepping the control voltage from 0V to 1.2V, the gain control response time is typically less than 500ns to settle within 10% of the final signal level at the 1VPP (–6dBFS) output. The control voltage input (VCNTL pin) represents a high impedance input. Using the VCNTL pins of each device, multiple AFE5805 devices can be connected in parallel without significant loading effects. Note that when the vcntl pin is not connected, it floats to a potential of about +3.7V. For any voltage level above 1.2V and 5.0V, the VCA continues to operate at its minimum attenuation level; however, it is recommended to limit the voltage to approx. 1.5V or lower.

When the AFE5805 operates in CW mode, the attenuator stage remains connected to the LNA output. Therefore, it is recommended to set the VCNTL voltage to +1.2V to minimize the internal loading of the LNA output. Smaller power consumption and improved distortion performance can also be achieved. improvement of.

Continuous Wave Doppler Processing

The AFE5805 integrates many of the components required to implement a CW Doppler processing circuit, such as a V/I converter per channel and a crosspoint switch matrix with an 8-input 10-output (8×10) configuration. In order to switch the AFE5805 from the default TGC mode operation to CW mode, Bit D5 of the VCA control register must be updated to low ("0"); see Table 5. This setting also allows access to all other registers that determine the switch matrix configuration (see Input Register Bits mapping table). To process CW signals, the LNA is internally fed into a differential V/I amplifier stage. The transconductance of the v/i amplifier is typically 15.6ma/v with an input signal of 100mvpp. For proper operation, the CW output must be connected to an external bias voltage of +2.5V. Each CW output is designed to receive a small DC current of 0.9mA and can provide up to 2.9mAP of signal current.

The resulting signal current then passes through an 8×10 switch matrix. Depending on the programmed configuration of the switch matrix, any V/I amplifier current output can be connected to any of the 10 CW outputs. This design is a simple current summing circuit such that each CW output can represent the sum of any or all channel currents. The CW output is usually routed to a passive LC delay line, allowing coherent summation of the signals. After summing, the cw signal path further includes a high dynamic range mixer for downconversion to I/Q baseband signals. The i/q signal is then band limited (ie, low frequency content is removed) on a pair of high resolution, low sample rate ADCs.

clock input

Eight channels on the device are operated by one clock input. To ensure that aperture delay and jitter are the same for all channels, the afe5805 uses a clock tree network to generate separate sampling clocks for each channel. The clock paths of all channels are matched from the source point to the sampling circuit. This architecture ensures the same performance and timing for all channels. Matching using a clock tree introduces an aperture delay, which is defined as the delay between the rising edge of FCLK and the actual sampling instant. The aperture delays of all channels are matched to the best possible degree between the aperture instants of the eight ADCs within the same chip. There is a mismatch of ±20PS (±3s). However, the aperture delay of the ADC can be several hundred picoseconds between two different chips.

The AFE5805 can operate in CMOS single-ended clock mode (diff_clk=0 by default) or differential clock mode (sine, lvpecl or lvds). In single-ended clock mode, clkm must be forced to 0vdc and single-ended cmos is applied on the clkp pin, Figure 54 shows this operation.