feature
+2.2 GHz operation
+ Dual band optimization
+Low supply current (5.1mA)
+Surface mount 14-pin TSSOP components
+ Scaled PD gain for dual frequency operation
+ Programmable phase detector polarity
+ Sync or force counter updates to load
+ Power down mode via external pin or serial bus
+ Reference for low load capacitance applications on input buffers
+ GSM900 / 1800 /1900 series
+North America IS-136/137
+ Personal Digital Cellular (Japan RCR-27)
+ Personal Handy Phone (Japan RCR-28)
+CDMA (IS-95)

W3000 is a high-performance ultra-high-frequency RF phase-locked loop synthesizer, specially designed for digital wireless communication applications, with special emphasis on dual-frequency applications in the design, in addition to the outer loop filter circuit required for single-frequency applications, no need Nearly seamless switching between operating frequency bands Combined with a suitable reference crystal, UHF VCO and associated loop filter components, the W3000 provides a very low noise oscillator solution.
The reference signal is divided by programmable 11-bit counters to provide a wide range of comparison frequencies, allowing compliance with various standards. The reference input is rising edge triggered, we recommend using a reverse buffer when interfacing the W3000 with a commercial TCXO.
The main input signal normally associated with the UHF VCO is fed into a dual modulo prescaler (64/65) and divided by the 11-bit main counter for comparison with the output of the reference counter in the digital phase detector.
The W3000 is implemented with a programmable charge pump current, allowing fast band switching in dual-band applications without changing the loop filter. The charge pump can be programmed internally or externally using a resistor (recommended). The charge pump output can be disabled, allowing open loop VCO modulation schemes.
With synchronous reload, when the counter reaches zero, the counter is reloaded with a new programmed value. In the case of a forced counter reload, the reload occurs while the program word is locked. These techniques can improve the time to perform a double frequency hop or lock during a start-up condition.
The W3000 uses a standard 3-wire programming bus (data, enable, clock) and operates up to 10 MHz. This serial interface is via a 24-bit word, including register addressing and device addressing, allowing the two chips to share the bus.

Absolute Maximum Ratings Stresses in excess of the Absolute Maximum Ratings can cause permanent damage to the device. These are absolute pressure ratings only. Functional operation of the device at these or any other conditions is not meant to exceed those given in the operating section of the data sheet. Prolonged exposure to Absolute Maximum Ratings can adversely affect device reliability.
Parameter Symbol Min Max Unit Ambient Operating Temperature ta–30 85°C
Storage temperature TSTG–65 150°C
Lead temperature (soldering, 10 s) TL-300°C
Positive supply voltage VDD 0 4.5 Vdc
Positive charge pump supply voltage vddc 0 4.5 vdc
Power consumption PD - 250 mW AC input voltage - 0 VDD Vp-p
Digital Voltage - vss – 0.3 vdd + 0.3 vdc
Electrostatic Discharge Considerations Although protective circuitry has been designed into this unit, appropriate precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and installation. Lucent Microelectronics employs the Human Body Model (HBM) and Charge Device Model (CDM) for ESD susceptibility testing and protection design evaluation. The ESD voltage threshold depends on the circuit parameters used to define the model. The CDM has not adopted any industry standards. However, standard HBM (resistance = 1500Ω, capacitance = 100 pF) is widely used and, therefore, can be used for comparison purposes.

charge pump current

Function description
The W3000 contains a reference register (REF) and a main register (main). The REF register is used to program the division ratio of the reference clock and the initial setting of the operating mode. The main register is used for frequently occurring programming, such as dynamic channel switching and placing the w3000 in Power saving mode.
Register Programming Diagram
Both the REF and main registers are programmed individually, and each register has a 24-bit data sequence. The last bit is the bit immediately preceding the low-to-high latch input transition that occurs when the clock input is low. Bit 24 is loaded first and bit 1 is loaded last. The last bit in the sequence is c0. This bit is used to direct a 24-bit sequence to the main or reference register

Phase lock detection function
The W3000 provides basic lock detection for troubleshooting or system specification requirements.
In the w3000, the lengths of the upper and lower pulses applied to the loop filter are compared to a reference clock period. The ld line is asserted if the current pulse for 15 consecutive compare cycles is shorter than the reference clock cycle. If a current pulse longer than the reference clock period is detected, the ld line is not set.
The ld line signals the pll fault status. It does not provide true loop lock output. For example, in a GSM system with a reference clock of 13mhz and a comparison frequency of 200khz, to assert the LD line, 15 consecutive current pulses need only be less than 1/65 of a period, which corresponds to a phase of about 0.4 degrees. In the worst case, if the phase stays within this limit, moving from one extreme to the other, the frequency will only be within 0.2%, which is 4MHz on a 2GHz VCO.
The LD outputs of the W3000 are standard logic signals and do not require external comparisons or RC filters.
Typical performance characteristics

The main and reference inputs are set to induce a small beat frequency at the phase detector input. This will produce a sawtooth signal at the output of the charge pump of known slope. The amplitude of the UHF source is reduced. The sensitivity limit is reached when the slope of the waveform deviates from the calculated value. Then repeat this for the reference source.