Features: CPU Core Power: 0.925V to 2.0V Output Range Reference Accuracy Over ±1% of Temperature Dynamic Voltage Setting Using 5-Bit DAC 6V to 24V Input Voltage Range Two-Phase Interleaved Switching Active Droop Differential Remote for Reduced Output Capacitor Size Voltage Sensing High Efficiency: 90% Efficiency Over Wide Load Range 80% Efficiency at Light Load Good Voltage Dynamic Response Feedforward and Average Current Mode Control Sense or Precision Current Sensing Using Sense Resistors Fault Protection: Over Voltage, Over Current and Thermal Shutdown Control: Enable, Forced PWM, Power Good, Power Good Delay Qsop28 and TSsop28

Application: AMD Mobile Athlon CPU VCORE Regulator Graphics Chip vCore Regulator

General Description: 5240 -ic/" title="FAN5240 Product Specifications, Documentation and Source Information" target="_blank">FAN5240 is a single output 2-phase synchronous buck controller to power amd's mobile cpu core. This FAN5240 includes a 5 A digital-to-analog converter (DAC) is used to adjust 0.925VDC to 2.0VDC, in operation. Special measures are taken to enable the output to convert to a controlled slew rate to comply with AMD's power technology The FAN5240 includes an accurate reference, and a proprietary Architecture Integrated compensation provides excellent static and dynamic core voltage regulation. The regulator includes special circuits that balance the two-phase currents for maximum efficiency. At light loads, when the filter inductor current becomes discontinuous, the controller operates in hysteretic mode , significantly improves system efficiency. fpwm suppresses hysteresis operation mode control pin. Fan 5240 monitors output voltage and issues PGOOD (power good) when soft start is complete and output is in regulation. Provides a pin to add latency to connect with an external capacitor .Built-in overvoltage protection (OVP) forces the mosfet on to prevent the output from exceeding a set of voltages. The overcurrent circuit of the PWM controller monitors the converter load by sensing the voltage drop across the lower mosfet. The overcurrent threshold is determined by an external resistor If precision overcurrent protection is required, an optional external current sense resistor can be used.

Circuit Description Overview: The FAN5240 is a 2-phase, single-output power management IC that provides low voltage, high current to power modern processors in notebook computers. Using few external components, the IC controls a precisely programmable synchronous buck converter to drive an external n-channel power MOSFET. By changing the DAC (VID) code setting (see Table 2). The output voltage of the core converter can be programmed with a programmable slew rate, meeting the critical requirements of AMD's mobile Athlon/Duron processors. The converter can operate in two modes: fixed frequency PWM and variable frequency hysteresis depending on the load. Hysteresis mode is active for operation when the load is below the point where the filter inductor current becomes discontinuous. Switching from pwm to hysteretic operation at light loads improves converter efficiency-efficiency and extends battery runtime. Continuous current operation has resumed as the filter inductor resumes. Initialization, soft-start and pgood Assuming EN is high, FAN5240 initialization is applied on VCC at power-up. If VCC falls below the UV low pressure threshold, an internal power-on reset function disables the chip. The IC tries to regulate the vcore output based on the voltage appearing on the ss pin (vss). During converter startup, this voltage is initially 0 and rises linearly to 90% of the VID programming voltage. The 25µA internal current supplies the current source to the CSS. The time required to reach this threshold is: Where, if the CSS unit is μF, then T90% is in seconds. At this point, the current source becomes 500 microamps, which determines the output in response to video changes. This dual ramp method helps to provide voltage and current start-up in the converter at the initial stage while setting the control speed to do so when the core voltage changes when commanded by the processor.

The css is usually based on responsiveness to video changes. For example, if the spec requires 500 mV steps in 100 microseconds:

Assuming that vid is set to 1.5v, and the value of css is this value, find the time for the output voltage to rise to 0.9 of VVID using Equation 1:

The transition from 90% vid to 100% vid accounts for 0.5% of the entire soft start time, the tss is basically t90%. The pgood delay (tdly, Figure 3) can be programmed if the capacitor is grounded on pin 16 (delay):

CDELAY is typically selected to provide a 1ms "blanking" shutdown for overcurrent. The following conditions set the PGOOD pin low: A Brownout – vCore is below a fixed voltage. 2. Due to over temperature or over current is defined as follows.

The converter operates at rated current, and the frequency converter operates in pwm mode with a fixed frequency. The comparison output voltage is set by the DAC to the reference voltage, which appears on the SS pin. The derived error signal is internally compensated by the inverting input of the error amplifier and its applied pwm comparator. To provide the output voltage drop for enhanced dynamic load regulation, a signal proportional to the output current is added to the A1+ input voltage feedback signal. Since the processor specifies VCORE, phase load balancing using a 30µA current source and an external 1K resistor is achieved by adding a signal proportional to the difference between the two phase currents before the error amplifier (at nodes A and B). This feedback scheme, combined with a pwm ramp proportional to the input voltage, allows a fast settling loop for a wide range of input voltage and output responses to current changes. For efficiency and maximum simplicity, the current sense signal is derived from the voltage drop conduction time of the low power mosfet during its operation. This current sense signal is used to set the droop level as well as phase balance and current limit.

The PWM controller is in the path from the error amplifier to the PWM comparator. During a heavily loaded step, the error amplifier from the error amplifier can enter its orbit, pushing the duty cycle to almost 100% for a considerable period of time. This can cause a severe rise in the inductor current, especially if the battery voltage is too high, resulting in excessive recovery time or even if the converter fails. To prevent this, the output error amplifier is detected in both if large output voltage excursions are detected. The sensitivity of this circuit is set to not affect the PWM control expected from the load during the transition.

Operation Mode Control The mode control circuit changes the mode of the converter from pulse width modulation to hysteresis and vice versa, based on the voltage polarity of the sw node. The lower MOSFET is conducting, just before the upper MOSFET is turned on. For continuous inductor current, when the lower mosfet is on and the converter is operating at a fixed frequency, the sw node is negative as shown in the PWM mode. This mode of operation enables high efficiency at rated load. When the load current is reduced to the point where the inductor current is in the "reverse" direction through the lower mosfet, the sw node becomes positive, the mode changes to hysteretic, and the efficiency is higher - efficiency at lower currents by reducing the effective switching frequency. Prevents accidental mode changes or "mode jitter" when the SW node is positive for eight consecutive clock cycles. The polarity of the sw node is the sampling time at the end of the lower MOSFET conduction. In the transition mode between pwm and hysteresis, both the upper and lower mosfets are turned off. The phase node will "ring" based on the output inductance and parasitic capacitance on the phase node and settle at the output voltage value. The boundary value of the inductor current, where the current becomes discontinuous, can be estimated by the following expression. The hysteretic mode is the opposite, the transition from hysteretic mode to pwm mode occurs when the sw node is negative for 8 consecutive cycles. A sudden increase in output current also causes a switch from hysteretic mode to PWM mode. This batch increase causes the output voltage to drop due to the output voltage capacitor ESR. If the load causes the output voltage (as seen at VSN) to drop below the hysteretic regulation level (20 mV below VREF), the mode changes to PWM for the next clock cycle. This Guaranteed for full power output current increase as required. In hysteretic mode, the pwm comparator and its error amplifiers that provide control in PWM mode are disabled. The hysteretic comparator is activated. hysterical mode low side mosfet operates as a synchronous rectifier where the voltage on vds(on) is monitored and when vds(on) is running its gate is off positive (current flowing back from the load) blocking reverse conduction hysteresis comparator Initiate a pfm signal to turn the output voltage (VSN) below the lower threshold (10mV below VREF) and terminate the PFM signal when VSN rises above the higher threshold (5mV above VREF).

The switching frequency is mainly: 1. The spread between the two hysteresis thresholds 2. The transition of the output inductor capacitor esr back to PWM (continuous conduction mode) or ccm) mode occurs when the inductor current rises enough to keep positive for 8 consecutive cycles Occurs when: In the formula, ∏vhysteresis=15mv, and esr is equal to the series resistance. Due to the different control mechanisms, the transition to CCM operation occurs when the load current is usually higher than the load level at which point it transitions to hysteretic mode.

The discussion below the current processing section refers to the figure. Set the switch node to cross 0V after each phase current sampling of RSENSE is about 200nS. For correct converter operation, choose the RSENSE value: It's about 1K for the components in the diagram. Active droop core converters contain a proprietary output fast load voltage drop method for optimal handling of transients found in modern processors. "Active droop" or voltage positioning is now widely used in computer power supply applications. The technique is based on increasing the inverter voltage load current expectation of a step increase at light loads, and conversely, reducing the vcore in the step expectation. In the case of active droop, the output voltage changes with the load like a resistor with the output of the converter. In series, in other words, what it does is increase the output resistance of the converter. The load current decreases.

To maximize the use of active droop, it should be scaled to match the ESR voltage drop of the output capacitor.

Active droop allows the size and cost of the output to be reduced in capacitors required to handle CPU current transients. The reduction may be a factor of 2 compared to a system without active sag.

In addition, the CPU power consumption is also slightly reduced in proportion to the applied voltage. The squared reduction and even a slight voltage reduction will translate into a measurable reduction in power consumption.

The processor regulation window includes transients specified as +100mV...-50mV to accommodate droop, and the converter's output voltage rises by about 30mV at no load. The converter's response to a load step is shown in the graph. At zero load current, the output voltage is about 30mV above the nominal value of 1.5V. As the load current increases, the output voltage drops by approximately 55mV. The use of an active droop converter allows better utilization of the output voltage regulation with load current.

Layout Considerations Switching converters, even during normal operation, can generate short pulses of current that, if layout is restricted, can cause a lot of ringing and become a source of EMI that goes unobserved. There are two sets of key components in DC-DC converters. Switching power components process large amounts of energy to generate noise at high rates. The feedback function of low power components causing bias is sensitive to noise. A multilayer printed circuit board is recommended. Designating a solid layer for the ground plane dedicates another solid layer as a power layer and destroys this plane into a smaller island of common voltage levels. Note all nodes subject to high dV/dt voltage swings such as SW, HDRV and LDRV. All surrounding circuits tend to couple signals from these nodes through stray capacitance. Do not place oversized copper traces connected to these nodes Do not place traces connected to feedback components close to these traces High density interconnect systems or micro vias are not recommended for these signals Use of blind or buried vias should be limited to low current signals . Normal use of thermal vias is up to the designer.

Keep the trace source of the wiring from the IC to the gate of the mosfet as short as possible, capable of handling a peak current of 2A. Minimize the area within the gate-source path to reduce stray inductance and eliminate parasitic ringing in front of the gate. Locate small critical components, such as soft-start capacitors and current-sense resistors, as close as possible to individual IC pins. FAN5240 adopts advanced packaging technology with a lead pitch of 0.6 mm. High performance narrow lead pitch analog semiconductors may be required in PWB design and manufacturing. Proper cleanliness is critical. The area around these devices is not recommended for use with any type of rosin or acid core solder, or the use of flux in production or repair may result in corrosion or low electromigration and/or eddy current near sensitive points current signal. When these chemicals are used on or near the PWB, it is recommended that the PWB should be thoroughly cleaned and dried prior to use.