Features

Monitor up to 5 supply voltages; control and monitor up to 4 fan speeds; 1 on-chip and 2 remote temperature sensors; monitor up to 6 processor video bits; dynamic tmin control mode intelligently optimizes system acoustics; automatic fan speed Control mode controls system cooling based on measured temperature; enhanced acoustic mode significantly reduces user perception of changes in fan speed; thermal protection via thermal output; monitors Intel Pentium 4 impact on performance; processor thermal control via thermal input Circuit; 2-wire and 3-wire fan speed measurement; limit comparison of all monitored values; compliant with SMBus 2.0 electrical specification (full SMBus 1.1 compliant).

application

Low noise pcs; networking and telecommunication equipment.

General Instructions

The ADT7463 DBCool controller is a complete system monitor and multiple PWM fan controller for noise sensitive applications requiring active system cooling. It can monitor CPU supply voltages of 12V , 5V and 2.5V, plus its own supply voltage. It can monitor the temperature of up to two remote sensor diodes, plus its own internal temperature. It can measure and control the speed of up to four fans, running them at the lowest possible speed for minimal noise. An automatic fan speed control loop optimizes fan speed for a given temperature. Unique dynamic tmin control mode enables intelligent management of system thermal/acoustics. The effectiveness of the system's thermal solution can be monitored by heat input. The ADT7463 also uses a bidirectional thermal pin as an output to provide critical thermal protection for the system to prevent overheating of the system or components.

Functional Description General Description

The ADT7463 is a complete system monitor and multi-fan controller for any system requiring monitoring and cooling. Devices communicate with the system through the serial system management bus. The serial bus controller has an optional address line (pin 14) for device selection, a serial data line (pin 1) for reading and writing address and data, and an input line for serial clock (pin 1). pin 2). All control and programming functions of the ADT7463 are performed over the serial bus. Additionally, two of these pins can be reconfigured as SMBALERT outputs to indicate limit violations.

Measurement input

The unit has six measurement inputs, four for voltage and two for temperature. It can also measure its own supply voltage and can measure the ambient temperature with its on-chip temperature sensor.

Pins 20 to 23 are analog inputs with on-chip attenuators configured to monitor 5 V, 12 V, 2.5 V, and the processor core voltage (2.25 V input), respectively.

Power is supplied to the chip through pin 4, and the system also monitors VCC through this pin. In pcs, this pin is usually connected to a 3.3v backup power supply. However, this pin can be connected to a 5 V supply and monitored without changing the range too much.

Remote temperature sensing is provided by the d1 and d2 inputs, diodes are connected to the d1 and d2 inputs, and external temperature sensing transistors such as 2N3904 or CPU thermal diodes can be connected to the d1 and d2 inputs.

The ADC also accepts input from an on-chip bandgap temperature sensor that monitors the ambient temperature of the system.

sequential measurement

When the ADT7463 monitoring sequence starts, it loops in turn measuring the analog input and the temperature sensor. The measured values of these inputs are stored in value registers. These can be read out over the serial bus or compared to programmed limits stored in limit registers. The result of the out-of-limit comparison is stored in a status register that can be read over the serial bus to flag an out-of-limit condition.

Processor Voltage ID

Five digital inputs (VID0 to VID5 pins 5 to 8, 19 and 21) read the processor voltage ID code and store it in the VID register, from which the management system can read it via the serial bus. The vid code monitoring feature is compatible with both vrm9.x and future vrm10 solutions. Additionally, SMBALERT can be generated to flag changes in the VID code.

ADT7463 address selection

Pin 13 is the dual function PWM3/address enable pin. If pin 13 is pulled low at power-up, the ADT7463 reads the state of pin 14 (TACH4/Address Select/Therm pin) to determine the slave address of the ADT7463. If pin 13 is high at power-up, the ADT7463 defaults to SMBus slave address 0x2e.

Internal registers of the ADT7463

The main internal registers of the ADT7463 are briefly described below.

configuration register

The configuration registers provide control and configuration of the ADT7463, including alternate pin-out functions.

address pointer register

This register contains the address to select one of the other internal registers. When writing to the ADT7463, the first byte of data is always a register address, which is written to the address pointer register.

state register

These registers provide the status of each limit comparison and are used to signal an out-of-limit condition on the temperature, voltage, or fan speed channels. If pin 10 or pin 22 is configured as smbalert, this pin will be asserted low whenever a status bit is set.

interrupt mask register

These registers allow masking of each interrupt status event when pin 10 or pin 22 is configured as a SMBALERT output.

video register

The state of the processor's vid0 to vid5 pins can be read from this register. vid code changes can also generate smbalert interrupts.

Value and Limit Registers

The results of the analog voltage input, temperature and fan speed measurements and their limits are stored in these registers.

offset register

These registers allow each temperature channel reading to be offset by the two's complement value written to these registers.

tmin register

These registers program the startup temperature of each fan under automatic fan speed control.

transfer register

These registers program the temperature to fan speed control slope for each PWM output in automatic fan speed control mode.

operating point register

These registers define the target operating temperature for each thermal zone when operating under dynamic tmin control. This feature allows the cooling solution to be dynamically adjusted based on measured temperature and system performance.

Enhanced Acoustic Register

These registers allow adjustment of each PWM output to control the fan to enhance the acoustics of the system.

Typical Performance Characteristics - ADT7463

recommended implementation

Configuring the ADT7463 as shown in Figure 2 allows the system designer to have the following capabilities:

(1), Six VID inputs (VID0 to VID5) for VRM1 support.

(2) Two PWM outputs for fan control of up to three fans (front and rear chassis fans are connected in parallel).

(3), three tachometer fan speed measurement input.

(4) VCC is internally measured through pin 4.

(5), CPU core voltage measurement (VCore).

(6), 2.5V measurement input for monitoring CPU current (connected to VCOMP output of ADP316x VRM controller) This is used to determine CPU power consumption.

(7), 5 V measurement input.

(8) The VRM temperature uses a local temperature sensor.

(9) Use the remote 1 temperature channel to measure the CPU temperature.

(10) Ambient temperature measured by remote 2 temperature channels.

(11) If VID5 is not used, this pin can be reconfigured as 12 V monitoring input.

(12) Two-way hot pins. Allows Intel Pentium 4 processors to monitor and output as overheat.

(13), smbalert system interrupt output.

serial bus interface

Control of the ADT7463 is performed under the control of a master controller using the Serial System Management Bus (SMBus) to which the ADT7463 is connected as a slave device.

The ADT7463 has a 7-bit serial bus address. When the device is powered up with pin 13 (PWM3/address enable) high, the default SMBus address for the ADT7463 is 0101110 or

0x2E. A read/write bit must be added to obtain an 8-bit address. If multiple ADT7463s are used in a system, each ADT7463 should enter address select mode by holding pin 13 low at power up. The logic state of pin 14 then determines the smbus address of the device. The logic of these pins is sampled at power up.

When the serial bus address byte matches the selected slave address, the device address is performed on the first valid SMBus transaction (more precisely the low-to-high transition at the beginning of the 8th SCL pulse) Sampling and Latching Use the Address Enable/Address Select pins to select the selected slave address. After this, any attempted changes in the address will have no effect.

The ability to make hardwired changes to the SMBUS slave address allows the user to avoid conflicts with other devices sharing the same serial bus, for example if multiple ADT7463s are used in the system.

The serial bus protocol operates as follows:

1. The host initiates a data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line sda, while the serial clock line scl remains high. This means that the address/data stream will follow. All slave peripherals connected to the serial bus respond to the start condition and shift in the next 8 bits, including the 7-bit address (msb first) plus the r/w bit, which determines the direction of data transfer , i.e. whether the data will be written or read from the slave device.

no connection

The peripheral whose address corresponds to the address sent responds by pulling the data line low during the low cycle before the ninth clock pulse (called the acknowledge bit). All other devices on the bus are now idle while the selected device is waiting to read or write data from it. If the r/w bit is 0, the master writes to the slave. If the r/w bit is 1, the master reads from the slave.

2. Data is sent over the serial bus in the order of 9 clock pulses, 8 bits of data, and an acknowledgment bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period because a low-to-high transition while the clock is high can be interpreted as a stop signal. The number of bytes of data that can be transferred over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle.

3. A stop condition is established when all data bytes are read or written. In write mode, the master asserts a stop condition by pulling the data line high during the tenth clock pulse. In read mode, the master overwrites the acknowledge bit by pulling the data line high in the low cycle before the ninth clock pulse. This is called non-recognition. The master then asserts the stop condition by taking the data line low during the low period before the 10th clock pulse and then high during the 10th clock pulse.

In one operation, any amount of data can be transferred over the serial bus, but it is not possible to mix reads and writes in one operation because the operation type is determined at the beginning and cannot be done without starting a new operation Subsequent changes.

In the case of the adt7463, a write operation contains one or two bytes, and a read operation contains one byte and performs the following functions.

To write data to or read data from one of the device data registers, the address pointer register must be set up so that the correct data register can be addressed before data can be written to or read from it. The first byte of a write operation always contains the address stored in the address pointer register. If data is to be written to the device, the write operation consists of writing the second data byte of the register selected by the address pointer register.

As shown in Figure 7. The device address is sent over the bus and then R/W is set to 0. Followed by two data bytes. The first data byte is the address of the internal data register to be written, which is stored in the address pointer register. The second data byte is the data to be written to the internal data register.

When reading data from a register, there are two possibilities:

1. If the address pointer register value of the ADT7463 is unknown or not the desired value, it first needs to be set to the correct value before data can be read from the desired data register. This is done by performing a write to the ADT7463 as before, however, only the data byte is sent and it contains the register address. As shown in Figure 8.

A read operation is then performed, including the serial bus address, the r/w bit is set to 1, and the data byte is read from the data register. As shown in Figure 9.

2. If the address pointer register is already at the desired address, data can be read from the corresponding data register without first writing to the address pointer register, so Figure 8 can be omitted.

notes

1. If the value of the address pointer register is already correct, a data byte can be read from the data register without first writing to the address pointer register. However, it is not possible to write data to the address pointer register, because the first data byte written is always written to the address pointer register.

2. In Figures 7 to 9, the serial bus address is shown as the default value of 01011(a1)(a0), where a1 and a0 are set by the previously defined address selection mode function.

3. In addition to supporting the Send Byte and Receive Byte protocols, the ADT7463 also supports the Read Byte protocol (see System Management Bus Specification Revision). 2.0 for more information).

4. If multiple read or write operations need to be performed, the host can send a repeated start condition instead of a stop condition to start a new operation.

ADT7463 Write Operation

The smbus specification defines several protocols for different types of read and write operations. Those used in the ADT7463 are discussed below. The following abbreviations are used in the diagrams: s–start

P – Stop; R – Read; W – Write; A – Acknowledge; A – Not Acknowledge; the ADT7463 uses the following SMBus write protocol.

send bytes

In this operation, the master sends a single command byte to the slave as follows:

1. The master asserts a start condition on sda.

2. The master sends the 7-bit slave address followed by the write bit (low).

3. The addressing slave asserts ack on sda.

4. The host sends the command code.

5. The slave asserts ack on sda.

6. The primary server declares a stop condition on sda and the transaction ends.

For the ADT7463, the send byte protocol is used to write a register address to RAM so that subsequent single bytes can be read from the same address. As shown in Figure 10.

If data needs to be read from a register immediately after setting the address, the host can assert a Repeated Start condition immediately after the final ack and perform a single-byte read without asserting an Intermediate Stop condition.

write bytes

In this operation, the master device sends a command byte and a data byte to the slave device as follows:

1 Master asserts start condition on sda.

2. The master sends the 7-bit slave address followed by the write bit (low).

3. The addressing slave asserts ack on sda.

4. The host sends the command code.

5. The slave asserts ack on sda.

6. The host sends a data byte.

7. The slave asserts ack on sda.

8. The host asserts a stop condition on sda to end the transfer. As shown in Figure 11.

ADT7463 read operation

The ADT7463 uses the following SMBus read protocol.

receive bytes

This is useful when reading a single register repeatedly. The registered address needs to be pre-set. In this operation, the master device receives a single byte from the slave device as follows:

1. The master asserts a start condition on sda.

2. The master sends a 7-bit slave address followed by a read bit (high).

3. The addressing slave asserts ack on sda.

4. The host receives a data byte.

5. The captain did not confirm on sda.

6 The master declares a stop condition on sda and the transaction ends.

In the ADT7463, the receive byte protocol is used to read a single byte of data from a register whose address was previously set by a send byte or write byte operation.

Alert response address

The Alarm Response Address (ARA) is a feature of SMBus devices that allows an interrupting device to identify itself to the host when multiple devices are present on the same bus.

smbalert output can be used as interrupt output or as smbalert. One or more outputs can be connected to a common smbalert line connected to the main server. If the device's smbalert line goes low, the following process occurs:

1. SMBALERT is pulled low.

2. The host initiates a read operation and sends an alert response address (ARA=0001 100) This is a general call address that cannot be used as a specific device address.

3. The device whose SMBALERT output is low responds to the alarm response address, and the host reads its device address. The address of the device is now known and can be queried in the usual way.

4. If the smbalert output of multiple devices is low, the device with the lowest device address will have a priority consistent with normal smbus arbitration.

5. Once the ADT7463 responds to the alert response address, the host must read the status register and clear the SMBAlert only when the error condition disappears.

SMBus timeout

The ADT7463 includes an SMBus timeout function. If there is no smbus activity for 35 ms, the adt7463 assumes the bus is locked and releases the bus. This prevents the device from locking up or holding onto data required by SMBus. Some SMBus controllers cannot handle the SMBus timeout feature, so it can be disabled.

Configuration Register 1 – Register 0x40

<6>TODIS=0; Enable SMBus timeout (default)

<6>TODIS=1; SMBus timeout disabled

2 – Rev. C The ADT7463 has four external voltage measurement channels. It can also measure its own supply voltage, VCC. Voltage measurement input

Pins 20 to 23 are dedicated to measuring 5 V, 12 V, and 2.5 V supplies and processor core voltage VCCP (0 V to 3 V input). VCC supply voltage measurements are made through the VCC pin (pin 4). Setting Bit 7 of Configuration Register 1 (Register 0x40) allows a 5 V supply to power the ADT7463 and make measurements without changing the range of the VCC measurement channel. The 2.5V input can be used to monitor the supply voltage of the chipset in a computer system.

analog to digital converter

All analog inputs are multiplexed to the on-chip, successive approximation, ADC. Its resolution is 10 bits. The basic input range is 0 V to 2.25 V, but the inputs have built-in attenuators that allow measurement of 2.5 V, 3.3 V, 5 V, 12 V, and the processor core voltage VCCP without any external components. To allow for tolerances in these supply voltages, the ADC produces an output of 3/4 full scale (768 decimal or 300 hex) for the nominal input voltage, so there is plenty of headroom for overvoltage.

input circuit

The internal structure of the analog input is shown in Figure 13. Each input circuit consists of an input protection diode, an attenuator, and a capacitor, forming a first-order low-pass filter that makes the input immune to high-frequency noise.

Voltage Measurement Register

Rule: 0x20 2.5 V reading = 0x00 default

Rule: 0x21 VCCP read = 0x00 default

Rule: 0x22 VCC read = 0x00 default

Rule: 0x23 5 V reading = 0x00 default

Rule: 0x24 12 V reading = 0x00 default

Voltage Measurement Limit Register

Associated with each voltage measurement channel are high and low limit registers. Exceeding the programmed upper or lower limit sets the corresponding status bit. Exceeding either limit also generates an smbalert interrupt. rule. 0x44 2.5 V lower limit = 0x00 default value

Rule: 0x45 2.5 V cap = 0xFF default

Rule: 0x46 VCCP lower limit = 0x00 default value

Rule: 0x47 VCCP cap = 0xFF default

Rule: 0x48 VCC lower limit = 0x00 default value

Rule: 0x49 VCC cap = 0xFF default registry. 0x4A 5 V lower limit = 0x00 default value

Rule: 0x4B 5 V cap = 0xFF default

Rule: 0x4C 12 V lower limit = 0x00 default

Rule: 0x4D 12 V cap = 0xFF default

When the ADC is running, it samples and converts the voltage input in 711 microseconds, averaging 16 conversions to reduce noise; it typically takes 11.38ms to measure each input.

Video encoding monitoring

The ADT7463 has five dedicated voltage ID (video code) inputs.

These are digital inputs and can be used to determine the processor voltage required/in use in the system via the video register (REG.0x43). Five video code inputs support VRM9.x solutions. Also, pin 21 (12v input) can be reconfigured as a sixth vid input to meet future vrm requirements.

Video Encoding Register - Register 0x43

<0> = video (reflects the logic state of pin 5)

<1> = Video 1 (reflects the logic state of pin 6)

<2> = Video 2 (reflects the logic state of pin 7)

<3> = Video 3 (reflects the logic state of pin 8)

<4> = Video 4 (reflects the logic state of pin 19)

<5> = Video 5 (reconfigurable 12 V input) When pin 21 is configured as a 12 V input, this bit reads 0. When the pin is configured as VID5, this bit reflects the logic state of pin 21.

Video Encoding Input Threshold Voltage

The switching threshold of the VID code input is approximately 1v. For future compatibility, the vid code input threshold can be lowered to 0.6v. Bit 6 (thld) of the vid register (REG). 0x43) Controls the video input threshold voltage.

Video Encoding Register - Register 0x43

<6>thld=0; vid switch threshold=1v, vol<0.8v, vih>1.7v, vmax=3.3v thld=1; vid switch threshold=0.6v, volume<0.4 V, VIH>0.8 V, Vmax= 3.3V.

Reconfigure pin 21 (+12V/VID5) as VID5 input

Pin 21 can be reconfigured to be the sixth vid code input (vid5) for vrm10 compatible systems. Since the pin is configured as VID5, the 12 V supply can no longer be monitored.

The video register (REG.0x43) determines the function of pin 21. The system or bios software can read the status of bit 7 to determine if the system is designed to monitor 12v or the sixth vid input.

Video Encoding Register - Register 0x43

<7>vidsel=0; pin 21 is used as a 12 V measurement input. Software can read this bit to determine that five video inputs are being monitored. Bit 5 of register 0x43 (VID5) always reads back 0. Bit 0 of Status Register 2 (Register 0x42) reflects the 12 V overrun measurement.

VIDSEL = 1; pin 21 is used as the sixth video code input (VID5). Software can read this bit to determine that six video inputs are being monitored. Bit 5 of Register 0x43 reflects the logic state of pin 21 Status Bit 0 of Register 2 (Register 0x42) reflects the video code change.

Video encoding change detection function

adt7463 has vid code change detection function. When pin 21 is configured as a vid5 input, the ADT7463 can detect and report changes in the vid code. Bit 0 of Status Register 2 (Register 0x42) is the 12V/VC bit and represents the VID change on set. The vid code change bit is set when the logic state on the vid input is different from the previous 11 microseconds. Changes to the VID code can be used to generate SMBAlert interrupts. If the SMBALERT interrupt is not required, then Interrupt Mask Register 2 (Reg, Bit 00x75), when set, prevents smbalerts from occurring when the video code changes.

Status Register 2 - Register 0x42<0> 12V/VC = 0; if pin 21 is configured as vid5, a logic 0 indicates that the vid code has not changed in the past 11 microseconds.

<0>12V/Vc=1; if pin 21 is configured as VID5, a logic 1 indicates that the VID code input has changed within the past 11 microseconds. If this feature is enabled, a smbalert is generated.

Additional ADC functions

Several additional features are available to users to provide greater flexibility for system designers, including:

off average

For each voltage measurement read from the value register, 16 readings have actually been taken internally, and averaging the results before putting them into the value register may have an instance where you want to speed up the conversion. Setting Bit 4 of Configuration Register 2 (Register 0x73) turns off averaging. This effectively speeds up reads by a factor of 16 (711 microseconds), but reads can be noisier.

Bypass Voltage Input Attenuator

Setting Bit 5 of Configuration Register 2 (Reg 0x73) removes the attenuation circuit from the 2.5 V, VCCP, VCC, 5 V, and 12 V inputs. This allows the user to directly connect external sensors or rescale the analog voltage measurement input for other applications. The input range of the ADC without the attenuator is 0v to 2.25v.

single channel adc conversion

Setting Bit 6 of Configuration Register 2 (Register 0x73) places the ADT7463 in single-channel ADC conversion mode. In this mode, the ADT7463 can only read a single voltage channel. If the internal ADT7463 clock is used, the selected input is read every 711 microseconds. Select the appropriate ADC channel by writing to Bits<7:5> of the TACH1 Minimum High Byte register (0x55).

Temperature measurement system Local temperature measurement

The ADT7463 contains an on-chip bandgap temperature sensor whose output is digitized by an on-chip 10-bit ADC. The 8-bit MSB temperature data is stored in the local temperature register (address 26h) because it can measure positive and negative temperatures, the temperature data is stored in two's complement format, as shown in Table 3. In theory, the temperature sensor and ADC can measure temperatures from -128C to +127C with a resolution of 0.25C. However, this is outside the operating temperature range of the device, so local temperature measurements outside this range are not possible.

Remote temperature measurement

The ADT7463 can measure the temperature of two remote diode sensors or diode-connected transistors connected to pins 15 and 16, or 17 and 18.

The forward voltage of a diode or diode-connected transistor operating at constant current shows a negative temperature coefficient of about -2 mV/C. Unfortunately, the absolute value of VBE varies from device to device and requires individual calibration to remove it, so this technique is not suitable for mass production. The technique used in the ADT7463 is to measure the change in VBE when the device is operated at two different currents. This is Depend on:

where: K is the Boltzmann constant. Q is the charge on the carrier. Type T is absolute temperature in Kelvins. n is the ratio of the two currents.

Figure 14 shows the input signal conditioning used to measure the output of a remote temperature sensor. This image shows an external sensor as a substrate transistor used to monitor temperature on some microprocessors. It can also be a discrete transistor such as the 2N3904.

If using a discrete transistor, the collector will not be grounded and should be connected to the base. If using a PNP transistor, the base should be connected to the D- input and the emitter to the D+ input. If using an NPN transistor, the emitter is connected to the D- input and the base is connected to the D+ input Figures 15a and 15b show how to connect the adt7463 to an npn or pnp transistor for temperature measurement. To prevent ground noise from interfering with the measurement, the more negative terminal of the sensor is not referenced to ground, but is biased to ground by an internal diode at the D- input.

To measure ∏vbe, the sensor switches between the operating currents of I and NI. The resulting waveform is passed through a 65 kHz low-pass filter to remove noise and passed to a chopper-stabilized amplifier that performs waveform amplification and correction functions to produce a DC voltage proportional to ∏vbe. This voltage is measured by the ADC, which outputs the temperature in 10-bit 2's complement format. To further reduce the effect of noise, digital filtering is performed by averaging the results over 16 measurement cycles. Remote temperature measurements typically take 25.5 ms. The results of the remote temperature measurement are stored in 10-bit, 2's complement format. Additional resolution for temperature measurements is stored in Extended Resolution Register 2 (REG). 0x77). This gives a temperature reading with a resolution of 0.25 degrees Celsius.

Eliminate temperature errors

As CPUs run faster, it becomes increasingly difficult to avoid high frequency clocks when routing D+, D- traces on the system board. Even if the recommended layout guidelines are followed, there may be temperature errors due to noise coupling onto the D+/D- lines. High frequency noise often has the effect of excessive temperature measurements. The ADT7463 has temperature offset registers for the Remote 1 and Remote 2 temperature channels at Address 0x70, 0x72. By performing a one-time calibration of the system, the offset caused by system board noise can be determined and zeroed using the offset register. The offset register automatically adds two 8-bit readings to each temperature measurement. The LSB adds a 0.25°C offset to the temperature reading, so the 8-bit register effectively allows up to 32C of temperature offset with a resolution of 0.25C. This ensures that the readings in the temperature measurement registers are as accurate as possible.

Temperature Offset Register

Rule: 0x70 remote 1 temperature offset = 0x00 (default 0°C)

Rule: 0x71 local temperature offset = 0x00 (default 0°C)

Rule: 0x72 remote 2 temperature offset = 0x00 (default 0°C)

temperature measurement register

Rules: 0x25 remote 1 temperature = 0x80 default registry 0x26 local temperature = 0x80 default

Rule: 0x27 remote 2 temperature = 0x80 default

Rule: 0x77 extended resolution 2 = 0x00 default

<7:6> TDM2 = Remote 2 Temp LSB <5:4> LTMP = Local Temp LSB

<3:2> TDM1 = Remote 1 Temperature LSB

Temperature Measurement Limit Registers Associated with each temperature measurement channel are the high and low limit registers. Exceeding the programmed upper or lower limit will set the corresponding status bit. Exceeding either limit will also generate a smbalert interrupt.

Rule: 0x4E Remote 1 Temperature Lower Limit = 0x81 Default

Rule: 0x4F remote 1 temperature upper limit = 0x7F default value

Rule: 0x50 local temperature lower limit = 0x81 default value

Rule: 0x51 local temperature upper limit = 0x7F default value

Rule: 0x52 Remote 2 Temperature Lower Limit = 0x81 Default

Rule: 0x53 remote 2 temperature upper limit = 0x7F default value

Reading temperature from ADT7463

It is important to note that the temperature can be read from the ADT7463 as an 8-bit value (with a resolution of 1°C) or a 10-bit value (with a resolution of 0.25°C). If only 1°C resolution is required, the temperature reading can be at any Times are read in any particular order.

If a 10-bit measurement is required, a 2-bit register needs to be read per measurement. The Extended Resolution Register (REG.0x77) should be read first. This will cause all temperature reading registers to freeze until all temperature reading registers are read from. This will prevent the msb read from updating when the 2 lsb of the msb are read and vice versa.

Additional ADC functions

There are many other features on the ADT763 for system designers to add flexibility.

off average

For each temperature measurement read from the value register, 16 readings have actually been taken internally and the results are averaged before putting them into the value register. Sometimes a quick measurement may be required, such as the CPU temperature setting Bit 4 of Configuration Register 2 (Register 0x73) to turn off the average. A reading is taken every 13 milliseconds. The measurement itself takes 4ms.

single channel adc conversion

Setting Bit 6 of Configuration Register 2 (Register 0x73) places the ADT7463 in single-channel ADC conversion mode. In this mode, the ADT7463 can only read a single temperature channel. If the internal ADT7463 clock is used, the selected input is read every 1.4 milliseconds. Select the appropriate ADC channel by writing to Bits<7:5> of the TACH1 Minimum High Byte register (0x55).

overtemperature event

Overtemperature events on any temperature channel can be automatically detected and handled in automatic fan speed control mode. Registers 0x6a to 0x6c are thermal limits. All fans run at 100% duty cycle when temperatures exceed their thermal limits. The fan remains running at 100% until the temperature drops to thermal hysteresis (this can be disabled by setting the boost bit in Configuration Register 3, Bit 2, Register 0x78). The hysteresis value for this thermal limit is the value programmed into Registers 0x6d, 0x6e (hysteresis registers). The default hysteresis value is 4°C.

Limits, Status Registers and Interrupt Limits

Associated with each measurement channel on the ADT7463 are high and low limits. These can form the basis of system status monitoring: status bits can be set for any violation of limits and detected by polling the device. Alternatively, a smbalert interrupt can be generated to flag the processor or microcontroller as out of bounds.

8 bit limit

Below is a list of the 8-bit limitations on the ADT7463.

Voltage Limit Register

Rule: 0x44 2.5 V lower limit = 0x00 default

Rule: 0x45 2.5 V upper limit = 0xFF default

Rule: 0x46 VCCP lower limit = 0x00 default value

Rule: 0x47 VCCP cap = 0xFF default

Rule: 0x48 VCC lower limit = 0x00 default value

Rules: 0x49 VCC cap = 0xFF default registry. 0x4A 5 V lower limit = 0x00 default register 0x4B 5 V upper limit = 0xFF default

Rule: 0x4C 12 V lower limit = 0x00 default

Rule: 0x4D 12 V cap = 0xFF default

temperature limit register

Rule: 0x4E Remote 1 Temperature Lower Limit = 0x81 Default

Rule: 0x4F remote 1 temperature upper limit = 0x7F default value

Rule: 0x6A Remote 1 Thermal Limit = 0x64 Default

Rule: 0x50 local temperature lower limit = 0x81 default value

Rule: 0x51 local temperature upper limit = 0x7F default value

Rule: 0x6B local thermal limit = 0x64 default

Rule: 0x52 Remote 2 Temperature Lower Limit = 0x81 Default

Rule: 0x53 remote 2 temperature upper limit = 0x7F default value

Rule: 0x6C Remote 2 Thermal Limit = 0x64 Default

Thermal Limit Register

Rule: 0x7A Thermal Limit = 0x00 Default

16-bit limit

The fan speed measurement is a 16-bit result and the fan speed limit is also 16 bits, consisting of a high byte and a low byte. Since the fan running at speed or stall is usually the only condition of interest, there is only a high limit to the fan speed. Since the fan speed cycle is actually measured, exceeding this limit indicates a slow or stalled fan.

Fan Limit Register

Rule: 0x54 TACH1 minimum low byte = 0xFF default value

Rule: 0x55 TACH1 minimum high byte = 0xFF default value

Rule: 0x56 TACH2 minimum low byte = 0xFF default value

Rule: 0x57 TACH2 minimum high byte = 0xFF default value

Rule: 0x58 TACH3 minimum low byte = 0xFF default value

Rule: 0x59 TACH3 minimum high byte = 0xFF default value

Rule: 0x5A TACH4 minimum low byte = 0xFF default value

Rule: 0x5B TACH4 minimum high byte = 0xFF default value

Compare out of limit

Once all limits are programmed, the ADT7463 can be enabled for monitoring. The ADT7463 measures all parameters in a loop and sets the appropriate status bits for the limit violation condition. The comparison is done differently depending on whether the measured value is compared to an upper or lower limit.

Analog monitoring cycle time

An analog monitoring cycle begins when a 1 is written to the start bit (bit 0) of Configuration Register 1 (REG). 0x40). The ADC measures each analog input in turn, and after each measurement is completed, the result is automatically stored in the corresponding value register. This loop monitoring loop will continue unless disabled by writing 0 of Configuration Register 1 to Bit 0.

Since ADCs typically run freely this way, the time it takes to monitor all analog inputs is usually not important, as the latest measurement for any input can be read out at any time.

It is easy to calculate for applications where monitoring cycle time is important.

The total number of channels measured is:

• Four dedicated supply voltage inputs

• 3.3 VSTBY or 5 V power supply (VCC pin)

• local temperature

• Two remote temperatures

As mentioned before, the ADC performs a cyclic conversion that takes 11.38 ms for each voltage measurement, 12 ms for the local temperature reading, and 25.5 ms for the remote temperature reading.

Therefore, the total monitoring cycle time for average voltage and temperature monitoring is nominally:

The fan speed measurements are made in parallel and are not synchronized with the analog measurements.

state register

The result of the limit comparison is stored in status registers 1 and 2. The status register bits for each channel reflect the status of the last measurement and limit comparison on that channel. If the measured value is within the limits, the corresponding status register bit is cleared to 0. If the measurement exceeds the limit, the corresponding status register bit is set to 1.

The status of the various measurement channels can be polled by reading the status registers over the serial bus. In Status Register 1 (REG.0x41), 1 indicates that a limit exceeded event is flagged in Status Register 2. This means that the user only needs to read Status Register 2 when this bit is set. Alternatively, pin 10 or pin 22 can be configured as an SMBALERT output which will automatically notify the system supervisor of a limit violation. Whenever the error condition that caused the interrupt is cleared, reading the status register clears the corresponding status bit. Status register bits are "sticky". Whenever a status bit is set, indicating a limit violation, it remains set even if the event that caused it disappears (until read). The only way to clear the status bits is to read the status register after the event disappears. The Interrupt Status Mask Register (REG.0x74, 0x75) allows masking of a single interrupt source so that it does not cause a smbalert. However, if one of the masked interrupt sources exceeds the limit, its associated status bit will be set in the interrupt status register.

mbalert interrupt behavior

The status of the ADT7463 can be polled, or an SMBAlert interrupt can be generated for conditions that exceed limits. When writing interrupt handler software, one must pay attention to the behavior of the smbalert output and status bits.

Figure 23 shows the behavior of the smbalert output and the "sticky" status bits. Once the limit is exceeded, the corresponding status bit is set to 1 and the status bit remains set until the error condition disappears and the status register is read. Status bits are called sticky bits because they remain set until they are read by software. This ensures that if the software periodically polls the device, events that exceed the limit are not missed. Note that the smbalert output remains low for the entire duration the read exceeds the limit, until the status register is read. This has implications for how software handles interrupts.

Handling smbalert interrupts

To prevent the system from being tied by interrupt servicing, it is recommended to handle the SMBALERT interrupt as follows:

1. Detect smbalert assertions.

2. Enter the interrupt handler.

3. Read the status register to identify the source of the interrupt.

4. Mask the interrupt source by setting the appropriate mask in the interrupt mask register (REG). 0x74, 0x75).

5. Take the appropriate action for the given interrupt source.

6. Exit Interrupt Handler.

7. Periodically poll the status register. If an interrupt status bit is cleared, reset the corresponding interrupt mask bit to 0. This will cause the smbalert output and status bits to behave as shown in Figure 24.

heat as input

When configured as an input, the user can time the assertion on the therm pin. This is useful for connecting to the prochot output of the cpu to measure system performance.

The user can also program the ADT7463 so that when the thermal pin is externally driven low, the fan runs at 100% speed. The fan runs at 100% during the time the hot sell is pulled down.

This is done by setting the boost bit (bit 2) in configuration register 3 (address = 0x78) to 1. This only works if the fan is already running (eg manual mode when the current duty cycle is above 0x00) or automatic mode when the temperature is above tmin. If the temperature is below TMIN or the duty cycle in manual mode is set to 0x00, the external pull-down heat has no effect. See Figure 25 for more information.

hot timer

The ADT7463 has an internal timer to measure the thermal assertion time. For example, the THERM input can be connected to the PROCHOT output of a Pentium 4 CPU and measure system performance. The thermal input can also be connected to the output of the trigger point temperature sensor.

The timer starts when the hot input of the ADT7463 is asserted, and stops when the pin is negated to count therm times accumulatively, that is, the timer continues to count the next therm assertion. The Therm timer continues to accumulate Therm assertion time until the timer is read (cleared on read) or reaches full scale. If the counter reaches full scale, it stops at that reading until cleared.

The 8-bit thermal timer register (REG.0x79) is designed so that bit 0 of the first therm assertion is set to 1. Once the accumulated thermal assertion time exceeds 45.52 ms, bit 1 of the thermal timer is set, bit 0 now becomes the LSb of the timer with a resolution of 22.76 ms.

Figure 26 demonstrates how the THERM timer can be asserted and negated as a hot input. Bit 0 is set on the first therm assertion detected. This bit remains set until the cumulative thermal assertion exceeds 45.52ms. At this point, bit 1 of the thermal timer is set and bit 0 is cleared.

Bit 0 now reflects timer readings with 22.76ms resolution.

When using the heat timer, please note the following:

After thermal timer read (REG.0x79):

a), the content of the timer is cleared when it is read.

b), need to clear the F4P bit (bit 5) of status register 2 (assuming that the thermal limit has been exceeded).

If the therm timer is read during a therm assertion, the following will happen:

a), the contents of the timer are cleared.

b), Bit 0 of the thermal timer is set to 1 (because a thermal assertion is occurring).

c), the thermal timer is incremented from zero.

d), if thermal limit (Reg.0x7a) = 0x00, then set the f4p bit.

Generate smbalert interrupt from therm event

The ADT7463 can generate an SMB alert when a programmable temperature limit is exceeded. This allows system designers to ignore short, infrequent therm assertions when capturing longer therm events. Register 0x7A is the THERM limit register. This 8-bit register allows the limit from 0 seconds (the first therm assertion) to be set to 5.825 seconds, then the smbalert is generated. Compare the thermal timer value with the contents of the thermal limit register If the thermal timer value exceeds the thermal limit value, set the F4P bit (bit 5) of Status Register 2 and generate an SMBALERT Note, F4P of Mask Register 2 (REG) bit (bit 5). 0x75) If this bit is set to 1, the SMBALERTs are masked, although the F4P bit of the Interrupt Status Register 2 will still be set if the thermal limit is exceeded.

Figure 27 is a functional block diagram of the thermal timer, limits and associated circuitry. Writing a value of 0x00 to the thermal limit register (Reg0x7A) causes a SMBALERT to be generated on the first THERM assertion. Once the cumulative thermal assertion exceeds 45.52 ms, a thermal limit value of 0x01 will generate a smbalert.

Configure the desired thermal behavior

1. Configure the desired pins as thermal inputs. Configuration Register 3 (REG.0x78) enables thermal monitoring. By default this is enabled on pin 14.

Setting Bit 1 of Configuration Register 4 (TH5V)

(Registration number 0x7d) Enables thermal monitoring on pin 20 (bit 1 of configuration register 3 must also be set). Pin 14 can be used as tachometer 4 .

2. Select the desired fan behavior for thermal events.

Configuration Register 3 (Reg0x78) causes all fans to run at 100% duty cycle when THERM is asserted. This allows for fail-safe system cooling. If this bit is 0, the fan operates at its current setting and is not affected by thermal events.

3. Select whether the therm event should generate a smbalert interrupt.

Mask Register 2 (Register 0x75), when set, masks SMBALERTs when the thermal limit value is exceeded. This bit should be cleared if smbalerts based on therm events are desired.

4. Select the appropriate thermal limit value. This value determines whether the smbalert is generated on the first therm assertion, or only when the cumulative therm assertion time limit is exceeded. A value of 0x00 causes a smbalert to be generated on the first therm assertion.

5 selectable thermal monitoring times.

This is how often the operating system or bios-level software checks the therm timer. For example, the bios can read the therm timer every hour to determine the accumulated therm assertion time. For example, if the total thermal assertion time is less than 22.76 ms at hour 1, greater than 182.08 ms at hour 2, and greater than 5.825 s at hour 3, this may indicate a significant reduction in system performance since heat assertions are made more frequently in hourly Base.

Alternatively, the operating system or bios-level software can set the timestamp when the system is powered on. Another timestamp can be taken if a smbalert is generated due to exceeding the thermal limit. The time difference can be calculated as a fixed thermal limit time. For example, if it takes one week to exceed the thermal limit of 2.914 s, and the next time it only takes 1 hour, it is an indication of severe system performance degradation.

Configuring the ADT7463 Thermal Pins as Outputs In addition to the ADT7463's ability to monitor therm as an input, the ADT7463 can optionally drive therm low as an output. The user can pre-program critical system thermal limits. The thermal assertion is low if the temperature exceeds the thermal limit by 0.25°C. If the temperature for the next monitoring cycle is still above the thermal limit, therm remains low. The heat is kept low until the temperature is at or below the thermal limit. Since the temperature of this channel is only measured every monitoring cycle, once THERM is asserted, it is guaranteed to remain low for at least one monitoring cycle.

The thermal pin can be configured to assert low if the remote 1, local, or remote 2 temperature thermal limit exceeds 0.25°C. The thermal limit registers are located at locations 0x6a, 0x6b, and 0x6c, respectively. Setting Bit 3 of Registers 0x5f, 0x60, and 0x61 enables the thermal output function of the Remote 1, Local, and Remote 2 temperature channels, respectively. Figure 28 shows how the THERM pin acts low as an output during a critical overtemperature condition.

Fan drive with pwm control

The ADT7463 uses pulse width modulation (PWM) to control fan speed. This relies on changing the duty cycle (or on/off ratio) of the square wave applied to the fan to change the fan speed. Using pwm to control the external circuitry needed to drive the fan is very simple. Only one nmosfet drive device is required. The specification of the MOSFET depends on the maximum current required by the fan being driven. A typical laptop fan is rated at 170mA, so SOT devices can be used where board space is a concern. In desktops, fans can typically draw 250mA to 300mA. If driving multiple fans in parallel from one PWM output or driving larger server fans, the MOSFET needs to handle higher current requirements. The only other stipulation is that the MOSFET should have gate voltage drive, VGS<3.3v, for connecting directly to PWM output pins VGS can be greater than 3.3v as long as the pull-up on the gate is connected to 5v. The MOSFET should also have low on-resistance to ensure that there is no significant voltage drop across the FET. This reduces the voltage applied to the fan and thus reduces the maximum operating speed of the fan. Figure 29 shows how to drive a 3-wire fan using PWM control.

Figure 29 uses a 10 kΩ pull-up resistor as the tachometer signal. This assumes the tach signal is coming from the open collector of the fan. In all cases, the TACH signal from the fan must be kept below 5 V to prevent damage to the ADT763. If in doubt about whether the fan you are using has an open collector or totem pole tachometer output, use one of the input signal conditioning circuits shown in the fan speed measurement section of the datasheet.

Figure 30 shows a fan driver circuit using npn transistors such as the generic mmbt2222. While these devices are inexpensive, they tend to have lower current handling capabilities and higher on-resistance than MOSFETs. When choosing a transistor, care should be taken to ensure that it meets the current requirements of the fan.

Make sure to choose a base resistor that saturates the transistor when the fan is powered up.

Drive two fans from PWM3

Note that the ADT7463 has four tachometer inputs available for fan speed measurement, but only three PWM drive outputs. If a fourth fan is used in the system, it should be paralleled with the third fan, driven from the PWM3 output. Figure 31 shows how to drive two fans in parallel using low-cost NPN transistors.

Figure 32 is the equivalent circuit using the ndt3055l mosfet. Note that since the mosfet can handle up to 3.5A, it's just a matter of putting another fan directly in parallel with the first.

The drive circuits for the transistors and FETs should be carefully designed to ensure that the PWM pins do not require current sources and that they sink more than the 8mA maximum current specified on the datasheet.

Drive up to three fans from PWM2

The fan's RPM measurement is synchronized to a specific PWM channel, eg RPM1 is synchronized to PWM1. Both Tach 3 and Tach 4 are synchronized with PWM3, so PWM3 can drive 2 fans. Alternatively, PWM2 can be programmed to synchronize tachometer 2, tachometer 3, and tachometer 4 to the PWM2 output. This allows PWM2 to drive two or three fans. In this case, the drive circuit is shown in Figure 31 and 32 registers The sync bit in 0x62 enables this feature.

<4> (Sync) Enhanced Acoustics REG 1 (0x62) sync=1 to synchronize TACH2, TACH3 and TACH4 to PWM2.

Drives 2-wire fans

Figure 33 shows how a 2-wire fan connects to the ADT7463. This circuit allows the speed of a 2-wire fan to be measured even if the fan does not have a dedicated speed signal. The series resistor rsense in the fan circuit converts the fan commutation pulses to voltage. This is AC coupled to the ADT7463 through a 0.01µf capacitor. On-chip signal conditioning allows precise monitoring of fan speed. The selected RSENSE value depends on the programmed input threshold and the current to the fan. For the fan about 200 mA, a value of 2 psi is appropriate when the threshold is programmed to 40 mV. For fans that draw more current, such as larger desktop or server fans, rsense may lower the same programmed threshold. The lower the programmed threshold, the better, because the more voltage developed on the fan, the faster the fan spins. Figure 34 shows a typical sense waveform for the tach/AIN pin. The most important thing is that the amplitude of the voltage spike (negative or positive) exceeds 40 mV. This way the fan speed can be determined reliably.

Arrangement of 2- and 3-wire fans

Figure 35 shows how to lay out the common circuit for 2-wire and 3-wire fans. Depending on whether a 2-wire or 3-wire fan is used, some components will not populate.

Tachometer input

Pins 9, 11, 12, and 14 are open-drain tachometer inputs for fan speed measurement.

The signal conditioning in the ADT7463 adjusts the slow rise and fall times of the typical output of the fan tachometer with a maximum input signal range of 0 V to 5 V, even if VCC is less than 5 V. If these inputs are supplied from fan outputs in excess of 0 V to 5 V, resistive attenuation of the fan signal or diode clamps must be included to keep the inputs within acceptable limits.

Figures 36a to 36d show circuits for the most common fan tachometer outputs. If the fan tachometer output has a resistive pull-up to VCC, it can be connected directly to the fan input, as shown in Figure 36A.

If the fan output is resistively pulled up to 12V (or other voltages greater than 5V), the fan output can be clamped with a zener diode, as shown in Figure 36b. The Zener diode voltage should be selected so that it is greater than the VIH of the tachometer input but less than 5V, allowing the voltage tolerance of the Zener. A value between 3 V and 5 V is suitable.

If the fan has a strong pullup (less than 1KΩ) to 12V or a composite output, a series resistor can be added to limit the zener current, as shown in Figure 36C. Alternatively, resistive attenuators can be used, as shown in Figure 36D.

The choice of right 1 and r2 should ensure that:

The input resistance of the fan input to ground is nominally 160 kΩ, so this should be taken into account when calculating the resistance value. Suitable values for R1 and R2 are 100 kΩ and 47 kΩ when the pull-up voltage is 12 V and the pull-up resistor is less than 1 kΩ. This produces a high input voltage of 3.83 volts.

Fan speed measurement

The fan counter does not directly count the fan tachometer output pulses because the fan speed may be less than 1000 rpm and it will take several seconds to accumulate a fairly large and accurate count. Instead, the period of the fan speed is measured by gating a 90 kHz on-chip oscillator to the input of a 16-bit counter for N cycles of the fan speed output (Figure 37), so the accumulated count is actually the same as the fan speed period proportional to the fan speed.

n, the number of pulses counted is determined by the setting of register 0x7b (one fan pulse per revolution register). This register contains two bits per fan, allowing one, two (default), three or four tach pulses to be counted.

Fan Speed Measurement Register

The fan tachometer reads as a 16-bit value consisting of 2 bytes read from the ADT7463.

Rule: 0x28 TACH1 low byte = 0x00 default value

Rule: 0x29 TACH1 high byte = 0x00 default value

Rule: 0x2A TACH2 low byte = 0x00 default value

Rules: 0x2B TACH2 high byte = 0x00 default register 0x2C TACH3 low byte = 0x00 default value

Rule: 0x2D TACH3 high byte = 0x00 default value

rule:. 0x2E TACH4 low byte = 0x00 default value

Rule: 0x2F TACH4 high byte = 0x00 default value

Read fan speed from ADT7463

If you are measuring fan speed, you need to read 2 registers per measurement. The low byte should be read first. This causes the high byte to be frozen until both the high and low byte registers have been read. This prevents false tachometer readings.

The fan tachometer read register reports the 11.11 microsecond period clock (90 microseconds) gated to the fan tach counter from the rising edge of the first fan tach pulse to the rising edge of the third fan tach pulse (assuming two pulses per revolution are counting) kHz oscillator). Since the device is basically measuring fan RPM cycles, the higher the count, the slower the fan is actually running. A 16-bit fan tachometer reading of 0xFFFF indicates that the fan has stalled or is running very slowly (<100 rpm).

Since the actual fan speed cycle is being measured, exceeding the fan speed limit of 1 will set the appropriate status bits and can be used to generate the smbalert.

Fan Speed Limit Register

The Fan Speed Limit Register is a 16-bit value consisting of two bytes.

Rule: 0x54 TACH1 minimum low byte = 0xFF default value

Rule: 0x55 TACH1 minimum high byte = 0xFF default value

Rule: 0x56 TACH2 minimum low byte = 0xFF default value

Rule: 0x57 TACH2 minimum high byte = 0xFF default value

Rule: 0x58 TACH3 minimum low byte = 0xFF default value

Rule: 0x59 TACH3 minimum high byte = 0xFF default value

Rule: 0x5A TACH4 minimum low byte = 0xFF default value

Rule: 0x5B TACH4 minimum high byte = 0xFF default value

Fan speed measurement rate

Fan tachometer readings are usually updated every second. Configuration Register 3 (REG.0x78), when set, updates the fan tachometer reading every 250ms.

If any fan is not driven by a pwm channel, but powered directly by 5v or 12v, its associated dc bit should be set in configuration register 3. This allows fans connected directly to the DC power source to take continuous tachometer readings.

Calculate fan speed

Assuming the fan has two pulses/revolution (two pulses/revolution is measured), the fan speed is calculated by the fan speed (rev/min) = (90000 60) / fan speed reading, where fan speed reading = 16-bit fan tachometer reading.

Example: TACH1 high byte (REG 0x29) = 0x17 TACH1 low byte (REG 0x28) = 0xFF What is the RPM of fan 1?

Fan 1 RPM reading = 0x17FF = 6143 Decimal RPM = (F 60) / Fan 1 RPM reading RPM = (90000 60)/6143 Fan RPM = 879 RPM

Fan pulses per revolution

Different models of fans can output 1, 2, 3 or 4 speed pulses per revolution. Once the number of fan speed pulses is determined, it is programmed into the Fan Pulses Per Revolution Register (Reg 0x7b) for each fan. Alternatively, this register can be used to determine the number or pulses/speed of output for a given fan. Determine the correct pulse/tach value by plotting the fan speed measurements at 100% RPM with different pulse/tach settings, the smoothest graph with the least ripple.

Fan Pulse Register per Revolution

<1:0> Fan 1 default = 2 pulses per revolution.

<3:2> Fan 2 default = 2 pulses per revolution.

<5:4> Fan 3 default = 2 pulses per revolution.

<7:6> Fan 4 default = 2 pulses per revolution.

00 = 1 pulse per revolution.

01 = 2 pulses per revolution.

10 = 3 pulses per revolution.

11 = 4 pulses per revolution.

2-Wire Fan Speed Measurement

The ADT7463 is capable of measuring the speed of a 2-wire fan, i.e. a fan without a tachometer output. To do this, the fan must be connected as shown in the fan driver circuit section of the datasheet. In this case, the tachometer input needs to be reprogrammed as an analog input, AIN.

Configuration Register 2 (Register 0x73)

Bit 3 (AIN4) = 1, pin 14 is reconfigured to measure the speed of a 2-wire fan using an external sense resistor and coupling capacitor.

Bit 2 (AIN3) = 1, pin 9 is reconfigured to measure the speed of a 2-wire fan using an external sense resistor and coupling capacitor.

Bit 1 (AIN2) = 1, pin 12 is reconfigured to measure the speed of a 2-wire fan using an external sense resistor and coupling capacitor.

Bit 0 (ain1) = 1, pin 11 is reconfigured to measure the speed of a 2-wire fan using an external sense resistor and coupling capacitor.

AIN switching threshold

After configuring the tachometer input as the ain input for 2-wire measurements, the user can select the sensing threshold for the ain signal.

Configuration Register 4 (Register 0x7 Day) <3:2> Air These two bits define the input threshold for the 2-wire fan speed measurement.

00=20mV

01=40mV

10=80mV

11=130mV

fan rotation

The ADT7463 has a unique fan rotation feature. It spins the fan with a 100% PWM duty cycle until two tachometer pulses are detected at the tachometer input. Once two pulses are detected, the PWM duty cycle will reach the expected operating value, eg 33%. The advantage is that the fans have different rotational characteristics and require different times to overcome inertia. The ADT7463 just runs the fan fast enough to overcome inertia and spin up more quietly than the fan programmed to spin for a given spin time.

Fan startup timed out

To prevent spurious interrupts when the fan starts up (because it is below operating speed), the ADT7463 includes a fan start time-out function. This is the time limit that allows two tachometer pulses to be detected while spinning up. For example, if a 2 second fan start timeout is selected and no tachometer pulses occur within 2 seconds of starting a spin, a fan failure will be detected and marked in the interrupt status register.

<2:0> of the PWM1 configuration (Register 0x5c) rotates these bits to control the startup timeout of PWM1.

000=No startup timeout

001=100ms

010=250ms (default)

011=400ms

100=667 milliseconds

101=1 second

110=2 seconds

111=4 seconds

<2:0> of the PWM2 configuration (register 0x5d) rotates these bits to control the start-up timeout of PWM2.

000=No startup timeout

001=100ms

010=250ms (default)

011=400ms

100=667 milliseconds

101=1 second

110=2 seconds

111=4 seconds

Rotating these bits <2:0> in the PWM3 configuration (Register 0x5e) controls the startup timeout for PWM3.

000=No startup timeout

001=100ms

010=250ms (default)

011=400ms

100=667 milliseconds

101=1 second

110=2 seconds

111=4 seconds

Disable fan startup timeout

While fan start makes fan spin quieter than static time spin, there is an option to use a fixed spin rise time. Bit 5 (FSPDIS) = Configuration Register 1 (Reg0x40) disables acceleration for both tachometer pulses. Instead, the fan spins for a fixed time selected in registers 0x5C to 0x5E.

PWM logic state

The PWM output can be programmed to be 100% duty cycle high (no inversion) or 100% duty cycle low (inversion).

<4> Investment of PWM1 configuration (register 0x5C) 0 = 100% PWM duty cycle logic high 1 = 100% PWM duty cycle logic low

<4> Investment of PWM2 configuration (register 0x5D) 0 = 100% PWM duty cycle logic high 1 = 100% PWM duty cycle logic low

<4> Investment in PWM3 configuration (register 0x5e) 0=100% PWM duty cycle logic high 1=100% PWM duty cycle logic low

PWM drive frequency

The PWM drive frequency registers 0x5f to 0x61 can be adjusted according to the application to configure the pwm frequency for pwm1 to pwm3 respectively.

PWM1 Frequency Register (Register 0x5f to 0x61) <2:0> Frequency 000 = 11.0 Hz

001=14.7 Hz

010=22.1 Hz

011=29.4 Hz

100 = 35.3 Hz (default)

101 = 44.1 Hz

110 = 58.8 Hz

111 = 88.2 Hz

Fan speed control

The ADT7463 can control fan speed using two different modes. The first is the automatic fan speed control mode. In this mode, once the initial parameters are set, the fan speed will change automatically with temperature without CPU intervention. The benefit of this is that in the event of a system hang, the user can be assured that the system will not overheat. Automatic fan speed control includes a feature called dynamic TMIN calibration. This feature reduces the design effort required to program an automatic fan speed control loop. For more information and how to program an automatic fan speed control loop and dynamic tmin calibration.

Manual fan speed control

The ADT7463 allows manual adjustment of the duty cycle of any PWM output. This is useful if the user wishes to change the fan speed in software or adjust the PWM duty cycle output for testing purposes. Bits<7:5> of Registers 0x5c through 0x5e control the behavior of each pwm output.

PWM Configuration (Register 0x5c to 0x5e) <7:5> bhvr111 = Manual Mode

Once under manual control, each PWM output can be manually updated by writing to registers 0x30 to 0x32 (PWMX current duty cycle registers).

Programming the PWM Current Duty Cycle Register The PWM Current Duty Cycle Register is an 8-bit register that allows the PWM duty cycle of each output to be set from 0% to 100% in 0.39% steps.

The value programmed into the pwmmin register is given by: DecimalValue() = pwmmin 0.39

Example 1: For a 50% PWM duty cycle, value (decimal) = 50/0.39 = 128 decimal value = 128 decimal or 0x80. Example 2: For a PWM duty cycle of 33%, value (decimal) = 33/0.39 = 85 decimal value = 85 decimal or 0x54.

PWM Duty Cycle Register

Rule: 0x30 PWM1 duty cycle = 0xFF (100% default)

Rule: 0x31 PWM2 duty cycle = 0xFF (100% default)

Rule: 0x32 PWM3 duty cycle = 0xFF (100% default)

By reading the PWMx current duty cycle registers, the user can track the current duty cycle on each PWM output, even when the fan is running in automatic fan speed control mode or sound enhancement mode.

Operates from a 3.3V backup supply

The ADT7463 is specifically designed for use with a 3.3V backup power supply in computers that support S3 and S5. In these states, the core voltage of the processor is reduced. If dynamic tmin mode is used, reducing the core voltage of the processor will change the temperature of the cpu and change the dynamic characteristics of the system under dynamic tmin control. Also, when monitoring therm, the therm timer should be disabled in these states.

Dynamic tmin Control Register 1 (Register #0x36) <1> VCCPlo = 1, when the supply is powered by 3.3 V STBY and the VCCP voltage drops below the VCCP lower limit, the following occurs:

• Set Status Bit 1 (VCCP) in Status Register 1.

• If enabled, SMBALERT is generated.

• Disable thermal monitoring. The heat timer should hold its value until the S3 or S5 state.

• Disable dynamic tmin control. This prevents tmin from being adjusted due to s3 or s5 state.

• Prevents the ADT7463 from entering a shutdown state.

Once the core voltage VCCP exceeds the lower limit of VCCP, everything will be re-enabled and the system will resume normal operation.

Note that these voltage channels set status bits or generate smbalerts as other voltages may drop or turn off in low power states. It is still necessary to mask these channels before entering a low power state using the interrupt mask register. The mask bits can be cleared when exiting a low-power state. This prevents the device from generating unwanted SMB alerts in low power states.

XOR tree test mode

The ADT7463 includes an XOR tree test mode. This mode is useful for in-circuit test equipment for board level testing. Opens or shorts on the system board can be detected by applying stimuli to the pins contained in the XOR tree. Figure 39 shows the signals performed in the XOR tree test mode.

Boot default

By default, the ADT7463 does not monitor temperature and fan speed at power-up. Temperature and fan speed can be monitored by setting the start bit (bit 0, address 0x40) in configuration register 1 to 1. The fan runs at full speed when powered on. This is because the bhvr bits (bits 7:5) in the pwmx configuration register are set to 100 by default (fan running at full speed).