Features: 256 Kbit Ferroelectric Random Access Memory (F-RAM) logically organized as 32k x 8 high endurance 100 trillion (1014) read/write 151 year data retention period (see data retention and endurance table) nodelay 8482 ; write In-page mode operation Advanced high-reliability ferroelectric process SRAM compatible with industry standard 32 K×8 SRAM pins 70 ns access time, 140 ns cycle time better than battery-backed SRAM modules No battery issues Monolithic reliability True surface mount Mounting solution with no rework steps Suitable for moisture, shock and vibration Negative voltage overshoot resistance : –40°C to +85°C; Packaging: 28-pin Small Outline Integrated Circuit (SOIC) package 28-pin Thin Small Outline Package (TSOP) Type I 32-pin Thin Small Outline Package (TSOP) Type I Compliant with Restriction of Hazardous Substances (RoHS)

Function overview: FM28V020 is a 32K×8 non-volatile memory, which can read and write similar to standard SRAM. Ferroelectric random number access memory, or F-RAM, is non-volatile, which means that data is retained after a power outage. It has been battery-backed SRAM (BBRAM) for 151 years while eliminating reliability issues, functional flaws and system design complexity. Fast write timing and high write endurance make f-ram superior to other types of memory. The FM28V020 operates similarly to other RAM devices. Therefore, it can be used as a standard SRAM in the system. The read and write cycles can be triggered by ce or by changing the address. F-RAM memory is non-volatile due to its unique ferroelectric memory. process. These features make the FM28V020 ideal for applications requiring frequent or fast non-volatile memory writes. The device is available in 28-pin SOIC, 28-pin TSOP I, and 32-pin TSOP I surface mount packages. Device specifications are over the industrial temperature range of -40°C to +85°C.

Device Operation The FM28V020 is logically byte-range F-RAM memory organized as 32768 x 8 and uses an industry standard parallel interface. All data written to the component is immediately non-volatile. The device provides page-mode operation, and the memory operator accesses 32,768 memory locations, each with 8 data bits via a parallel interface. The f-ram array is organized into eight blocks, each with 512 rows and eight columns each allowing quick access to locations in page mode. When the initial address is latched by the falling edge of CE, there is no need to access subsequent column locations to toggle CE. When CE is de-high voltage, the pre-charge starts immediately before entering each write must toggle we pin operation. Write data is stored in an immediate array of non-volatile memory, a feature unique to F-RAM called Nordley writes. READ OPERATIONS A read operation begins with the falling edge of CE. A falling edge of ce causes the address to be latched and initiates a memory read cycle if we are high. Data is available to the bus after the access time. When the access is done when the address is locked, a new random location access (different row) may start while CE is still low. The cycle time for the smallest random address is trc. Note that, unlike SRAM, the CE boot access time of the FM28V020 is longer than the address access time. When oe is asserted low, the fm28v020 will drive the data bus and meet the memory access time. If the memory access time is met, the data bus will be available with valid data. If OE is asserted before completing the memory access, the data bus will not be driven until valid data is available. This feature works by eliminating transients caused by invalid data being driven to the bus. when? OE is de-configured high and the data bus will remain in the HI-Z state.

Write operation In the FM28V020, the interval between writing and reading is the same. This FM28V020 supports both CE and WE controlled write cycles. In both cases, the address is locked on the falling edge of ce. In a CE-controlled write operation, the WE signal starts a memory cycle. That is, when the device is activated while the chip is enabled, the device starts a memory cycle in write mode in this case. The FM28V020 will not drive the data bus regardless of the state of OE as long as we are low. Input data must be valid when CE is de-overestimated. After a we control the write, the memory loop starts from the falling edge and our signal about CE will fall after a while. So the memory loop starts with a read if the run experience is low; however, when we are asserted low, it will be hi-z. The CE and WE controlled write timings show that the data bus is in a hi-Z state when the chip is being written to before the desired setup time. Although this may seem like a medium voltage, it is recommended that all DQ pins meet minimum VIH/VIL operating levels. A write access to the array starts the memory loop. Write accesses are on the rising edge of US or CE, whichever comes first. A valid handwriting operation requires the user to meet the access time specification before the data set time in WE or CE leaves the indication on write access (rising edge of WE or CE).

Unlike other non-volatile memory technologies, it has no write operation latency to F-RAM because the underlying memory is the same, and the user does not experience delays on the bus. The entire memory operation happens in a single bus round-robin data polling, a method for eeprom The technique does not need to determine whether the write is complete. Page Mode Operation The FM28V020 allows users to quickly access row elements with eight column address locations per row. The address inputs a2–a0 define the column address. Accessed access can start from anywhere within the row. Column location CE pins can be accessed without toggling. For fast access reads, the column address inputs A2–A0 can be changed to new values after the first data byte is driven to the bus. Then, a new data byte is driven to the DQ pin. For fast access writes, the first write pulse defines the first write access. When CE is low, subsequent write pulses provide page mode write entry with the new column address. Precharge Operation A precharge operation is an internal condition where the memory state is ready for a new access. Precharge is initiated by the user by driving the CE signal high and it must be left high for at least the minimum precharge time, tpc. Precharge can also be activated by changing the address above, A14–A3 are currently being accessed. The device automatically detects a higher order address change and begins a precharge operation. Locked, new read data within the TAA address has a valid speed random address which can be tRC and tWC respectively.

SRAM Insert Replacement FM28V020 is designed as standard asynchronous SRAM. The device does not need the CE to switch for each new address. CE may remain low indefinitely when VDD is applied. When CE is low, the device automatically detects the address change and starts a new access. It also allows running page mode at speeds up to 15 MHz. A typical application is shown in the picture which shows a pull-up resistor on CE that keeps the pin high cycling on power up, assuming a tri-state condition on the MCU/MPU pins during reset. The pull-up resistor value should be chosen to ensure that the CE pin tracks VDD to a high enough value so that current draw is not a problem when CE values are low. 10-K resistor is 330 microamps when ce is low and vdd=3.3v.

Note that if CE is tied to ground, the user must ensure that we are not low during a power-up or power-down event. If both CE and US are during a low power cycle, the data will be corrupted. The graph shows that we have a pull-up resistor on us, during a power cycle, assuming the MCU/MPU pins are in a reset condition. The pull-up resistor value should be chosen to ensure that the we pin tracks vdd value is high enough so that when we are low, current consumption is not an issue. 10-k When we are at low voltage and VDD=3.3V, the resistor dissipates 330uA.

For applications that require the lowest power consumption, the CE signal should only be active during memory accesses. Expired to an external pull-up resistor, which will draw some supply current when CE is low and when CE is high, the device no longer draws more than the maximum standby current ISB. ce switching to low on every address access is perfectly acceptable in the FM28V020. The Endurance FM28V020 can be accessed at least 1014 times – read or write. f-ram memory goes through a read and restore mechanism. Therefore, on a row basis. The f-ram architecture is based on row and column addresses defined by row A14-3 and column by A2-a0. The array is organized into 4 rows of 8 rows per byte. If a single byte or all eight bytes are read or written. Each byte in the endurance calculation if addressing is inherently contiguous. The user has the option to write CPU instructions and run them from a certain address space. Table 1 shows the calculation of an endurance 256-byte repeating loop, which includes the starting address, seven-page mode access, and a CE precharge. The number of bus clock cycles required to complete an eight-byte read transaction is 1+7+1 or 9 clocks. The whole loop makes each byte go through only one persistence period. The read and write persistence of f-ram is virtually unlimited.