General Description The W29C020C is a 2Mbit, 5V CMOS flash memory consisting of 256K x 8 bits. The device can be written (erased and programmed) to the system with a standard 5V power supply. 12 volt VPP is not required. The unique cell structure of the W29C020C results in fast write (erase/program) operations with extremely low current consumption compared to other similar 5V flash memory products. The device can also be programmed (erased and programmed) by using a standard eprom programmer.
Function

Single 5V Write (Erase and Program) Operation (Erase/Program) Cycle: 10ms (Max) - Valid Byte Write (Erase/Program) Cycle: 39µs - Optional Software Protected Data write

Fast Chip Erase Operation: 50ms, Two 8KB Boot Blocks w/ Lock, Whole Chip Cycle: 10K (typ) Software and Hardware Data Protection, Low Power Consumption - Active Current: 25mA (typ) – Standby Current : 20µA (typ) Auto Write (Erase/Program) Timing, Internal VPP Generation, End of Write (Erase/Program) Detection - Toggle Bits - Data Polling, Latch Address and Data, All Inputs and Outputs are directly TTL compatible, Jedec standard byte wide pins, available in packages: 32-pin 600 mil DIP, 32-pin TSOP and 32-pin PLCC

Functional Description Read Mode The read operation of the W29C020C is controlled by CE and OE, both of which must be low for the host to get data from the output. CE is used for equipment selection. When CE is high, the chip is deselected and only the backup power is consumed. OE is the output control and is used to get data from the output pins. When CE or OE is high, the data bus is in a high impedance state. See Reading Loop Timing Waveforms for more details.
page write mode
W29C020C writes (erase/program) in page units, then the entire page of data must be loaded into the device. Any unloaded bytes will be erased to "ff hex" during a page write operation.
The write operation is initiated by forcing CE and WE low and OE high. The write process consists of two steps. Step 1 is the byte load loop in which the host writes to the device's page buffer. Step 2 is an internal write (erase/program) cycle during which data in the page buffer is simultaneously written to the memory array for non-volatile storage.
During a byte load cycle, the address is locked by the falling edge of CE or WE, whichever occurs last. Data is locked by the rising edge of CE or WE, whichever occurs first. seconds byte load cycle time (tblc) to load the second byte into the page buffer, the w29c020c will remain in the page load cycle. Additional bytes can then be loaded consecutively. If no additional bytes are loaded into page buffers a7 through a17 at the specified page address, the page load loop will terminate and the internal write (erase/program) loop will begin. All bytes loaded into the page buffer must have the same page address. a0 to a6 specify byte addresses in the page. Bytes can be loaded in any order; sequential loading is not required. During an internal write cycle, all data in the page buffer is written to the memory array at the same time. Before completing the internal write cycle, the host is free to perform other tasks, such as fetching data from elsewhere in the system, in preparation for writing the next page.
The software protected data writing device offers optional software protected data writing approved by jedec. When this scheme is enabled, any write operation requires a three-byte command sequence (send specific data to a specific address) before the data load operation. The three-byte load command sequence starts the page load cycle, otherwise the write operation will not be activated. This write scheme provides optimal protection against accidental write cycles, such as those triggered by noise during system power-up and power-down. The W29C020C is shipped with software data protection enabled. To enable the software data protection scheme, execute a three-byte command cycle at the beginning of the page load cycle. The device will then enter software data protection mode and any subsequent write operations must occur before the three-byte command sequence loops. Once enabled, software data protection will remain enabled unless a disable command is issued. Power transitions will not reset the software data protection feature. To reset the device to unprotected mode, a 6-byte command

Order is required. For information on specific codes, see Software Data Protection Command Codes in the Operating Modes table. The integrity of the data stored in the W29C020C is also protected by the following hardware:
(1) Noise/fault protection: WE pulses of duration less than 15 nS will not initiate a write cycle.
(2) VDD power up and down detection: When VDD is less than 2.5V, write operation is prohibited.
(3) Write inhibit mode: Forcing oe low, ce high or we high will inhibit the write operation. This prevents accidental writes during power up or power down.
(4) VDD power-up delay: When VDD reaches its sense level, the device will automatically time out for 5ms before any write (erase/program) operation.
Chip Erase Mode Boot Block Operation This device has two boot blocks (8k bytes each) that can be used to store boot codes. One of them is in the first 8k bytes and the other is in the last 8k bytes of memory. By using a seven-byte command sequence, the first or last 8k of memory can be set as the boot block.
For specific codes, see Boot Block Lock Enable Command Code After this feature is set, the data of the specified block cannot be erased or programmed (program lock); other memory locations can be changed by normal programming methods. After the boot block program lock feature is enabled, The chip erase function will be disabled. In order to detect whether the boot block function is set on two 8K blocks, the user can execute a 6-byte command sequence: enter product identification mode (for specific codes, see Command Code Identification/Boot Block Lock Detection) and then start from address "00002 hex" (the first 8K bytes) or "3FFF2 hex" (the last 8K bytes) read if the output data is "FF hex", start the block programming lock function; if the output data is "FE hex", turn off the lock function, Blocks can be programmed.
To return to normal operation, execute a three-byte command sequence to exit identification mode. For specific codes, see Command Codes for Identity/Boot Block Lock Detection.
Data Polling (DQ7) - Write Status Detection The W29C020C includes a Data Polling function to indicate the end of a write cycle. When the W29C020C is in an internal write cycle, any attempt to read DQ7 from the last byte loaded in a page/byte load cycle will receive the complement of the real data. DQ7 will display the real data once the write cycle is complete.

Toggle Bit (DQ6) - Write Status Detection In addition to data polling, the w29c020c provides another method of determining the end of a write cycle. During an internal write cycle, any successive attempts to read the dq6 will result in alternating 0s and 1s. Toggling between 0 and 1 will stop when the write cycle is complete. The device can then proceed to the next operation.
Product ID Product ID Action Outputs Manufacturer Code and Device Code Programming the device automatically matches the device to its appropriate erasing and programming algorithms.
Manufacturer and device codes are accessible through software or hardware operations. In software access mode, the product identification can be accessed using a six-byte command sequence. The output read from address "00000 hex" is the manufacturer code "DA hex". The output read from address "00001 hex" is the device code "45 hex". Product identification operations can be terminated by a three-byte command sequence.
In hardware access mode, access to Product ID is activated by forcing CE and OE low, WE high, and boosting A9 to 12 volts.