Features

Remote temperature sensor: ±2°C accuracy, 0.125 °C resolution; Local temperature sensor: ±2°C accuracy, 0.125°C resolution; PWM controller; PWM frequency: 10Hz to 40kHz duty Ratio: 0% to 100%, 8-bit; Automatic fan speed control loop; SMBus interface; Power supply: 2.7V to 5.5V; Package (green): QSOP-16 (4mm x 5mm); RoHS compliant.

application

Notebook and desktop computers; network servers; telecommunications equipment; PC-based equipment; DLP and LCD projectors.

illustrate

The AMC6821 is an intelligent temperature monitor and pulse width modulation (pwm) fan controller. It is designed for noise-sensitive or power-sensitive applications that require active system cooling. Using low-frequency or high-frequency pulse width modulated signals, this unit can simultaneously drive fans, monitor remote sensor diode temperature, and measure and control fan speed to make it Work at the lowest possible speed to reduce noise.

AMC6821 has three fan control modes: auto temperature fan mode, software speed mode and software DCY mode. Each mode controls the fan to speed up by changing the duty cycle of the PWM output. The automatic temperature fan mode is an intelligent, closed-loop control that optimizes the fan speed according to user-defined parameters. This mode allows the AMC6821 to operate as a standalone device without CPU intervention; the fans can continue to be controlled (based on temperature measurements) even if the CPU or system locks up. The software speed mode is the second closed loop control. In this mode, the AMC6821 regulates the PWM output to keep the fan speed consistent at a user-specified target value; that is, the device acts as a fan speed regulator. Software RPM mode can also be used to allow the AMC6821 to operate as a standalone device. This third mode, software dcy, is open loop. In software DCY mode, the PWM duty cycle is set directly by writing the value to the device. The AMC6821 has a programmable SMBAlert for indicating error conditions and a dedicated fan fault output to indicate fan failure. The THERM pin is a failsafe output for overtemperature conditions that can be used to limit the CPU clock. Also, the OVR pin indicates that the temperature limit is exceeded. All alarm thresholds are set via device registers. The AMC6821 is available in the Qsop-16 software package.

Typical features

At TA=+25°C and VDD=5V unless otherwise noted.

The AMC6821 communicates via the Serial System Management Bus (SMBus) The AMC6821 connects to this bus as a slave device under the control of the bus master. The AMC6821 has a 7-bit serial bus address that can be programmed by properly connecting address pins A0 and A1. Table 2 shows the selection of the slave address for the AMC6821. The address select pins should be connected directly to VDD or GND. For NC conditions, they should be disconnected from the smallest tracking capacitance. Note that the address is only checked on reset or power on.

letter of agreement

The AMC6821 uses four standard SMBus protocols: send bytes, receive bytes, write bytes, and read bytes. All other operations result in undefined results. Repeated starts are not allowed during bit read.

The first register is the register that sends the first data byte The next register is the second register If the bus master continues to clock data out after reading the last location (0x3f), the value 0x00 will be sent until Operation stopped.

The AMC6821 is completely controlled by registers. All registers are 8 bits. The AMC6821 has an address pointer register; the value of the address pointer register determines which register is to be written or read. To write data to or read data from a device register, the address pointer register must be set correctly. Data can then be written to or read from this register. Commands issued by the bus master always contain the initial value of the address pointer register.

In a send byte operation, the bus master writes the address of the specified device register into the address pointer register.

In a receive byte operation, the bus master reads data from the device register addressed by the address point register.

In a write byte operation, the bus master sets the address pointer register to the address of the specified device register, and then writes 8-bit data into it. In a read byte operation, the smbus master first sets the address pointer register to the address of the specified device register. address, and then read 8 bits of data from it.

In a write multibyte operation, the address pointer of the AMC6821 is incremented by "1" after writing data until the last register address (0x3f) is reached. If the host continues to transfer data to the amc6821 after writing the last location, all data will be ignored until the operation is stopped. When reading multiple bytes, the AMC6821's address pointer is incremented by "1" after transferring data until it reaches the last register address (0x3F). If the host continues to time data after reading the last position, it will send the value 0x00 until the operation stops.

SMBus Alert Response Address (ARA)

The alert response address is a function of the SMBus device that allows the interrupting device to identify itself to the host when multiple devices issue interrupts at the same time. The smbalert pin is an open-drain interrupt output pin. When the AMC6821 issues an interrupt request, the following process occurs:

1. SMBALERT is pulled low.

2. The bus master sends the alarm response address or ARA (ARA=0001100) and starts the read operation, as shown in Table 10.

3. AMC6821 responds to ARA by sending back the slave address. The slave address is placed in the 7 most significant bits of the byte; the last bit is "0".

4. The host receives the AMC6821 slave address and starts the interrupt service.

5. If multiple devices pull the smbus low, during a slave address transfer, the highest priority (lowest slave address) device wins communication rights through standard arbitration (see smbus specification version 2.0 for details).

6. In order to satisfy the interrupt request of the AMC6821, the host must read the status register. Most of the interrupt source bits in the status register are cleared after reading the status register and re-acknowledge if the error condition still exists in the next monitoring cycle. SMBALERT will only clear when the interrupt has been resolved.

Power-on reset and start-up operation

After power-up, all registers are set to power-up defaults. The device does not perform any monitoring functions until the start bit ("1") of configuration register 1 is set. No detection is performed until the first monitoring cycle is completed and all measurement data registers (such as remote and local temperature data registers and tachometer data registers) are updated with new measurement values before the first monitoring and detection cycle is completed , no interrupt signal will be generated. This process avoids any false alarms caused by the power-on defaults.

After power is applied, perform the fan startup procedure. At the end of the acceleration, the duty cycle of the PWM driver is adjusted to 33% (see the Fan Spinning section for details). The device state after a software reset is similar to a power-on reset.

analog to digital converter

The AMC6821 has an 11-bit on-chip analog-to-digital converter (ADC), as shown in Figure 11. This ADC converts the analog input to digital format and the analog input passes through the front-end signal conditioning circuit to remove noise. Then the signal converted by adc. To further reduce the effect of noise, digital filtering is performed by averaging the results over 32 measurement cycles. After digital filtering, the latest results are stored in the temperature data registers (low and high bytes) in 2's complement format when the configuration register is cleared. The ADC stops when the start bit of 1 ("0") and runs when the start bit = 1.

Temperature Sensor

The AMC6821 has an integrated temperature sensor (shown in Figure 12) to measure the ambient temperature, and a remote diode sensor (such as a Pentium thermal diode) to measure the external (CPU) temperature measurement relies on the operation of the semiconductor junction at a fixed current level The forward voltage (vbe) of a characteristic diode depends on the current through it and the ambient temperature. When the diode is operated at two different currents, I1 and I2, the change in VBE is shown in Equation 1:

where: k is the Boltzmann constant, q is the charge of the carrier, T is the absolute temperature in degrees Kelvin, and n is the ratio of the two currents.

Remote sensing transistors can be substrate transistors built into microprocessors (such as Pentium IV) or discrete small-signal transistors. This architecture is shown in Figure 13. Internal bias diodes bias the input terminals towards ground to prevent ground noise from interfering with the measurement. External capacitors (up to 1000pF) can be placed between In+ and In- to further reduce interfering noise.

The analog sensing signal is pre-processed by a low-pass filter and signal conditioning circuit, and then digitized by the ADC. The resulting digital signal is further processed by a digital filter and processing unit. The final result is stored in the local temperature data register and the remote temperature data register, respectively. . Eight msbs are stored in the corresponding Temp DATA HByte registers and three lsbs are stored in the Temp DATA LByte registers.

The format of the final result is two's complement; see Table 11. It should be noted that this unit measures a temperature range of -40°C to +125°C, although the code indicates a temperature range of -128°C to +127°C.

Series Resistance Elimination

The parasitic resistance to and from the input of the AMC6821 (in series with the remote diode) is caused by a variety of factors, including the trace resistance and trace length of the printed circuit board (PCB). This series resistance is shown as a temperature offset in the remote sensor temperature measurement, with an error of more than 0.45° per ohm. The CAMC6821 is implemented with TI's patented technology, which automatically eliminates the effect of this series of resistances, providing more accuracy without requiring the user to describe the resistance. With this technique, the AMC6821 is able to reduce the effect of series resistance to typically less than 0.0025°C per ohm.

Read temperature data

It is important to note that temperature can be read as an 8-bit value (with a resolution of 1°C) from the Temperature Data Byte register, or an 11-bit value (with a resolution of 1°C) from the Temperature Data Byte and Temperature Data Byte registers. 0.125°C) If only 1°C resolution is required, temperature readings can be taken at any time and in any particular order. If an 11-bit measurement needs to be read, the process involves reading two registers for each measurement. To get the 11-bit result from the remote sensor, the controller must first read the temperature data byte register (0x06), then read The remote temperature data byte register (0x0B) is required to complete the read. However, in order to get only bit 11 of the local sensor, or both local and remote sensors, the controller must first read the temperature data lbyte, then the local temperature data hbyte (0x0a), and finally read the remote temperature data hbyte. This method causes all relevant temperature data registers to be frozen until the remote temperature data hbyte register is read. This process also prevents the high-byte data from being updated when three lsbs are read, and vice versa.

The AMC6821 has the following temperature limit detection:

1. High and low temperature limits: The values of the high temperature limit and low temperature limit registers specify the remote or local temperature range for normal operation. When the local or remote temperature is equal to or higher than the value of the corresponding high temperature limit register, the lth or rth bit in the status register is set ("1"). Likewise, the ltl or rtl bit in the status register is set ("1") when the local or remote temperature is less than or equal to the corresponding low temperature limit register.

A local temperature out of range event occurs when the local temperature is out of range (lth=1 or ltl=1). Set the LTO bit in the status register ("1"), if the LTO interrupt is enabled, an LTO interrupt is generated through the SMBALERT pin (set the LTO bit of the configuration register 2) Similarly, when the remote temperature is out of range (rth=1 or rtl= 1), a remote temperature out of range event occurs. Set the RTO bit ("1") in the status register, and if the RTO interrupt is enabled, generate an RTO interrupt through the SMBAlert pin (ie, set the RTIE bit of Configuration Register 2).

2. Critical Limit: The critical temperature limit is the highest allowable value for the remote or local temperature. When the temperature is greater than or equal to the set corresponding table ("1 in response to critical temperature, LTCT or RTCT bit of the status register"), the output of the ovr pin goes low and a non-maskable interrupt is generated through the smbalert pin (low).

3. Passive Cooling Temperature (PSV) Limit: This limit defines the passive cooling threshold. In automatic remote temperature fan control mode, when the remote temperature is at or below this limit, the system enters passive cooling and the fans stop. In maximum fast calculation control mode, when the remote and local temperatures are at or below this limit, the fans stop and the system enters passive cooling. In passive cooling, Status Register 2 (0x03) is set to '1' and if enabled, a PSV interrupt is generated on the SMBALERT pin (PSVIE=1). Note that reading the status register will clear the LPSV bit. After reading, if the active control temperature remains at or below the PSV temperature, the bit restarts on the next monitoring cycle.

4. Thermal Limit: This limit is an additional fail-safe threshold. When the local or remote temperature is at or above this limit, the corresponding L-Therm or R-Therm bit is set ("1") and the Therm pin is asserted for Limit the CPU clock. Also, if enabled, a THERM interrupt is generated on the SMBALERT pin (THERMOVIE=1). Reading Status Register 1 clears the r-therm and l-therm bits. Once cleared, these bits will not be reinserted until the temperature drops by 5 degrees c below the thermal limit, even if thermal conditions persist. If Configuration Register 3 is set to '1', L-Therm=1 or R-Therm=1 forces the fan to run at full speed. When therm-fan-en=0, the state of the l-therm and r-therm bits does not directly affect the fan speed. Note that thermal limits can be lower or higher than other temperature limits. For example, if the thermal limit is lower than the PSV temperature limit, the CPU clock can be throttled when the cooling fan is off.

Remote temperature sensor fault detection

Remote temperature sensor fault detection determines if a remote sensor diode has an open, short to ground, or short to (in-) condition. This fault detection is based on the analog input voltage and is not checked until the first monitoring cycle after power-up is complete.

Reading a faulty sensor will return a value of -128°C (0x80). Since the power-up default value of the temperature data register is 0x80 (–128°C), reading 0x80 from the temperature data register immediately after power-up does not indicate a diode failure. The remote temperature sensor fault can only be checked after the first monitoring cycle has been completed after a power up or reset.

When a remote sensor fault occurs, the remote sensor fault bit (RTF in the status register) is set to "1", the OVR pin is forced low, and if interrupts are enabled (RTFIE=1), RTF is generated through the SMBALERT pin Interrupt Once this interrupt is generated, whether or not the fault condition persists, the RTF bit remains "1" and the ovr pin remains low until a power-on reset or software reset is issued.

PWM output

The PWM output pins are open-drain outputs. When PWM-EN of Configuration Register 2 is cleared ("0"), the PWM output pin is disabled and enters a high impedance state When PWM-EN is set ("1"), the PWM output pin is enabled to drive the fan . When enabled, the state of the PWM output pin is determined by the PWM duty cycle and phase bits (pwminv of Configuration Register 1). When pwminv=0 (default), the PWM output pin goes low at 100% duty cycle (suitable for driving fans with PMOS FETs). Setting PWMINV to '1' causes the PWM output pin to go high for 100% duty cycle (with an external pull-up resistor). This setting is used to drive the NMOS power FET.

PWM waveform settings

PWM frequency and duty cycle are programmable. The value of the DCY register defines the duty cycle: it has 8-bit resolution, and 1LSB corresponds to 1/255 (0.392%). Writing 0x00 sets the duty cycle to 0%; writing 0xFF sets the duty cycle to 100%.

The PWM frequency has two ranges: the high range is from 1kHz to 40kHz, and the low range is from 10Hz to 94Hz. The PWM mode pin state determines the selected range. When the PWM mode pin is grounded, the high range is selected. Otherwise, choose the low range. Bits[pwm2:pwm0] in the Fan Characteristics register define the frequency; see Table 12. The resolution of the pwm waveform period is 0.312µs, which corresponds to a 3.2mhz clock. The default value after power up is 30Hz when the low range is selected, or 25kHz when the high range is selected.

Fan speed measurement

The AMC6821 monitors the fan speed (RPM) through the tachometer pin as shown in Figure 17. The TACH-EN bit (Bit 2, 0x01) of Configuration Register 2 enables fan speed measurement. When TACH-EN is cleared ("0"), measurement is disabled When the TACH-EN bit is set to "1", measurement is enabled This section describes the device behavior when TACH-EN is set ("1").

Due to the low fan speed, the on-chip fan tachometer does not directly count the fan tachometer output pulses. Instead, the period of fan rotation is measured by gating an on-chip clock (100kHz). The result is stored in the TACH data register containing two bytes (16 bits total). Speed monitoring is disabled when the START bit of Configuration Register 1 or the TACH-EN bit of Configuration Register 2 is cleared ("0"); when START=1 and TACH-EN=1, speed monitoring is enabled.

If the speed mode bit is cleared, when the duty cycle of the software duty cycle mode and the automatic temperature fan control mode is less than 7%, the speed monitoring stops and the speed data register is not updated. In software RPM mode, RPM monitoring is performed and updated after each monitoring If the speed mode is "1", the speed monitoring is always performed and the speed data is updated after each monitoring.

data register

Two fan speed pulse cycles (PSPR=0) or four speed pulse cycles (PSPR=1) are measured, and the result is stored in the speed data register, as shown in Figure 17. If the counter is out of range, counting stops; the measurement cycle repeats until With monitoring disabled, the fan speed (RPM) can be calculated as Equation 2:

Read the tachometer data register

To read the fan speed, both the speed data bytes and the speed data bytes must be read. The tachometer data bytes must be read first. This read causes the tach data HByte to be frozen until both the high and low byte registers have been read, thus preventing tach reading errors.

Speed measurement rate

The TACH-FAST bits in Configuration Register 4 determine the rate. When TACH-FAST=1, the TACH-DATA register is updated every 250 ms (fast monitoring). When TACH-FAST=0 (default), the reading is updated every second (standard monitoring period).

Select the number of pulses/revolutions

Most common fans have tach sensors that provide two or four tach pulses per revolution. The pspr bits of Configuration Register 4 specify how many pulses are generated per revolution. pspr=1 means four pulses/rev, pspr=0 (default) means two pulses/rev.

Speed mode selection

The tach mode bits of configuration register 2 specify the fan's tach pulse output mode. Some fans (such as 3-wire and 2-wire) are powered directly by PWM, and the PWM must be turned on to provide tach pulse output. When the PWM output pin directly turns on/off these fans, The PWM output must be maintained in order to power the fan during the measurement period. In this case, the RPM Mode bit of Configuration Register 2 must be cleared ("0"). When RPM Mode = 0, during the critical RPM edge of the measurement period, Leaving the PWM output pin on to clear the tach mode ('0') also enables internal correction circuitry to correct for errors caused by the extra duty cycle applied during the measurement period. The power-on default value of PWM mode is "0".

Some fans (such as the JMC™ 4-wire fan) are powered directly by DC power rather than by PWM. In this case, the speed mode must be set to "1". When TACH-mode=1, the PWM output pins are not forced on; instead, the state is completely controlled by the DCY register, just like normal operation. Setting the tach mode to '1' also disables the internal correction circuit since no additional duty cycle is applied. Setting the tachometer mode to '1' allows the tachometer to be read continuously regardless of the state of the PWM output pins.

The choice of speed mode affects speed monitoring and control. When the tach mode bit is equal to '1', the duty cycle of the PWM output pin is always determined by the calculated value; the tach data is always updated on every tach monitor. However, when the tach mode bit is equal to "0", in software tach control mode, if the calculated duty cycle is less than 30%, the PWM output pin is forced to 30%; in other modes, the PWM output pin is forced to 30%. The output pin is forced to 0%, if the calculated duty cycle is less than 7%, the tach data will not be updated.

Fan speed out of range detection

Larger values of rotational speed data correspond to lower rotational speeds. When the tachometer data is greater than the tachometer lower limit, the fan is running below the predefined minimum speed and the fan bit in Status Register 1 is set to '1'. Note that there is no fan (fan slow) detection during spin-up the FANS bit is cleared ('0') only after reading this register, if fan slow is detected it is re-asserted ('1') in the next monitor after spin-up, Even if the RPM data is less than the lower RPM limit, the fan will be set ("1") until the register is read.

When the TACH data is less than the TACH upper limit, the fan is running above the predefined maximum RPM and the RPM-alarm bit in Status Register 1 is set ('1'). Note that the RPM-alarm bit is cleared when the register is read. Once cleared, this bit will not be reinserted in the next monitoring cycle even if the condition persists. This bit may only reappear when the RPM drops below the maximum allowed speed.

When FANS=1 or RPM-ALARM=1, if the FANIE bit in Configuration Register 1 is set ("1"), a fan out-of-range interrupt occurs and a fan-ORN is generated. This interrupt drives the SMBALERT pin low.

Fan Failure Detection

When the tachometer data is greater than the tachometer lower limit, the fan runs at a speed lower than the predefined minimum speed. When this happens, a boot process is applied to start the fan again when boot is enabled. Bits[stime2:stime0] of the fan characteristics register define this time period. Figure 19 shows the function of fan failure detection. See the fan rotation section.

Fan speed is measured immediately after startup; the TACH-FAST bits in Configuration Register 4 determine the monitoring rate. If the fan does not return to the normal range after 5 consecutive rotations, a fan fault occurs; the fan fault pin goes low when enabled (setting the fan fault en bit in Configuration Register 1), and the rotation process continues. If the fan returns to normal speed range before the fifth rotation, the fan fault pin will not go low even though the fan bit is still set to '1' Fan fault pin will not go low during startup (fan slow) detection After that, the acceleration will be performed indefinitely until the tach reading returns to the normal range or the acceleration is stopped.

The SMBAlert pin continues to generate interrupts after the fan fault pin is asserted because the tachometer measurement continues even after a fan fault. If the fan recovers from a fault state, the fan fault pin signal is invalid and the fan returns to normal operating speed. Figure 20 shows the operation of the fan interrupt.

Fan fault pin

The fan fault pin is an open-drain output pin as shown in Figure 21. When the fan-fault-en bit in Configuration Register 1 is cleared ("0"), the pin is disabled and is always in a high impedance state . When FAN-FAULT-EN=1, the pin is enabled and the status indicates a fan failure. When a fan fails, the pin is asserted low. When the fan returns to normal speed, the fan fault is negated.

fan control

Hot pins and external hardware control

The THERM pin is a bidirectional I/O, as shown in Figure 22.

output heat pin

As an open-drain output, the thermal pin is an indicator that the temperature has exceeded the thermal limit. When the remote temperature exceeds the remote temperature limit, or when the local temperature is above the local temperature limit, the thermal pin goes low and remains low until the measured temperature drops 5°C below the exceeded temperature limit.

When the thermal limit is exceeded, the corresponding status flag bit (r-therm or l-therm of status register 1 or status register 2) is set to "1", if enabled, a thermal interrupt is generated through the smbalert pin (bit configuration register 1 thermovie is set to "1"). This interrupt forces the smbalert pin low. Note that the Therm pin is always forced low when R-Therm=1 or L-Therm=1, regardless of the state of Thermovie. Reading the status register will clear the flag bits (r-therm and l-therm). Clearing the flag bit returns the smbalert pin high, but does not negate the therm pin. It remains in a cryogenic state until the temperature drops below the overtemperature limit of 5c. After clearing this bit, the active flag (R-THERM for remote temperature or L-THERM for local temperature) and the THERM interrupt will not be re-enabled until the temperature drops 5°C below the exceeded thermal limit. This process is shown in Figure 23. Show.

When operating as an output, the state of the THERM pin affects the RPM fan If the therm-fan-en bit is set ("1"), the fan will go to full speed (ie 100% duty cycle) when the therm pin goes low . However, when therm-fan-en=0, the state of the therm pin does not affect the fan speed.

hot pin as input

When this pin is used as an input, it is an input for external hardware control signals; the hot input bit of status register 2 reflects this input When the Therm Pin is pulled low as an input, the Therm is set regardless of the Therm-Fan-en -In ("1") and drive the fan at full speed (ie 100% duty cycle). The Therm-Fan-en bit has no effect when the Therm pin is used as an input.

fan rotation

The PWM duty cycle controls the cooling fan speed. In order to rotate the fan from a stopped state or a low speed state, a rotation process is employed to overcome the fan inertia. During the first third of startup, the PWM duty cycle gradually increases from 33.3% to 100%, and then remains at 100% throughout. At the end of the start-up process, after the duty cycle is adjusted to 33.3%, the fan speed control is normal. The spiral up process is shown in Figure 24. Bits[stime2:stime0] (bits 2:0 of 0x20) define the acceleration time from 0.2 seconds to 8 seconds, as shown in Table 13. The fan speed is monitored immediately after the start-up process.

Spin-up can be disabled by setting the fspd bit of the fan characteristics register to '1'. If disabled, when the fan is stopped or the speed is detected to be lower than the minimum speed, the acceleration process speed low limit register will not be applied to define the minimum speed. After power up or reset, the fspd bit will be cleared and spin up will always be performed regardless of the state of the fan bit (bit 1 of 0x02).

Note that no fan (slow fan) detection is performed during startup. This bit is only cleared ('0') after being read and reset to '1' on the next monitoring if a slow fan speed condition is detected. After spinning, the fan will be set ("1") until the flag is read, even if the tach data is less than the lower tach limit.

Normal Fan Speed Control

The fan speed is controlled by four different modes: software DCY control; software speed control; automatic remote temperature fan control.

Maximum fast calculation control.

The automatic temperature control fan control mode consists of automatic remote control fan control and maximum speed ratio calculation control. It is an intelligent closed loop control. In this mode, the fan speed is controlled by the remote temperature (automatic remote temperature fan control) or the maximum speed calculated by the internal temperature and the remote temperature. This control mode optimizes fan speed for a given temperature to intelligently manage system thermal/acoustics. After the user writes the appropriate registers to define the parameters of the linear feedback control algorithm, the AMC6821 operates independently without even the intervention of the microcontroller. It ensures that if the controller or system locks up, the fan can still be controlled based on the temperature measurement and adjusts the fan speed to correct for any changes in system temperature. The software speed acts as a fan speed regulator, keeping the speed at a programmable target value. It is a Closed loop mode, can also run independently. Software DCY mode is an open-loop mode; when the user writes the desired duty cycle to the device register, the PWM output duty cycle changes to the target value immediately.

The FDRC1 and FDRC0 bits in Configuration Register 1 determine the mode of operation.

Software DCY control mode

When bit[fdrc1:fdrc0]=[00], the fan operates in software dcy control mode. The host writes the desired duty cycle value corresponding to the desired rotational speed into the DCY register. The duty cycle changes to the new value immediately after writing. In this mode, if tach measurement is enabled (bit 2 of 0x01 = 1) and the tach mode bit (bit 1 of 0x01) is cleared ("0"), then when the value in the DCY register is less than 7%, the The duty cycle of the PWM-OUT pin is forced to 0%. However, if tach measurement is disabled (bit 2 of 0x01 is cleared) or tach mode is set ("1"), the DCY register always holds the programmed value written by the host, even if the programmed value is less than 7% Forced to be set to "0".

Software Speed Control Mode (Fan Speed Regulator)

This mode acts as a fan speed regulator, keeping the speed at a programmable target value. It only works when speed measurement is enabled (bit 2 = 1 of 0x02) When bits [FDRC1:FDRC0] = [01], the fan Operates in software speed control mode, as shown in Figure 25. The host writes the correct value to the speed setting register to set the target fan speed. The actual fan speed is monitored by an on-chip fan speed counter and the result is stored in the TACH data register (see the Fan Speed Measurements section for more details). Compare the actual speed with the set value. If there is a difference, adjust the duty cycle.

Monitor and adjust every second or every 250 ms as determined by the TACH-FAST bit (bit 5, 0x04) of configuration register 4. Bits[STEP1:STEP0] of the DCY-RAMP register define the allowable amount of each adjustment when The adjustment ends when the difference between the tachometer data and the value of the tachometer setting register is equal to or less than 0x000A. 0x000A corresponds to a tolerance of about 1.8% at 10,000 rpm, or about 0.9% at 5,000 rpm. The measurement architecture is shown in Figure 26.

In actual operation, the selected target speed cannot be too low to operate the fan. When the tach mode bit (bit 1 of 0x02) is cleared ('0'), the duty cycle of the PWM output is forced to 30% when the calculated expected value of the duty cycle is less than 30%. Therefore, the speed setting value must not be greater than the value corresponding to the speed at 30% duty cycle. When the RPM mode is "1", the RPM setting must not be greater than the value corresponding to the minimum allowed RPM for the fan to operate normally.

Auto temperature fan mode

Auto Temperature Fan Mode is a closed loop control that optimizes fan speed at a given temperature to intelligently manage system thermal/acoustics. It operates independently, even without controller intervention. The AMC6821 has two automatic temperature fan control modes. When bit[FDRC1:FDRC0]=[10] (default), the fan is in automatic remote temperature fan speed control mode. The temperature reading from the remote temperature sensor is the active control temperature that controls the PWM duty cycle. When bits[FDRC1:FDRC0]=[11], the fan is in maximum fast speed calculation control mode. Local temperature and remote temperature have independently programmed control loops with different parameters. In the maximum speed fast calculation control mode, the fan speed required for the remote and local channels is calculated separately. Whichever control loop calculates the fastest speed based on the measured temperature will drive the fan monitor. Once activated, the PWM duty cycle is determined by the actual control temperature. When the temperature is higher than the low temperature and lower than the high temperature, the internal control loop automatically adjusts the duty cycle to an appropriate value according to the measured temperature. When the temperature increases, the duty cycle increases; when the temperature decreases, the duty cycle decreases. This structure Keep the fans running at optimal speed at all times. This adjustment is based on the control loop parameters defined in the Local Temperature Fan Control Register, Remote Temperature Fan Control Register, and DCY Ramp Register. Changing the parameters will change the duty cycle and fan speed to the desired values.

Bits[R-TEMP4:R-TEMP0] of the remote temperature fan control register and bits[L-TEMP4:L-TEMP0] of the local temperature fan control register are the low temperature bits that define the low temperature of the control loop Bits[spl2:spl0] of these registers is the slope bit that defines the duty cycle increment for a 1°C increase in temperature. Bits[rate2:rate0] (Bits[4:1], 0x23) of the DCY-RAMP register specify the update rate of the duty cycle in temperature fan control mode, and Bits[step1:step0] define the amount of adjustment of the duty cycle each time renew. The target duty cycle for temperature T1 and high temperature (high temperature) can be calculated by Equation 3:

When the active control temperature is equal to or lower than the corresponding low temperature, the duty cycle is equal to the value of the DCY-low-TEMP register, and the fan runs at a predefined minimum speed. When the control temperature is equal to or higher than the corresponding high temperature, the PWM duty cycle The empty ratio is set to 100% and the fans run at full speed. When the active control temperature is equal to or lower than the corresponding value of the PSV temperature register (the predefined passive cooling temperature), the fan stops working and the PWM duty cycle is set to 0.

When the actual duty cycle is different from the expected value, the duty cycle is automatically adjusted. When the RAMP bit of the DCY-RAMP register is cleared ("0"), the duty cycle becomes the desired value immediately after calculation. When the ramp bit is "1", the duty cycle gradually changes to the new value.

The DCY-RAMP register specifies the speed at which the duty cycle changes. Depending on bits[rate2:rate0], the duty cycle can be checked every 0.0625 seconds to every 8 seconds. It changes 1/255 (0.392%) to 4/255 (1.57%) each time, depending on the bits[step1:step0] bits. Adjustment ends when the difference between the actual value and the target value is equal to or less than the adjustment threshold (defined by Bits[THRE1:THRE0]). See the DCY-RAMP register for details. When tachometer monitoring is enabled (tach-EN bit, bit 2 of 0x02 is set to "1") and the tachometer mode bit (bit 1 of 0x02) is cleared ("0"), when the calculated value is less than 7%, Duty cycle is forced to 0% If speed monitoring is disabled (rev-en=0) or the speed mode bit is set ('1'), the duty cycle is always set to the calculated value even if the value is less than 7%.

interrupt

AMC6821 provides two interrupt output pins, OVR and SMBALERT.

ovr pin

OVR is an open-drain output pin used as a supercritical temperature limit (shutdown threshold) indicator and a remote sensor fault indicator. This architecture is shown in Figure 30. Setting the OVREN bit of Configuration Register 4 to "1" will enable this pin; clearing OVREN ("0") will disable this pin. When disabled, the ovr pin is in a high impedance state. When enabled, the status is controlled by the supercritical temperature flag and remote sensor fault flag bits in the status register.

When the temperature exceeds the critical limit (shutdown threshold), the corresponding supercritical limit flag of the status register (RTC for the remote channel and LTC for the local channel) is set ("1"). When reading the status register, this flag is cleared ("0"). Once cleared, even if the supercritical limit condition persists, this bit will not be reset until the temperature drops 5°C below the supercritical limit when the temperature is equal to or Above the critical temperature limit, the ovr pin will be asserted (active low) to indicate this critical condition. As a supercritical temperature limit indicator, once determined, the OVR pin remains low until the measured temperature drops 5°C below the supercritical limit.

When a remote temperature sensor fault condition (short or open) is detected, the Remote Temperature Sensor Fault bit (RTF) in Status Register 1 (Bit 5, 0x02) is set ("1"), regardless of the state of RTFIE, ovr pins are forced low. This value indicates that the remote sensor is faulty. Once this occurs, the RTF bit remains '1' and the OVR pin remains low until a power-on reset or software reset is issued, regardless of whether the fault condition continues. When rtfie=1, rtf=1 also generates rtf interrupt through smbalert pin.

smbalert pin

The SMBALERT pin is a standard interrupt output defined by the SMBus specification version 2.0. This pin is an open-drain output pin, as shown in Figure 33.

smbalert interrupt behavior

When an overrun event occurs, the appropriate flag bit ('1') is set in the status register and the corresponding interrupt (if enabled) is generated. When an interrupt is generated, the SMBALERT pin is asserted low. The host can poll the device status register for information, or respond to the smbalert interrupt signal. When writing interrupt handler software, attention must be paid to the behavior of the SMBALERT output and status bits Figure 31 shows the behavior of the SMBALERT output and status bits.

Once the limit is exceeded, the corresponding status bit will be set to '1'. The status bits remain set until the error condition disappears and the status register is read. Status bits are called sticky because they stay set until they are read by software. This design ensures that if the software periodically polls the device, the limit exceeded event will not be missed. For the entire duration of the read limit violation, smbalert The output remains low and remains low until the status register is read. This architecture has implications for how software handles interrupts.

Handling smbalert interrupts

In order to prevent the system from being bound when the service is interrupted, it is recommended to handle the SMBALERT interrupt in the following way:

1. Detect smbalert assertions.

2. Enter the interrupt handler.

3. Read the status register to identify the source of the interrupt.

4. Disable the interrupt source by clearing the appropriate enable bit in the configuration register.

5. Take the appropriate action for the given interrupt source.

6. Exit the interrupt handler.

7. Periodically poll the status register. If the interrupt source bit is cleared, reset the corresponding interrupt enable bit to '1'. This reset causes the smbalert output and status bits to behave as shown in Figure 32.

Individual interrupts can be masked to prevent smbalert interrupts by clearing the corresponding interrupt enable bit in the configuration register. Note that masking the interrupt source only prevents the smbalert pin output from being asserted; the appropriate status bits are set to normal.

register map

All registers are 8 bits.

Device Status Register

Reading the status register will clear the corresponding status bit. Status register bits are sticky (except for RTF bits) Whenever a status bit is set (indicating a limit violation), it will remain set until the event that caused it is resolved and the status register is read only after the event is resolved Status register, to clear status bits. When the register is read, all bits are cleared, and if the limit state still exists in the next monitoring cycle, all bits are re-acknowledged, unless otherwise stated.

In a read operation, the data returned is the actual duty cycle (DCY) value driving the PWM output pin, with the following two exceptions:

1. When speed mode=0 and the system is in software speed control mode, if the calculated duty cycle is less than 30%, the return value is the calculated value, not the actual PWM output pin duty cycle forced to 30% .

2. When the speed mode = 0 and the system is in software DCY control mode or auto temperature fan mode, if the calculated duty cycle is less than 7%, the return value is the calculated value, not the actual PWM output pin forced to 0% duty cycle.

In a write operation, the data written is the actual DCY driving the PWM output pins in software DCY control mode. However, in all other control modes, the data written is not used to drive the PWM. Instead, it is stored in a temporary register and controls the PWM as soon as the control mode is changed to software DCY control mode.