Module Features, Architecture Overview, Array Size and Resources, Functional Description DS099 (v3.1) Input/Output Block (IOB), IOB Overview, SelectIO Interface I/O Standard, Configurable Logic Block (CLB) Block RAM, Dedicated Multiply Controller, Digital Clock Manager (DCM) Clock Network, Configuration Module 3: DC and Switching Characteristics DS099 (v3.1) DC Electrical Characteristics Absolute Maximum Ratings Supply Voltage Specifications Recommended Operating Conditions DC Characteristics Switching Characteristics I/O Timing Internal Logic Timing DCM Timing Configuration and JTAG Timing Module 4, Pin Descriptions, Pin Behavior During Configuration, Package Overview, Pin Table, Package Outline

Introduction The Spartan® 3 family of field programmable gate arrays is specifically designed to meet high volume, cost sensitive consumer electronics applications.
These eight member families offer system door densities ranging from 50,000 to 5,000,000. The success of the Spartan-3 series builds on the earlier Spartan IIE series, which increases the number of logic resources, the amount of internal RAM, the total number of I/Os, and the overall performance level, and improves clock management capabilities. Many enhancements stem from virtex ? -ii Platform Technology. These Spartan-3FPGA enhancements, combined with advanced processing technology, provide more features and bandwidth per dollar than before, setting a new standard in the programmable logic industry Due to its extremely low cost, Spartan-3 FPGAs are ideal for a wide range of consumer electronics applications, including broadband access, home networking, display/projection and digital television equipment. The Spartan-3 series is an alternative to mask programming asic. FPGAs avoid the high initial costs, lengthy development cycles and inherent flexibility of traditional ASICs. In addition, the programmability of FPGAs allows for field design upgrades without the need for hardware replacement, which is not possible in ASICs.
Functional, low-cost, high-performance logic solution for high-volume, consumer-facing applications, up to 74,880 logic cell densities, selectio interface signaling, up to 633 I/O pins per I/ O's 622+MB/s data transfer rate, 18 single-ended signal standards, 8 differential I/O standards, including LVD, RSD, termination through digitally controlled impedance, signal swing range from 1.14V to 3.465V, double data rate (DDR) support, DDR, DDR2 SDRAM support up to 333 MB/s, logic resources, rich logic cells, with shift register function, wide, fast multiplexer, fast look-ahead carry logic, dedicated 18 x 18 multiplier , JTAG logic compatible with IEEE 1149.1/1532, SelectRAM hierarchical memory, total block RAM up to 1872kbit, total distributed RAM up to 520kbit, digital clock manager (up to four DCMs) clock skew cancellation, frequency synthesis, high resolution phase mobile, eight global clock lines and rich routing, fully supported by Xilinx ISE® and Webpack software development systems, Microblaze and PicoBlaze processors, PCI® and PCI Express® pipe endpoints and other IP cores, no PB package options, Automotive Spartan- 3 XA Series Variant Architecture Overview The Spartan-3 Series architecture consists of five basic programmable functional elements: The Configurable Logic Block (CLB) contains a RAM-based Look-Up Table (LUT) that implements functions that can be used as flip-flops or Logic and storage elements of latches. The clb can be programmed to perform various logic functions and store data. Input/Output Blocks (IOBs) control data flow between I/O pins and the device's internal logic. Each IOB supports bidirectional data flow and tri-state operation for 26 different signaling standards, including double data rate (DDR) registers. The Digitally Controlled Impedance (DCI) feature provides automatic on-chip termination, simplifying board design. The block RAM provides data storage in the form of 18kbit dual-port blocks, the multiplier block accepts two 18-bit binary numbers as input and computes the product, and the Digital Clock Manager (DCM) block distributes, delays, multiplies, divides and shifts the clock signal Provides a self-calibrating all-digital solution. The organization of these elements is shown in Figure 1. An iob ring surrounds a regular array of clbs. The xc3s50 embeds a column of block ram in the array. Devices from XC3S200 to XC3S2000 have two columns of block RAM xc3s4000 and xc3s5000 devices have four columns of ram. Each column consists of several 18kbit RAM blocks; each block is associated with a dedicated multiplier. The DCM is located at the end of the external block RAM column. The Spartan-3 series has a rich network of traces and switches, interconnecting all five functional elements, transferring signals between them. Each functional element has an associated switch matrix, allowing multiple connections to be routed.

The configuration Spartan-3fpgas is programmed by loading configuration data into robust reprogrammable static CMOS Configuration Latches (CCLs) that collectively control all functional elements and routing resources. Configuration data is stored in an external prom or Among other non-volatile media, either on or off the board.
Note: 1. The other two block ram columns for the xc3s4000 and xc3s5000 devices are shown with dotted lines. The xc3s50 has only the block ram column on the far left.
Power, configuration data is written to the FPGA using any of five different modes: master parallel, slave parallel, master serial, slave serial and boundary scan (jtag). The master-slave parallel mode uses an 8-bit wide selectmap port. The recommended memory for storing configuration data is the low-cost Xilinx platform Flash PROM family, which includes the XCF00S PROM for serial configuration and the high-density XCF00P PROM for parallel or serial configuration.

Package marking Top marking of Spartan-3 FPGAs in a four-tablet package. Top marking for Spartan-3 FPGAs in BGA packages, except for 132-ball chip scale packages (CP132 and CPG132). The markings for the bga package are almost identical to those for the quad flat package, except that the markings are rotated relative to the ball a1 indicator. The top-marked "5C" and "4I" part combinations for Spartan-3 FPGAs in the CP132 and CPG132 packages can be double marked "5C/4I". Devices with double markers can be used as -5c or -4i devices. Equipment is guaranteed to have a mark only within the marked speed class and temperature range. Some specifications vary based on mask revisions. No errata for Mask Revision E devices. All shipments since 2006 are E-version face shields.

Spartan-3 Field Programmable Gate Array QFP Package Marking Example for Part Number XC3S400-4PQ208C

Spartan-3 fpga design documentation Spartan? The features of the -3 FPGA family are described in the following documents. Topics covered in each guide are listed. 8226 ; UG331: Spartan-3 Generation FPGA User Guide • Clocking Resources • Digital Clock Managers (DCMs) • Block RAM • Configurable Logic Blocks (CLB) - Distributed RAM - SRL16 Shift Register - Carry and Arithmetic Logic • I/ O Resources • Embedded Multiplier Blocks • Programmable Interconnects • ISE® Software Design Tools • IP Cores • Embedded Processing and Control Solutions • Pin Types and Package Overview • Package Diagrams • Powering FPGas • UG332: SPARTAN-3 Generation Configuration User Guide Configuration Overview - Configuration Pins and Behavior - Bitstream Size Detailed Description by Mode - Master Serial Mode PROM using Xilinx Platform Flash - Slave Parallel (SelectMAP) Using Processor - Slave Serial Using Processor - JTAG Modes ISE iMPACT programming examples Create a Xilinx user account and register to receive automatic email notifications when this datasheet or related user guide is updated Input/Output Blocks (IOBs) are provided between the I/O pins and the FPGA internal logic A programmable bidirectional interface. A simplified diagram of the internal structure of the IOB is shown in Figure 7. There are three main signal paths in the IOB: the output path, the input path, and the three-state path. Each path has its own pair of storage elements, which can act as registers or latches. Refer to the Memory Element Functions section for details. The three main signal paths are as follows: • The input path carries data directly from the pad (the pad is connected to the package pin) to the I line via an optional programmable delay element. There is alternate routing to the iq1 and iq2 lines through a pair of storage elements. The iob outputs i, iq1 and iq2 all point to the internal logic of the fpga. Delay elements can be set to ensure zero hold time • The output path, starting from the O1 and O2 lines, transfers data from the FPGA internal logic through the multiplexer and then to the IOB board through a tri-state driver. In addition to this direct path, the multiplexer offers the option of inserting a pair of storage elements. • The three-state path determines when the output driver is high impedance. The T1 and T2 lines pass data from the FPGA's internal logic to the output drivers through a multiplexer. In addition to this direct path, the multiplexer offers the option of inserting a pair of storage elements. When the T1 or T2 line is asserted high, the output driver is high impedance (floating, hi-Z) and the output driver activates low enable. • All signal paths into the IOB, including those associated with storage elements, have an inverter option. Any inverters placed on these paths are automatically absorbed into the IOB.
The storage element function has three pairs of storage elements in each IOB, one pair for each of the three paths. Each of these storage elements can be configured as either edge-triggered d-type flip-flops (fd) or level-sensitive latches ( ld). Pairs of storage elements on the output path or tri-state path can be used with dedicated multiplexers to produce double data rate (DDR) transfers. This is accomplished by converting data synchronized to the rising edge of the clock signal into bits that are synchronized on the rising and falling edges. The combination of two registers and a multiplexer is called a double data rate d-type flip-flop (fddr).

Double Data Rate Transfer Double Data Rate (DDR) transfer describes a technique for synchronizing a signal to the rising and falling edges of a clock signal. Spartan-3 devices use register pairs in all three IOB paths to perform DDR operations A pair of storage elements (off1 and off2) on the iob output path are used as registers, combined with a special multiplexer to form a ddr d-type flip-flop device (fddr). This primitive allows DDR transfers where the output data bits are synchronized with the rising and falling edges of the clock. This functionality can be accessed by placing an fddrrse or fddrcpe component or symbol in the design. DDR operation requires two clock signals (50% duty cycle), one is the inverted version of the other. These signals alternately toggle the two registers, as shown in Figure 8. Typically, a digital clock manager (DCM) generates two clock signals by mirroring one input signal and then shifting it 180 degrees. This method ensures minimal deviation between the two signals. Pairs of storage elements on the tri-state paths (TFF1 and TFF2) can also be combined with local multiplexers to form FDDR primitives. This allows the output to be synchronized to the rising and falling edges of the clock. This DDR operation is implemented in the same way as the output path. The pair of storage elements on the input path (iff1 and iff2) allows the i/o to receive the DDR signal. The incoming ddr clock signal triggers one register, and the reverse clock signal triggers the other register. In this way, the registers take turns capturing the bits of the incoming ddr data signal.

In addition to high-bandwidth data transfer, DDR can also be used to reproduce or "mirror" a clock signal at the output. This method is used to transmit both clock and data signals at the same time. Similar methods are used to reproduce a clock signal at multiple outputs. The advantage of these two methods is that the skew of the outputs is minimal. Some adjacent I/O blocks (IOBs) share a common route connecting the ICLK1, ICLK2, OTCLK1 and OTCLK2 clock inputs of the two IOB pairs by their differential pair name i o_xn_35; and io_xxp_35; to identify, where "xx" is the i/o pair number and "3535;" is the i/o bank number. Two adjacent IOBs containing DDR registers must share a common clock input, otherwise one or more clock signals will not be output.
Pull-Up and Pull-Down Resistors Optional pull-up and pull-down resistors are used to establish high and low levels, respectively, on unused I/Os. Pull-up resistors optionally connect each IOB board to VCCO. A pull-down resistor can optionally connect each pad to GND. These resistors are placed in the design using the pull-up and pull-down symbols, respectively, in the schematic. They can also be instantiated as components, set as constraints, or passed as properties in HDL code. These resistors can also be selected for all unused I/Os using the bitstream generator (bitgen) option unusedpin. A low logic level on HSWAP_EN activates pull-up resistors on all I/Os during configuration (see "I/Os During Power-Up, Configuration, and User Mode" on page 21) spartan-3fpga i/o pull-ups and pull-down resistors are significantly stronger than the "weak" pull-up/pull-down resistors used in previous Xilinx FPGA families. See Table 33 on page 61 for equivalent resistance strength.
Holder Circuits Each I/O has an optional keeper circuit that holds the last logic level on the line after all drivers are turned off. This helps prevent the bus from floating when all connected drivers are in a high-impedance state. This function uses the KEEPER symbol to place pull-up and pull-down resistors in the design to override the keeper circuit.

ESD protection clamping diodes protect all device pads from electrostatic discharge (ESD) and excessive voltage transients. Each i/o has two clamping diodes: one diode extends p-to-n from pad to vcco and the other diode extends n-to-p from pad to gnd. During operation, these diodes are usually biased in the off state. These clamp diodes are always connected to the pads, regardless of the signal standard chosen. The presence of diodes limits the spartan-3fpga's i/o's ability to withstand high signal voltages.
Two options for slew rate control and drive strength, fast and slow, control the output slew rate. The fast option supports high-speed output switching. Slow options reduce bus transients These options are only available when using one of the lvcmos or lvttl standards, which also offer up to seven different levels of current drive strength: 2, 4, 6, 8, 12, 16, and 24ma. Choosing an appropriate drive strength level is another way to minimize bus transients.

Digitally Controlled Impedance (DCI) When the round-trip delay of the output signal (i.e. from output to input and back) exceeds the rise and fall times, terminating resistors are often added on the line carrying the signal. These resistors effectively match the input/output impedance of the device to the characteristic impedance of the transmission line, preventing reflections that can adversely affect signal integrity. However, with the high I/O counts supported by modern devices, adding resistors requires significantly more components and board area. Also, with some packages, such as ball grid arrays, it may not always be possible to place resistors near the pins. DCI addresses these issues by providing two types of on-chip termination: Parallel termination using an integrated resistor network series termination is the result of controlling the output driver impedance. DCI actively adjusts parallel and series terminations to precisely match the characteristic impedance of the transmission line. This adjustment process compensates for input/output impedance differences due to normal variations in ambient temperature, supply voltage, and manufacturing processes. When the output driver is off, the series termination is, by definition, close to a very high impedance; conversely, the shunt termination resistance remains at the target value. DCI is only available for certain I/O standards, as shown in Table 10. DCI is selected by applying the appropriate I/O standard extension to the symbol or component. There are five basic ways to configure endpoints, as shown in Table 11. The DCI I/O standard determines which endpoints are in effect. The vrn and vrp reference resistors are not required for hstl_i_dci-, hstl_iii_dci- and sstl2_i_dci- type outputs. Likewise, LVDCI type inputs do not require VRN and VRP reference resistors in groups without any dci i/o or containing non-dci i/o and pure hstl_u dci- or hstl_u dci-type outputs or sstl2_u dci-type outputs or lvdci-type inputs In the group, the associated vrn and vrp pins can be used as general purpose I/O pins. The hslvdci (high speed lvdci) standard is for bidirectional use. The driver is the same as lvdci and the input is the same as hstl. By using a vref reference input, hslvdci allows greater input sensitivity at the receiver than when using single-ended lvcmos type receivers.

Spartan-3fpga Compatible In the Spartan-3 series, all devices are pin-compatible through packaging. When the demand for future logic resources exceeds the capacity of the currently used Spartan-3 devices, larger devices in the same package can be directly replaced Larger devices may add additional vref and vcco lines to support more i/o. In larger devices, more pins can be converted from user I/O to VREF lines. Additionally, additional VCCO lines are connected to pins that are "unconnected" in smaller devices. Therefore, when the board is initially designed, it is important to plan for future upgrades by laying out connections to extra pins. The Spartan-3 family is not compatible with any previous Xilinx FPGA family or other platforms in the Spartan-3 generation of FPGas.
Rules Regarding Banks When assigning I/O to banks, the following VCCO rules must be followed: Do not leave the VCCO pins unconnected to the FPGA. Set all VCCO lines associated with the (interconnect) group to the same voltage level. The VCCO level used by all standards assigned to (interconnected) bank I/O must be consistent xilinx development software will check for this. Output per bank is only allowed in one of the following standards: LVDS, LDT, LVDS-EXT, or RSD This limit applies to eight banks per device, even if the VCCO level is shared across banks, as in CP132 and TQ144 packages said. If any standard assigned to (interconnect) group I/O does not use VCCO, connect all relevant VCCO lines to 2.5V. Typically, 2.5V is applied to VCCO bank 4 from power-up to end of configuration. During parallel configuration or readback operations, apply the same voltage to VCCO bank 5. Refer to the 3.3V Fault Tolerant Configuration Interface section for information on how to program the FPGA using a 3.3v signal and power supply. If any standard assigned to a cylinder bank input uses VREF, follow these additional rules: • Connect all VREF pins within the bank to the same voltage level. • The reference voltage level used by all standards assigned to the bank input must be consistent with the xilinx development software which will check this. Tables 8 and 10 describe how the different standards use the VREF supply. If none of the standards assigned to the bank inputs use VREF to bias the input switching threshold, all associated VREF pins operate as user I/Os.
Bank Exceptions That Support I/O Standards Bank 5 of any Spartan-3 device in the VQ100, CP132, or TQ144 package does not support the DCI signaling standard. In this case, bank 5 has neither VRN nor VRP pins.

Powering the IOB Three different power supplies power the IOB: • V CCO powers the output drivers, one power per I/O bank except when using the GTL and GTLP signaling standards. The voltage on the VCCO pin determines the voltage swing of the output signal • v ccint is the main power supply for the fpga's internal logic. V CcAUX is the auxiliary power supply, mainly to optimize the performance of various FPGA functions such as I/O conversion.
During power up, configuration, and user mode, all I/Os are in a high impedance state when no power is applied to the FPGA. The VCCINT (1.2V), VCCAUX (2.5V) and VCCO supplies can be used in any order. Before power-up is complete, VCCINT, VCCO Bank 4, and VCCAUX must reach their respective minimum recommended operating levels (see Table 29 on page 59). At this point, all I/O drivers will also be in a high impedance state. VCCO Bank 4, VCCINT and VCCAUX are used as inputs to the internal power-on reset circuit (POR). A low applied to the hswap_en input enables the pull-up resistors on the user I/Os to operate from power-up throughout configuration. A high level on hswap_en will disable the pull-up resistor, allowing the I/O to float. If the hswap_en pin is floating, the internal pull-up resistor pulls hswap_en high. Once powered up, the FPGA begins to initialize its configuration memory. At the same time, the FPGA internally declares a global reset (GSR), which asynchronously resets all IOB storage elements to a low state. After initialization is complete, INIT_B goes high, and the M0, M1, and M2 inputs are sampled to determine the configuration mode. At this time, the configuration The data is loaded into the fpga. During the entire configuration process, the I/O driver is always in a high-impedance state (with or without a pull-up resistor based on the HSWAP_EN input). The global tri-state (GTS) network is released during startup, marking the end of configuration and design in user mode Operation starts. At this point, those I/Os that have been assigned a signal will be active, while all unused I/Os will remain in a high-impedance state. The release of the GSR network, which is also part of the startup, leaves the IOB registers low by default. , unless the loaded design reverses the polarity of their respective RS inputs. In user mode, all internal pull-up resistors on the I/O are disabled and HSWAP_en becomes a "don't care" input. If a pull-up or pull-down resistor needs to be installed on an I/O with a signal, the appropriate symbol (eg, pull-up, pull-down) must be placed on the appropriate pad in the design. The bitstream generator (bitgen) option unusedpin available in xilinx development software determines whether unused I/Os have pull-up resistors, pull-down resistors, or no resistors in user mode.
Chapter "Using Configurable Logic Blocks" Configurable logic blocks (clbs) are the primary logic resource for implementing synchronous and combinational circuits. Each CLB contains four interconnected slices, which are grouped in pairs as shown in Figure 11. Each pair is organized into a column with an independent carry chain. The fpga editor part of the xilinx development software is used to specify the naming of slices as follows: the letter "x" followed by a number indicates the column of slices. The "X" number increases from left to right of the die with the letter "y" followed by a number to identify the position of each slice in a pair and to indicate the CLB row. The "Y" numbers count slices from the bottom of the die in the following order: 0, 1, 0, 1 (first CLB row); 2, 3, 2, 3 (second CLB row); and so on. The CLB in the lower left corner of the mold. Slices X0Y0 and X0Y1 form the column pair on the left, where slices X1Y0 and X1Y1 form the column pair on the right For each clb, the term "left-hand" (or slicem) indicates a pair of slices marked with an even "x" number, For example x0, the term "right-hand" (or slice) indicates a pair of cuts with an odd "x" number

Each of the two luts (F and G) in a slice has four logic inputs (A1-A4) and one output (D) which allows any four-variable Boolean logic operation to be programmed into them. In addition, wide function multiplexers can be used to efficiently combine LUTs within the same CLB or across different CLBs, enabling logic functions with more input variables. The LUTs in the right-hand and left-hand slice pairs not only support the above logic functions, but can also be used as a rom for data initialization when configuring. The luts in the left slice pair of each clb support two additional functions that the right slice pair (odd columns such as x1) do not. First, a "left lut" can be programmed as distributed RAM. This type of memory provides modest data buffering anywhere in the data path. A left lut stores 16 bits. Multiple left-side LUTs can be combined in various ways to store larger amounts of data The dual-port option combines two LUTs so memory access can be made from two separate data lines. Distributed ROM option allows memory to be preloaded with data during FPGA configuration Second, each left-hand LUT can be programmed as a 16-bit shift register Used in this fashion, each LUT can delay serial data by 1 to 16 clock cycles . The four left LUTs of a single CLB can be combined to produce up to 64 clock cycles of delayed shift and shift lines cascade LUTs to form larger shift registers. Shift registers can also be combined across multiple CLBs. The resulting programmable delay can be used to balance the timing of the data pipeline.

Block RAM Overview All Spartan-3 devices support block RAM, which is organized as a configurable synchronous 18Kbit block block ram that stores relatively large amounts of data more efficiently than the distributed ram feature described earlier. (The latter is better for buffering small amounts of data anywhere along the signal path.) This section describes basic block RAM functionality. See the section titled "Using Block RAM" in UG331 for more information. The aspect ratio, i.e. the width versus depth of each block RAM is configurable. Additionally, multiple blocks can be cascaded to create wider and/or deeper memory primitives. The choice between the block rams is used as dual port memory or as a Single-port memory operation. A name of the form RAMB16_S[wA]_S[wB] invokes a dual-port primitive, where the integers wA and wB specify the total datapath width of ports wA and wB, respectively. Thus, RAMB16_S9_S18 is a 9-bit wide port a and an 18-bit wide port B of dual-port RAM. A name of the form RAMB16_S[w] identifies a single-port primitive, where the integer w specifies the total datapath width of a single port ramb16_s18 is a single-port ram with 18-bit wide ports. Other memory functions, such as fifo, datapath width conversion, rom, etc., can be easily obtained using the core generator™ software of the xilinx development software.

In the case of on-chip synchronization,

Any of the DLL's seven output clock signals can be connected to the FPGA's internal registers through a common routing resource. The global clock buffer (bufg) or bufgmux provides access to the global clock network. Create a feedback loop by routing CLK0 (or CLK2X, in section [b]) to the global clock network, which in turn drives the CLKFB input. In the case of off-chip synchronization, Clk0 (or Clk2x) plus any other output clock signals of the DLL are used The output buffer (OBUF) exits the FPGA to drive the external clock network plus on-board registers. As shown in section [c] of Figure 21, a feedback loop is formed by feeding clk0 (or clk2x in section [d]) back to the FPGA using ibufg that directly accesses the global clock network or ibufg. The global clock network is then connected directly to the clkfb input. Dynamic Link Library Frequency Mode The dynamic link library supports two different operating modes, high frequency and low frequency, each of which is specified in a different clock frequency range. The dll_frequency_mode property selects between two modes. When the property is set to low, low frequency mode allows all seven DLL clock outputs to operate in the low to medium frequency range. When the property is set to high, high frequency mode allows the clk0, clk180 and clkdv outputs to operate at the highest possible frequency. The rest of the dll clock outputs are not available in high frequency mode. If the frequency of the CKIN signal is high so that it exceeds the maximum allowable value, use the high input frequency, divide it into an acceptable value, use the CKNYLIDVIEBYBYS2 property. When this property is set to TRUE, the CLKIN frequency is divided by a factor of 2 when entering DCM.

Statements made in this agreement for Xilinx hardware FPGA and CPLD devices are not subject to the terms and conditions of Xilinx's limited warranty, which does not apply to use of the product in applications or environments that do not meet the specifications set forth in the Xilinx data sheets. All specifications are subject to change without notice The product is not designed or intended to be fail-safe, nor is it intended for use in any application requiring fail-safe performance, such as life support or safety devices or systems, or any other cause of death, personal injury or Applications with potential risk of damage to property or the environment ("Critical Applications"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT YOUR OWN RISK UNDER APPLICABLE LAWS AND REGULATIONS CRITICAL APPLICATIONS DISCLAIMER XILINX products (including hardware, software and/or IP cores) are not designed or intended to be Safety performance applications, such as life support or safety equipment or systems, tertiary medical equipment, nuclear installations related to airbag deployment, or any other application that could lead to death, personal injury, or serious property or environmental damage (individually or collectively) referred to as "critical applications") In addition, Xilinx products are not designed or intended to affect the Any application for vehicle or aircraft control. Customer agrees to thoroughly test any system containing Xilinx products for security purposes before using or distributing it. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, CUSTOMER ASSUME ENTIRE RISK AND RESPONSIBILITY FOR THE USE OF Xilinx PRODUCTS IN CRITICAL APPLICATIONS. Automotive Application Disclaimer Xilinx products are not designed or intended for use in fail-safe, or in any application requiring fail-safe performance, such as those associated with: (i) deployment of airbags, (ii) control of vehicles, unless Have fail-safe or redundant features (excluding the use of software for redundancy in Xilinx equipment) and warning signs of operator failure, or (iii) use that could result in death or personal injury. Customer assumes all risk and responsibility for the use of Xilinx products in such applications.