feature

All-in-one synchronous buck driver; bootstrap high-side driver; one PWM signal generates two drivers; programmable transition delay; anti-cross-conduction protection circuit.

application

Multiphase desktop CPU power supplies; mobile computing CPU core power converters; single-supply synchronous buck converters; standard to synchronous converter adaptations.

General Instructions

The ADP3412 is a dual mosfet driver optimized for driving two N-channel mosfets, which are two switches in a non-isolated synchronous buck power converter, each capable of 20 ns propagation delay and 30 ns transition time Drives 3000 pf loads. One of the drivers can be bootstrapped for handling high voltage slew rates associated with "floating" high side gate drivers. The ADP3412 includes Overlap Drive Protection (ODP) to prevent shoot-through currents in external MOSFETs.

ADP3412

Typical performance characteristics

theory of operation

The ADP3412 is a dual MOSFET driver for driving two N-channel MOSFETs in a synchronous buck converter topology. Only one PWM input signal is required to properly drive the high-side and low-side FETs. Each driver can drive a 3nf load with a transition time of only 20ns. The ADP3412 and its characteristics are described in more detail below by referring to the general application circuit in Figure 1.

low end driver

The low-side driver is designed to drive low rds(on) n-channel Mossfett drive supplies and sink gate currents with a maximum output resistance of 5Ω. The low output resistance allows the driver to have 20ns rise and fall times under a 3nF load. Biasing of the low-side driver is internally connected to the VCC supply and PGND.

The output of the driver is 180 degrees out of phase with the PWM input.

high end drive

The high-side driver is designed to drive a floating low RDS(ON) N-channel MOSFET with a maximum output resistance of 5Ω for drive supply and sink gate current. The low output resistance allows the driver to have 20ns rise and fall times with a 3nF load. The bias voltage for the high-side driver is generated by an external bootstrap power supply circuit, which is connected between the BST and SW pins.

The bootstrap circuit includes a diode d1 and a bootstrap capacitor cbst. When the ADP3412 starts up, the switch pin is grounded, so the bootstrap capacitor will charge to VCC through D1. When the PWM input goes high, the high-side driver will start to turn on the high-side MOSFET by drawing charge from CBST, Q1 When Q1 is turned on, the SW pin will rise to VIN, forcing the BST pin to VIN+VC (BST), which is the gate-to-source voltage sufficient to keep Q1 on. To complete the cycle, Q1 is turned off by pulling the gate down to the voltage at the SW pin. When the low-side mosfet Q2 turns on, the SW pin is pulled to ground. This allows the bootstrap capacitor to recharge to VCC. The output of the high-side driver is synchronized with the PWM input.

Overlap Protection Circuit

An Overlap Protection Circuit (OPC) prevents the main power switches Q1 and Q2 from being turned on at the same time. This is done to prevent penetration currents from flowing through both power switches, and the associated losses that may occur during switching transitions. The overlap protection circuit works by adaptively controlling the delay from Q1 off to Q2 on, and from Q2 off to Q2 by an external setting. A delay in Q1 opening to achieve this.

To prevent gate driver overlap during Q1 off and Q2 on, the overlap circuit monitors the voltage at the switch pins. When the PWM input signal goes low, Q1 will start to turn off (after the propagation delay), but before Q2 can turn on, the overlap protection circuit waits for the voltage at the SW pin to drop from VIN to 1v. Once the voltage on the SW pin drops to 1v, Q2 will start to turn on By waiting for the voltage on the sw pin to reach 1v, the overlap protection circuit ensures that Q1 turns off before Q2 turns on, regardless of temperature, supply voltage, gate charge and drive current Variety.

To prevent overlap of gate drivers during Q2 off and Q1 off, the overlap circuit provides a programmable delay set by a capacitor on the dly pin. When the pwm input signal goes high, Q2 will start to turn off (after the propagation delay), but before Q1 can turn on, the overlap protection circuit waits for the voltage at Drvl to drop to around 10% of Vcc. Once the voltage at DRVL reaches the 10% point, the overlap protection circuit will wait a typical propagation delay of 20 ns plus an additional delay based on the external capacitor CDLY delay capacitor adds an additional delay of 1 ns/pf. Once the programmable delay period expires, Q1 will begin to turn on. The delay allows the time for current to swap from the body diode of Q2 to the external Schottky diode, which allows for lower turn-off losses While not as foolproof as the adaptive delay, the programmable delay adds a safety margin to account for the external power mosfet in Variations in size, gate charge, and internal delay.

Application Information Power Supply Capacitor Selection

For the power supply input (VCC) of the ADP3412, a local bypass capacitor is recommended to reduce noise and provide some peak current. Use 1µF low ESR capacitors. Multilayer ceramic chip (MLCC) capacitors offer the best combination of low ESR and small size, keeping ceramic capacitors as close to the ADP3412 as possible.

Bootstrap circuit

The bootstrap circuit uses a charge storage capacitor (CBST) and a Schottky diode, as shown in Figure 1. The selection of these components can be made after selecting the high-side MOSFET.

The bootstrap capacitor must have a voltage rating capable of handling the maximum battery voltage plus 5 volts. The recommended minimum voltage rating is 50 V. The capacitance is determined by the following formula:

where QGATE is the total gate charge of the high-side MOSFET, and ∏ is the allowable voltage drop across the high-side MOSFET driver. For example, the total gate charge of the irf7811 is about 20nc. For an allowable voltage drop of 200 mV, the required bootstrap capacitor is 100 nF. High-quality ceramic capacitors should be used.

A Schottky diode is recommended for the bootstrap diode because of its low forward drop, maximizing the driver for the high-side MOSFET. The bootstrap diode must have a minimum 40 V rating to withstand the maximum battery voltage plus 5 V. The average forward current can be estimated by:

where fMAX is the maximum switching frequency of the controller. The peak inrush current rating should be checked in the circuit as it depends on the source impedance of the 5V supply and the ESR of the CBST.

Selection of Delay Capacitors

The delay capacitor CDLY is used to add an additional delay when the low-side FET driver turns off and the high-side driver starts to turn on. The delay capacitor adds 1 ns/pF of additional time to the 20 ns fixed delay.

If you need a delay capacitor, look for high-quality ceramic capacitors with NPO or COG dielectrics, or high-quality mica capacitors. Both types of capacitors are available in the 1-100 pf range and have excellent temperature and leakage characteristics.

Printed Circuit Board Layout Considerations When designing a printed circuit board, follow these general guidelines:

1. Identify high current paths and use short, wide paths to make these connections.

2. Place the PGND pin of the ADP3412 as close as possible to the power supply of the lower mosfet.

3. The VCC bypass capacitor should be placed as close as possible to the VCC and PGND pins.

Typical Application Circuit

The circuit in Figure 3 shows how two drivers can be combined with an ADP 3160 to form a total power conversion solution for generating VCC (core) in a high current GOA computer Figure 4 shows a similar application circuit for a 35A processor .