Features: Logically 2-mbit Ferroelectric Random Access Memory (f-ram) organized as 128k x 16 256 K x 8 configured using UB and LB High Endurance 100 Trillion (1014) Read/Write 151 Year Data Retention (See Data Retention and Endurance table) nodelay 8482 ; write page mode operation to 30 ns cycle time Advanced high reliability ferroelectric process SRAM compatible with industry standard 128K x 16 SRAM pins 60 ns access time, 110 ns cycle time Advanced Features Software Programmable Block Write Protection Superior to Battery Backed SRAM Modules No Battery Issues Monolithic Reliability True Surface Mount Solution with No Rework Steps Suitable for Moisture, Shock and Vibration Low Power Consumption Active Current 8 mA (typ value) Standby current 90μA (typ) Sleep mode current 5μA (max) Low voltage operation: VDD=2.7 V to 3.6 V Industrial temperature: –40°C to +85°C 44-pin Thin Small Outline Package (TSOP) II Type compliant with Restriction of Hazardous Substances (RoHS)

Functional overview: fm21l16 is a 128k×16 non-volatile memory that can read and write similar to standard SRAM. Ferroelectric random number access memory, or F-RAM, is non-volatile, which means that data is retained after a power outage. It has been battery-backed SRAM (BBRAM) for 151 years while eliminating reliability issues, functional flaws and system design complexity. Fast write timing and high write endurance make f-ram superior to other types of memory. The FM21L16 operates similarly to other RAM devices. Therefore, it can be used as a standard SRAM in the system. The read and write cycles can be triggered by CE or by changing the address. The F-RAM memory is non-volatile due to its unique ferroelectric memory. process. These features make the FM21L16 ideal for non-volatile. In-memory applications that require frequent or fast writes. The FM21L16 includes a low voltage monitor that prevents accesses from being sent to the memory array when VDD is below the VDD minimum. Memory is protected against accidental access and data in this case. The device also has software-controlled write protection. The memory array is divided into 8 uniform blocks, each of which can be individually write-protected. The device is available in a 400 mil, 44-pin TSOP-II surface mount package device specification guaranteed to exceed the industrial temperature range of -40°C to +85°C.

Device Operation The fm21l16 is a word wide f-ram memory, logically organized as AS 131072x16 and uses an industry standard access parallel interface. Data is written to all parts without delay. The non-volatile device provides page-mode operation, providing high-speed access to addresses. Accessing other pages within a page (row) requires CE transitions for low or high address (A16–A2) changes. See the functional truth table on page 17 for a complete description of the read and write modes. Memory Operations Users access 131,072 memory locations, each with 16 data bits, through a parallel interface. The f-ram array is organized into eight blocks, each with 4096 rows. Four columns per row allow quick access to locations in page mode. When the initial address is latched by the falling edge of CE, there is no need to access subsequent column locations to toggle CE. When CE is released from high voltage, precharge begins. Enter now. We pin operation must be toggled on every write. Write data is stored in an immediate array of non-volatile memory, a feature unique to F-RAM called Nordley writes. READ OPERATIONS A read operation begins with the falling edge of CE. A falling edge of ce causes the address to be latched and initiates a memory read cycle if we are high. Data is available on the bus after reaching the access time. When the address is locked the access is complete and a new random location access (different row) may start while CE is still low. The minimum random address cycle time is trc.

Note that, unlike SRAM, the CE boot access time of the FM21L16 is faster than the address access time. The FM21L16 will drive the data bus byte enable (UB, LB) when run experience and at least one run experience are asserted as low upper data bytes are driven when ub is low and low data bytes are driven when lb is low. If OE is asserted after the memory access time, if satisfied, the data bus will be driven with valid data. If operating experience is to assert before completing the memory access, the data bus will not be driven until valid data is available. This feature will minimize invalidation by eliminating data driven to the bus when the operating experience is de-evaluated high and the data bus will remain in the HI-Z state. Write operation In fm21l16, the interval between writing and reading is the same. The FM21L16 supports both CE and WE controlled write cycles. In both cases, addresses A16–A2 are locked to CE. In a CE-controlled write operation, the we signal is low at the beginning of the memory cycle, that is, when CE goes down. In this case, the device starts the memory cycle with a write. This FM21L16 will not drive the data bus as long as we are low regardless of the state of the operating experience. When CE is de-asserted high in a write we control, the memory cycle starts from the falling edge of CE and our signal sometimes falls off later. Therefore, a store cycle begins with a read. Data will drive the bus if it is running low; however, when we are asserted low we control the write timing for write accesses to the array from starting the memory loop. Write access is valid on the rising edge of US or CE, whichever comes first. Valid handwriting operations require the user to meet the access time specification before US or CE leaves. Data setup time is indicated on write access (rising edge of WE or CE). Unlike other non-volatile memory technologies, it has no write latency to F-RAM. Because the underlying memory is the same, the user experience does not experience a delay on the bus. The entire memory operation happens in a single bus cycle. Data polling, a technique used in eeprom does not require determining whether a write is complete.

Page Mode Operation The F-RAM array is organized into eight blocks of 4096 rows each. There are four column address locations per row. Address inputs A1–A0 define the column address to be accessed. An access can start from any column address and another column location can be accessed without toggling the CE pin. For fast access reads, the column address inputs A1–A0 can be changed to the new value after the first data byte is driven onto the bus. A new data byte arrives no later than taap, less than half of the initial read access time. For fast access writes, the first write pulse defines the first write access. When ce is low, subsequent write pulses and new column addresses provide page-mode write access. Precharge Operation A precharge operation is an internal condition where the memory state is ready for a new access. Precharge is initiated by the user by driving the CE signal high. It must be left high for at least the minimum precharge time, tpc. Precharge can also be activated by changing the address above, A16–A2. The current row is accessing the new one. The device automatically detects a higher order address change and begins a precharge operation. The new address is locked and the new read data is at the tAA address for the write cycle, see Figure 14 on page 14. Speeds that can issue random addresses are trc and twc, respectively. Sleep Mode The device includes a sleep mode of operation that allows the user to reach minimum supply current conditions. It enters a low power sleep mode by asserting the zz pin low. Read and write operations must complete before the ZZ pin is falling. When ZZ is low, all pins except ZZ are ignored pins. When the ZZ is de-pressurized, there is some time delay (tzzex) before the user can access the device. If sleep mode is not used, the ZZ pin should be tied to VDD.

The software write-protected 128k×16 address space is divided into eight sectors (blocks) of 16k×16 each. Each sector can be individually software write protected and the settings are non-volatile. A unique address and command sequence invokes write-protected mode. To modify write protection, the system host must issue six read three write commands and one final read command. A specific read address sequence must be provided to access the write-protected mode. Following the read address sequence, the host must write a data byte specifying the desired protection state for each sector. To confirm this, the system must then write the complement of the protection byte immediately after the protection byte. Any errors that occur including reading addresses in the wrong order, issuing a seventh read address, or failing to supplement the protection value will remain write-protected. The write protection state machine monitors all addresses for no action until this particular read/write sequence occurs. During the address sequence, each read will occur as a valid operation and the data at the corresponding address will be driven to the data bus. Any address that is out of sequence will cause the software protection state machine to restart. After the address sequence is complete, the next operation must be a write cycle. The lower data bytes contain the write protection settings. This value is not written to the memory array, so the address is not a concern. Rather, it must be a supplement to the data set for protection before the next cycle. If the complement is correct, the write protection setting will be adjusted. Otherwise, the process aborts and the address sequence starts over. Data value addresses written after the correct 6 will not be entered into memory. The protection data byte consists of 8 bits, each bit is associated with the write protection status of a sector. A data byte must be driven into the lower 8 bits of the data bus, and DQ7-DQ0 set "1" bits to protect the corresponding sector; "0" enables writing for that sector. The following table shows the write protection sector settings with corresponding bits that control write protection.

The SRAM Insert Replacement FM21L16 is designed to replace standard asynchronous SRAM devices without the need for CE to toggle for each new address. CE may remain low for a long time. When CE is low, the device automatically detects the address change and starts a new access. It also allows page mode to run at speeds up to 33 MHz. The diagram shows a pull-up resistor on CE that will keep the pin high during power cycling, assuming the MCU/MPU pin is tri-stated in a reset condition. The pull-up resistor value should be chosen to ensure that the CE pin trace VDD is high enough, so the current drawn when ce is low is an issue. When CE is low and VDD=3.3V

Note that if CE is tied to ground, the user must ensure that we are not low during a power-up or power-down event. If both ce and us are during low power cycles, the data will be corrupted. The diagram shows that we have a pull-up resistor on it, during power cycling, assuming the MCU/MPU pins are in a reset condition. The pull-up resistor value should be chosen to ensure that the WE pin tracks VDD value is high enough so that when we are low, current consumption is not an issue. 10-k When we are at low voltage and VDD=3.3V, the resistor dissipates 330uA.

Note that if CE is tied to ground, the user will forgo executing the software write protect sequence. For applications that require the lowest power consumption, the CE signal should only be active (low) during memory accesses. When CE is low, even the address and control signals are static. When the CE value is high, the device does not exceed the maximum standby current ISB. The ce toggle to low on every address access is perfectly acceptable in the FM21L16. The UB and LB byte select pins are valid for both read and write cycles. They can be used to connect the device as 256K x 8 memory. The upper and lower data bytes can be controlled together with the byte selection. A single byte is enabled or the next higher address line A17 is available from the system processor.