feature

Replaces ADC574 , ADC674 and ADC774; for new designs; complete sampling A/D; reference, clock and; microprocessor interface; fast acquisition and conversion: 8.5 microseconds maximum temperature; eliminates external sample/hold; in most applications Medium; Guaranteed AC and DC performance; Single supply +5V operation; Low power: 120MW max; Packaging options: 0.6" and 0.3" dip, SOIC.

illustrate

The ADS74 is a 12-bit successive approximation. CMOS technology is implemented with low power consumption using an innovative analog-to-digital converter capacitor array (cdac). This is a replacement for ADC574, ADC674 and ADC774 models in most applications, with internal sampling, lower power consumption, and from a +5V supply.

The ADS774 features an internal clock, microprocessor interface, three-state outputs, and internal input ranges of 0V to +10V, 0V to + 20V , ±5V, ±10V. The maximum throughput time is 8.5 microseconds over the entire operating temperature range, including acquisition and conversion. Full user control over the internal sampling function helps eliminate external sample/hold amplifiers in most existing designs. The ADS774 requires +5V, optional -15V does not require +15V power supply Available packages include 0.3" or 0.6" wide 28-pin plastic dips and 28-pin SOICs.

Typical performance curve

At Ta=+25°C, VDD=Vee=+5V; bipolar ±10V input range; sampling frequency 110kHz; unless otherwise specified. All graphs use a 4096-point FFT.

theory of operation

In the ADS774, the advantages of advanced CMOS technology high logic density, stable capacitance, precise analog switching, and Burr Brown's state-of-the-art laser trimming technology combine to produce a fast, low-power analog-to-digital converter with internal sample/hold .

A charge redistribution successive approximation circuit converts the analog input voltage into a digital word.

Figure 1 shows a simple example of a charge redistribution A/D converter with only 3 bits.

Lock s1 in the "r" or "g" position. Similarly, a second approximation is by connecting S2 to reference and S3 to GND, and latching S2 based on the output of the comparator. After three successive approximation steps, the voltage level of the comparator will be within 1/2LSB of GND, and the digital word representing the analog input can be determined from the positions of S1, S2, and S3.

operate

input scaling

Precision laser-trimmed scaling resistors on the input divide the standard input range (0V to +10V, 0V to +20V, ±5V, or ±10V) into levels compatible with the CMOS characteristics of the internal capacitor array.

sampling

When sampling, the capacitor array switch of the msb capacitor (s1) is in the "s" position so that the charge on the msb capacitor is proportional to the voltage level of the analog input signal. The remaining array switches (s2 and s3) are set to position "g". Switch S is closed, setting the comparator input offset to zero.

convert

When a convert command is received, switch S1 is opened to capture the charge on the MSB capacitor proportional to the analog input level at the time of the sampling command, switch S is opened to float the comparator input Now, by placing switches s1, s2 and s3 Connected to position "r" (connected to reference) or "g" (connected to GND), the charge trapped in the capacitor array can move between the three capacitors in the array, changing the voltage developed at the comparator input.

During the first approximation, the MSB capacitance is connected to the reference through switch S1, while switches S2 and S3 are connected to GND. Depending on whether the comparator output is high or low, the logic will operate basically. Figure 2 shows the minimum connections required to operate the ADS774 in the basic ±10V range in control mode (discussed in detail in later chapters). The falling edge of the convert command (minimum 25ns low pulse on pin 5) switches the ADS774 input to hold and initiates the conversion. Pin 28 (status) will output high during conversions and will only go down after the conversion is complete and the data has been latched on the data output pins (pins 16 to 27). Therefore, the falling edge of state on pin 28 can be used to read data from the transition. Additionally, during a conversion, the status signal puts the data output pins in a high Z state and inhibits the input line. This means that pulses on pin 5 are ignored, so no new conversions can be initiated during a conversion, whether due to miscellaneous The scattered signal is still to shorten the period of the ADS774.

The ADS774 will start acquiring new samples after the conversion is complete (even before the state output has dropped) and will track the input signal until the next conversion begins. The ADS774 is designed to complete the conversion with a maximum of 8.5 microseconds over the entire operating temperature range and acquire the new signal accurately so that the conversion can be performed at the full 117KHz.

Controlling the ADS774

The Burr Brown ADS774 can be easily interfaced to most microprocessor systems and other digital systems. The microprocessor can have full control of each conversion, or the converters can operate in stand-alone mode, controlled only through the R/C input. Full control includes selecting an 8-bit or 12-bit conversion cycle, starting the conversion, and reading the output data when ready, selecting 12 bits at a time, or selecting 8 MSB bits followed by 4 LSB bits in left-justified format. The five control inputs (12/8, CS, A0, R/C and CE) are all TTL/CMOS compatible. The functions of the control input are shown in Table 2.

Independent operation

For stand-alone operation, the control of the converter - is connected by a control line to R/C. In this mode, CS and A0 are connected to digital common, and CE and 12/8 are connected to +5V. The output data is shown in Figure 2 for basic ±10V operation.

Rendered as a 12-bit word. Standalone mode is used in systems that contain dedicated input ports that do not require full bus interface functionality.

A conversion is initiated by a high-to-low transition of R/C. The tri-state data output buffer is enabled when R/C is high and state is low. Therefore, there are two possible modes of operation; data can be read by a positive or negative pulse state on the R/C. In both cases, the R/C pulse must be held low for at least 25ns.

Figure 3 shows the timing of the R/C pulse going low and returning high during a conversion. In this case, the tri-state output goes into a high impedance state in response to a falling edge on R/C and enables external data transfer after the conversion is complete. access.

Figure 4 shows the timing when using a positive R/C pulse. In this mode, the output data from the previous converter - SION is enabled when R/C is high. A new conversion begins on the falling edge of R/C, and the tri-state output returns to a high-impedance state until the next high R/C pulse.

Full control operation conversion length

Conversion length (8-bit or 12-bit) is determined by the state of the A0 input, which is latched when a conversion is received to start a conversion (described below). If A0 is latched high, the conversion continues 8 bits. If A0 is low, it will occur Full 12-bit conversion If all 12 bits are read after an 8-bit conversion, the 4LSB (DB0-DB3) will be low (logic 0). a0 is latched because it also participates in enabling the output buffer. No other control inputs are locked.

conversion starts

The converter initiates a conversion on any of the three logic inputs (CE, CS, and R/C) based on conversion, as shown in Table III. The transition is initiated by the last of the three logic inputs to reach the desired state, so all three logic inputs can be dynamically controlled. All three can change state at the same time if necessary, and the nominal delay time is the same regardless of which input actually starts transitioning. If a specific input is required to establish the actual start of a conversion, then the other two inputs should be stable for at least 50ns before the critical input transitions. The timing relationship for the start of the transition timing is shown in Figure 5.

The status output indicates the current state of the converter by being high only during the conversion period. During this period, the tri-state output buffer remains in a high impedance state, so data cannot be read during the conversion period. During this period, the three numbers that control the conversion Additional transitions entered will be ignored, so transitions cannot be prematurely terminated or restarted. However, if a0 changes state after the transition has started, any additional start transition transitions will lock in the new state of a0, potentially causing the transition to have a different transition length. Correct (8 bits versus 12 bits).

read output data

After a conversion is initiated, the output data buffer remains in a high-impedance state until the following four logic conditions are met simultaneously: R/C high, state low, CE high, and CS low. After these conditions are met, according to the input 12/8 and a0.

In most applications, the 12/8 input will be hardwired in a high or low condition, although it is fully ttl and cmos compatible, and if de-since 12/8 is high, all 12 output lines (DB0-DB11 ) are simultaneously enabled to transfer a complete word of data to a 12-bit or 16-bit bus. In this case, the a0 state is ignored when reading data.

When 12/8 is low, the data is presented as two 8-bit bytes, and selection of the byte of interest is done in the read cycle through the A0 state. When a0 is low, the byte address contains 8msb. When a0 is high, byte addressing consists of the 4lsb from the conversion, followed by four logical zeros forced by the control logic. The left-aligned format of two 8-bit bytes is shown in Figure 7. The connection of the ADS774 to the 8-bit bus is used for data transfer, as shown in Figure 8. The design of the ADS774 ensures that the a0 input can be switched at any time without damaging the converter; the outputs tied together in Figure 8 cannot be enabled at the same time. The a0 input is normally driven by the least significant bit of the address bus, allowing output data words to be stored in two consecutive memory locations.

S/H control mode and ADC774 emulation mode

Emulation mode allows the ADS74 to be dropped into most existing ADC77 4 sockets without requiring changes to other system hardware or software. In existing sockets, the analog input is held stable during the transition so that precise transitions can take place, but the input can change rapidly at any time before the transition begins. Emulation mode uses the stability of the analog input during conversion to acquire and convert at a maximum of 8 s (temperature above 8.5 μs). In fact, the throughput of the system can be increased because the input to the ADS74 can start spinning before the end of the conversion (after the acquisition time), which is not possible with the existing ADC77S.

The provided control modes allow full use of the internal sample/hold and no external sample/hold is required in most applications. In contrast to systems using separate sample/hold and A/D, the ADS774 in control mode also does not require one of the control signals, usually a conversion command. A command to put the internal sample/hold into hold also initiates a conversion, reducing time constraints in many systems.

The basic difference between the two modes is the assumptions made about the state of the input signal before and during the transition. These differences are shown in Figure 9 and Table VI. In control mode, it is assumed that the signal does not change faster than the tracking speed of the ADS774 during the required acquisition time of 1.4 microseconds. After the convert command arrives, no assumptions are made about the input level because the input signal is sampled and the conversion begins immediately after the convert command. This means that the convert command can also be used to switch input multiplexers or change the gain on a programmable gain amplifier , allowing the input signal to settle before the next acquisition at the end of the conversion. Since aperture shake is minimized in control mode, high input frequencies can be converted without external sample/hold.

In emulation mode, a delay time is introduced between the conversion command and the start of the conversion to give the ADS774 enough time to acquire the input signal before conversion. This increases the effective aperture delay time from 0.02 microseconds to 1.6 microseconds, but allows the ADS774 to Replacing the ADC774 in most circuits without additional changes In designs where the inputs to the ads774 change rapidly within 200ns before the conversion command, system performance can be improved by delaying the conversion command by 200ns.

When using the ADS74 in emulation mode to replace an existing converter in an existing design, the sample/hold amplifier usually precedes the converter. In these cases, the convert command does not require an additional delay before converting, and the existing sample/hold is not over-rotated when going from sample mode to hold mode.

In both modes, as soon as the conversion is complete, the internal sample/hold circuit starts spinning to track the input signal.

Install

Layout Considerations

The analog (pin 9) and digital (pin 15) commons are not connected together inside the ADS774, but should be connected together as close as possible to the analog common ground plane under the converter on the unit and board assembly side. Also, the wide wire pattern should go directly from pin 9 to the analog power common, and a separate wide wire pattern from pin 15 to the digital power common.

If a single point system common cannot be established directly at the converter, then at the converter, pins 9 and 15 should still be connected together. Then, a single wide conductor pattern connects these two pins to the system common. In both cases, the common return of the analog input signal should be referenced to pin 9 of the ADC. This prevents any voltage drop that might occur in the power common return in series with the input signal.

The speed of the ADS774 requires special attention to any unused input pins. For 10V input ranges, pin 14 (20V range) must be disconnected, and for 20V input ranges, pin 13 (10V range) must be disconnected. In both cases, unconnected inputs should be shielded with a ground plane to reduce noise pickup.

In particular, unused input pins should not be connected to any capacitive loads, including high-impedance switches. Even a small amount of pF on unused pins will reduce acquisition time.

Coupling between analog input lines and digital lines should be minimized through careful layout. For example, if lines must intersect, they should intersect at right angles. Parallel analog and digital lines should be separated from each other by a pattern connected to a common line.

If external full-scale and offset potentiometers are used, the potentiometers and associated resistors should be placed as close as possible to the ADS774.

On the ADS774, +5V (to pin 1) is the only supply required for proper operation. Pin 7 is not connected internally, so there is no problem in the existing ADC77 4 socket, which is connected to +15V here. Pin 11 (VEE) is used only as a logic input to select the control mode of the sampling function as described above. When used in an existing ADC74 socket, -15V on pin 11 selects ADC74 emulation mode. Since pin 11 is used as a logic input, it is immune to typical power supply variations.

The +5V supply should be bypassed with a 10µF tantalum capacitor close to the converter to facilitate noise-intrusive operation, as shown in Figure 2. Noise on the power line can degrade the performance of the converter. Noise and spikes in switching power supplies are particularly troublesome.

range join

The ADS774 offers four standard input ranges: 0V to +10V, 0V to +20V, ±5V, or ±10V. Figure 10 and Figure 11 show the necessary connections for each range, as well as optional gain and offset trim circuits. If a 10V input range is required, the analog input signal should be connected to pin 13 of the converter. Signals in the 20V voltage range are required to be connected to pin 14 in both cases, the other pin is left unconnected. Pin 12 (bipolar offset) connects to pin 9 (analog common) for unipolar operation, or pin 8 (2.5V reference output), or an external reference, full scale and offset adjustment for bipolar operation as described below.

The input impedance of the ADS774 is typically 50kΩ in the 20V range and 12kΩ in the 10V range. This is significantly higher than the traditional ADC774 architecture and reduces the loading of the input source in most applications.

input structure

Figure 12 shows the resistive divider input structure of the ADS774. Since the input drives the capacitor in the CDAC during acquisition, the input is looking for a high impedance node compared to the traditional ADC774 architecture, where the resistive divider network looks at virtual ground Comparator input node.

To understand how this circuit works, it is necessary to know that the input range of the internal sampling capacitor is 0V to +3.33V, and the analog input of the ADS774 must be converted to this range. The unipolar 20V range can be used as an example of how a divider network works. In 20V operation, the analog input goes to pin 14. Pin 13 is unconnected and pin 12 is connected to the analog common pin 9. It is clear from Figure 12 that the input to the capacitor array will be the analog input voltage on pin 14 divided by the resistor network (42kΩ + 42kΩ 10.5kΩ). The 20V input at pin 14 is split into 3.33V at the capacitor array, and the 0V input at pin 14 is 0V at the capacitor array.

The main effect of the 10kΩ internal resistor on pin 12 is to provide the same offset adjustment response as the traditional ADC774 structure without changing the external trim value.

Single supply operation

The ADS774 is designed to operate from a single +5V supply and handles all unipolar and bipolar input ranges, whether in control mode or emulation mode, pin 7 is not connected internally as described above. This is where +12V or +15V is provided by a conventional ADC774S. Pin 11 is the -12V or -15V power supply input on the legacy ADC774S and is only used as a logic input on the ADS774. There is a resistor divider inside pin 11 to reduce this input to the correct logic level within the ADS774, this resistor will increase the power dissipation of the ADS774 by 10MW to 15MW when -15V is provided on pin 11. To minimize power dissipation in the system, pin 11 can simply be grounded (for emulation mode) or tied to +5V (for control mode). The ADS774 requires no additional modifications to operate from a single +5V supply.

calibration

Optional external full scale and offset adjustment

For unipolar and bipolar operation, the offset and full-scale errors can be trimmed to zero using external offset and full-scale trim pots connected to the ADS774, as shown in Figures 10 and 11.

Calibration Procedure - Unipolar Range

If external adjustment of full scale and offset is not required, replace R2 in Figure 10 with a 50Ω 1% metal film resistor and connect pin 12 to pin 9, omitting other adjustment components.

If adjustment is required, connect the converter as shown in Figure 10 to scan the input through the terminal transition voltage (0V+1/2LSB; +1.22mV for 10V range, +2.44mV for 20V range), resulting in output code DB0 on (high) adjustment Potentiometer R1 until DB0 turns on and off alternately with all other bits off. Then, adjust full scale by applying an input voltage of negative 3/2lsb of nominal full scale, which should be such that all bits are connected Pass. For the 10V range, this value is +9.9963V; for the 20V range, this value is +19.9927V. Adjust potentiometer r2 until bits db1db11 turn on and db0 turns on and off.

Bipolar Span Calibration Procedure

If external adjustment of full scale and bipolar bias is not required, replace the potentiometer in Figure 11 with a 50Ω, 1% metal film resistor.

If adjustment is required, connect the converter as shown in Figure 11. The calibration procedure is similar to the steps described above for unipolar operation, except that the offset adjustment is performed with the input voltage above 1/2LSB of the negative full-scale value (–4.9988V for ±5V range, –9.9976V for ±10V range). Adjusting r1 makes db0 turn on and off with all other bits off. To adjust full scale, apply a DC input signal 3/2LSB below the nominal full scale value (+4.9963V for ±5V range, +9.9927V for ±10V range) and adjust R2 of DB0 to Turns on and off with all other bits turned on.