256kbit (32k×8) serial (spi) f-ram

Features: 64 kbit/256 kbit Ferroelectric Random Access Memory (F-RAM) 10064 ; logically organized as 8K×8 ( FM3164 )/32K×8 (FM31256) high endurance 100 trillion (1014) read/write 151 years Data retention period (see data retention and endurance table) nodelay 8482 ; written in advanced high reliability ferroelectric process high integration device can replace multiple parts serial non-volatile memory real time clock (RTC) low voltage reset early power down Warnings/NMI Two 16-bit event counters Serial number with write lock for security Real-time clock/calendar Backup current at 2 V: 1.15∏A, +25∏C seconds, in BCD format for centuries Tracking spanning 2099 Year of the year software calibrated using standard 32.768 kHz crystal (6 pF) ❐ Supports battery backup or capacitor processor Companion VDD and watchdog Active low reset output Programmable low VDD reset trip point ❐ Manual reset filtering and denoising available Programmable Watchdog Timer ❐ Dual Battery Event Counter Tracks System Intrusion or Other Events Power Failure Interrupt Comparator 64-bit Programmable Serial Number with Lock kHz traditional timekeeping RTC, supervisor device controlled via I2C interface Select pins for up to 4 memory devices Low power consumption 1.5mA at 1MHz Active current 150µA Standby current Operating voltage: VDD=2.7 V to 5.5 V Industrial temperature: – 40°C to +85°C? ? 14-pin Small Outline Integrated Circuit (SOIC) package compliant with Restriction of Hazardous Substances (RoHS)

Functional overview: fm3164/fm31256 devices integrate f-ram memory and the most commonly used processor-based functional systems. Key features include non-volatile memory, real-time clock, low VDD reset, watchdog timer, non-volatile event counter, lockable 64-bit serial number area and general availability for power failure (NMI) interrupts or any other purposes. fm3164/fm31256 are 64 kbit/256 kbit non-volatile memory using advanced ferroelectric process. Ferroelectric random access memory or F-RAM is non-volatile ram-like read and write operations. This memory is really not volatile and not battery powered. It provides reliable data retention for 151 years while eliminating the complexity, overhead and system-level reliability issues caused by other non-volatile memory. The FM3164/FM31256 can support 1014 read/write cycles, or 100 million times more write operations than EEPROM cycles. Real Time Clock (RTC) in BCD format. It can be permanently powered from an external backup voltage source, battery or capacitor. This timer uses a common external 32.768khz crystal and provides a calibration mode that allows software to adjust the timing accurately. Processor Companion includes commonly required CPU support features. Supervisory functions include a reset output controlled by a low VDD condition or a watchdog-controlled signal timeout when VDD falls below a programmable threshold, and remains active after 100 ms when VDD is above the trigger point. Programmable watchdog timer from 100ms to 3s The watchdog timer is optional, but if enabled, it will assert the reset signal for 100ms if not restarted by the host before timing out. The flag bit indicates the reset source. The comparator on the pfi connects the external input pin to the onboard 1.2V reference. This is useful for generating power failure interrupts (NMIs), but can be used for any purpose. This series also includes a programmable 64-bit serial number that can be locked so that it cannot be changed. In addition, it provides a battery backup event counter that tracks rising or falling edges detected on dedicated input pins.

Introduction: The fm3164/fm31256 devices combine a serial non-volatile RAM with a real-time clock (RTC) and a processor companion. Companion is a highly integrated peripheral that includes a processor manager, comparator warning for early power down, a non-volatile event counter and a 64-bit serial number. The FM3164/FM31256 integrate these complementary functions under a common interface in a single package. The product is organized as two logical devices. The first is the memory and the second is the buddy, including all remaining functions. From the system's point of view, on the serial bus are two separate devices with unique IDs. Memory is organized as independent non-volatile I2C memory using standard device ID values. Real time clock and access manager functions using separate I2C device IDs. This allows maintaining recently used memory addresses. Clock and supervisor functions are controlled by 25 Special Function Registers. The RTC and event counter circuits are maintained by the power supply on the VBAK pin, allowing them to be powered from the battery or back up capacitors when VDD falls below a set threshold. Each functional block is described below. Memory structure The memory size of the FM3164/FM31256 devices is available 64kbit/256kbit The device uses double-byte addressing for the memory portion of the chip This makes the device software compatible with separate memory counterparts, but they are compatible throughout the family . The storage array is logically organized as 8192×8 bits/32768×8 bits, using the industry standard I2C access interface. The memory uses f-ram technology. Therefore, it can be thought of as RAM, and at the speed of the I2C bus, there is no delay for write operations. It also provides effective unlimited write endurance. Non-volatile memory technology describes the I2C protocol memory array can be write protected by software. The address cannot be written to and the I2C interface will not be able to acknowledge any data to the protected address. The function registers that contain these bits are described in particular detail below.

Processor Companion In addition to non-volatile RAM, the FM3164/FM31256 integrates a real-time clock and highly integrated processor companion accompaniment including a low VDD reset, a programmable watchdog timer, battery powered event counter for early power failure Comparator for detection or other uses and a 64-bit serial number. Processing Supervisor The supervisor provides two basic functions of the host processor: power failure detection and a watchdog timer to evade software lockout conditions. The FM3164/FM31256 has a reset pin (RST) for power failure, power up and software lockout. It is an open channel with a weak internal pull up to VDD output which allows other reset power lines or connections to the first pin. When VDD is higher than the programming trigger point, the RST output is weakly pulled to VDD. If VDD drops below the reset trip point voltage level (VTP), the RST pin will be depressed and it will remain low until VDD drops too low for VRST level circuit operation. When VDD rises above vtp again, rst continues to drive low for at least 100 ms (trpu) to ensure a reliable system reset level under reliable vdd. When trpu is satisfied, the first pin will return to the weak high state. When rst is asserted, serial bus activity is locked out even if a transaction occurs while VDD drops below VTP. A memory operation that starts when VDD is higher than VTP is done internally. The table below shows how bits VTP (1:0) control a low VDD reset. They are located in bits 1 and 0 of register 0Bh. When VDD is below the selected VTP, the reset pin will be driven low and the I2C interface and F-RAM array will be locked out. Figure illustrates the response to low video displays.

The watch timer can also be used to drive the active reset signal. is a free running programmable timer. This timeout can be software programmed between 100 ms and 3 second in 100 mm increments via a 5-bit non-volatile register. Program settings as min and min. temperature according to operating specifications. The tea monitor has two additional control operations, an available watch bit (WD) and the time recovery bit both must be set while the monitor must be set. The time in command drives the RST activation. The reset event time will automatically resume at the reset edge pulse. If WDE==0, the watchdog time will run, but the watchdog fault will not be set because the vanquished low-income WTO flag will be Set, indicating a watchdog fault. This setting is used when using middle. Software Development If the developer doesn't want to drive the instructions to set the maximum time setting Disable the Counter to Save Power. The second control is Nibble that restarts the time preventing a reset. The time should stay the same after the time value has changed. Register 0AH, bit 4: The operable monitor is 7 bits. The Watchers are trapped. Write pattern 1010b to the next Nibble in register 09H. Writing to this mode also results in a new time load. Other modes of writing the value to this address will not affect its operation. Note that the observation time is free. In preference to creating it, the user should press the time limit described above. This guarantees that all timings will be in place immediately. The monitor fails when VDD is below VTP after Enabling.

Manual reset RST is a bidirectional signal that allows the FM3164/FM31256 to filter and debounce the manual reset switch. The RST input detects an external low state and drives the RST signal low for 100ms.

Reset Flag In a reset condition, a flag bit will be set to indicate the source of the reset. A low vdd reset is indicated by the por flag, register 09H, bit 6. A watchdog reset is indicated by the WTR flag, register 09h, bit 7. Note that the flags are set internally in response to a reset source, but they must be cleared by the user. When reading registers, if both of these occur after the last time the user cleared them. An early power-down comparator can provide early power-fail warning to the processor before VDD is out of specification. The comparator is used to create a power failure interrupt (NMI). This can be done through a resistor divider. The application circuit is shown below.

Compare the voltage on the pfi input pin to the onboard 1.2v reference. When the pfi input voltage is below this threshold, the comparator will drive the calibration/power factor output pin to the low country. The comparator has a 100 mV (max) hysteresis to reduce noise sensitivity, only for rising pfi signals. Because of a falling pfi edge, there is no hysteresis. The comparator is a general purpose device and its application is not limited to the NMI function. The comparator is not integrated into the special function register unless it shares its output pins with the calibration output. When the RTC calibration mode is invoked by setting the calibration bit (register 00H, bit 2), the CAL/PFO output pin will use a 512 Hz square wave and the comparator will be ignored. Since most users only invoke calibration mode during production, this pair uses comparators. Note: The maximum voltage at the comparator input PFI is limited to 3.75 V under normal operating conditions. Event Counters The FM3164/FM31256 provide the user with two battery-backed event counters. Input pins CNT1 and CNT2 are programmable edge detectors. A 16-bit counter per clock. When the edge occurs, the counters will increment their respective registers. Counter 1 is located in registers 0dh and 0eh, and counter 2 is located in registers 0fh and 10h. These register values can be read when VDD is higher than VTP, and they will increase over time as a valid VBAK supply is provided. To read, set the RC bit (register 0ch, bit 3) to 1. This is a snapshot counter byte for four photos, allowing a stable value during reading even if the count occurs. Registers can be used to allow counters to be cleared or initialized by the system. Counting is blocked during write operations. The two counters can be cascaded by setting cc to create a single 32-bit counter control bit (register 0ch, bit 2). When cascaded, the CNT1 input will cause the counter to increment. CNT2 is not used in this mode and should be connected to ground.

The control bits for the event count are located in register 0ch. Counter 1 polarity is bit c1p, bit 0; counter 2 polarity is bit c2p, bit 1; cascade control is CC, bit 2; read counter bit is RC, bit 3. The polarity bit must be set before setting the counter value. If the polarity bit is changed, the counter may inadvertently increment. If countersink pins are not used, tie them to the ground. The serial number provides a memory location for writing the 64-bit serial number. It is a writable block of non-volatile memory that can be accessed by the user once the serial number is set. The 8-byte data and lock bits are accessed through the processor's device ID. So the serial number area is separate from the memory array. The serial number register can be written an unlimited number of times, so these locations are general purpose memory. However, once the lock bit is set, the value cannot be changed and the lock cannot be removed. Once locked the serial number register can still be used by the system. The serial number is located in registers 11h to 18h. The lock bit is snl (register 0bh, bit 7). Setting the snl bit to '1' will disable writing to the serial number register, and the SNL bit must not be clear. Real Time Clock Operation A real time clock (RTC) is a timekeeping device that can be permanently powered by a battery or capacitor. It provides a software calibration function that allows high accuracy. rtc consists of oscillator, clock divider and register user access system. It will have a 32.768khz time base, providing a minimum resolution of seconds (1 Hz). Static registers provide the user with time values. It includes registers for seconds, minutes, hours, day of the week, date, month and year. The block diagram illustrates the RTC functionality. The user registers are synchronized with the timer core using the r and w bits in register 00h described below. Changing the R bit from '0' to '1' goes from the core into a holding register that can be read by the user If a timer update is pending while r is set, then the core will do the update before loading the user registers. The register is frozen until the R bit is cleared to '0'. R is used to read the time. Setting the W bit to '1' clears the lock user register to '0' to load the timing core with the value in the user register. The W bit is used to write a new time value. The user should ensure that invalid values such as ffh are not loaded into the timing registers. Updates to timing cores are made continuously unless locked.

The backup power real time clock/calendar is permanently powered. The VDD pin will drop when the main system is powered off. When VDD is less than 2.5 V, the RTC (and event counter) will switch to the backup power supply on VBAK. The clock operates at very low current to maximize. battery or capacitor life. However, in conjunction with the clock function of F-RAM memory, data is not lost regardless of the backup power source. IBAK current varies with temperature and voltage (see DC Electrical Characteristics table). The image below shows IBAK as a function of vbak. These curves are useful for calculating backup times when capacitors are used as VBAK sources.

The minimum vbak voltage varies linearly with temperature. This user can expect a minimum VBAK voltage of 1.23 V at +85°C and 1.90 V at -40°C. Test limit is 1.55 V at +25°C. Note: Minimum VBAK voltages are characterized by -40°C and +85°C, but are not 100% tested.

Trickle Charger To facilitate capacitor backup, the VBAK pin can optionally provide a trickle charge current. When the VBC bit (Register 0Bh, Bit 2) is set to '1', the VBAK pin will source approximately 15µA until VBAK. to VDD or 3.75 V, whichever is less. In 3V systems, the capacitor is charged to VDD without an external diode. Resistive chargers In 5V systems, it provides the same convenience and prevents the user from exceeding the VBAK maximum voltage specification. When not using a battery, the VBAK pin should be tied according to the following conditions: For 3.3V systems, VBAK should be tied to VDD. This assumes that VDD does not exceed 3.75 V. For a 5 V system, connect a 1µF capacitor to VBAK and turn on the trickle charger. The VBAK pin will regulate the internal charging backup voltage to around 3.6 V. VBAK should not be connected to 5 V as the VBAK (max) specification will be exceeded. A 1µF capacitor will keep the function working for about 1.5 seconds. Although VBAK may connect to VSS, this is not recommended if using a companion. No companion function will operate below 2.5 volts Note: Systems using Lithium batteries should clear the VBC bit to '0' to prevent battery charging. The VBAK circuit includes an internal 1K series resistor as a safety element. When the calibration bit in register 00h is set to '1', the clock enters calibration mode. In calibration mode, the calibration/power factor output pins are temporarily unavailable for the calibration function and the power-fail output is dedicated. The counter is digitally corrected by applying the frequency based error. In this mode, the CAL/PFO pin drives a square wave at 512 Hz (nominal).

Any measured deviation from 512 Hz becomes a timing error. The user converts the measured error and writes the appropriate correction value to the calibration register. The correction factors are listed in the table below. Positive ppm errors require negative adjustment to remove pulses Negative ppm errors require correction of positive increase pulses. Positive ppm adjustments have the CAL (sign) bit set to '1', while negative ppm adjustments have CAL set to '0'. After calibration, the clock will have the maximum value. The monthly error when calibrated is ±2.17 ppm or ±0.09 minutes of temperature. Calibration settings are stored in F-RAM, so there is no loss of backup source failure. It is in register 01h with bits cal (4:0). Only when the cal bit is set to "1". To exit calibration mode, the user must clear the calibration bit to '0'. When the CAL bit is "0", the CAL/PFO pin will resume the power-down output function. Crystal Oscillators Crystal oscillators are designed to use a 6 pf crystal without the need for external components such as loading capacitors. The FM3164/FM31256 devices have built-in loading capacitors optimized for use with 6 pf crystals. If a 32.768 kHz crystal is not used, an external oscillator can be connected to the FM3164/FM31256. Apply the oscillator to the X1 pin. Its high and low voltage levels can be rail-to-rail or amplitudes as low as about 500 mV p-p to To ensure proper operation, a DC bias must be applied to the X2 pin. It should be centered between the high and low pins of the X1 pin. This can be achieved with a voltage divider.

In this example, r1 and r2 are chosen so that the X2 voltage is centered on the X1 oscillator drive level. If you prefer to avoid DC currents, you can choose to drive a reverse clock inverter with an external clock and X2, using CMOS. Layout Recommendations x1 and x2 transistor pins using high impedance circuits connected to these pins will cause the oscillator to be disrupted by noise or additional loading. To reduce RTC clock error switching noise from the signal, a guard ring must be placed around these pads to ground. The SDA and SCL traces should be drawn from the X1/X2 pads. The x1 and x2 trace lengths should be less than 5 mm. The best ground plane to use is the backside or inner board layer. See layout example. Red is the top layer and green is the bottom layer.