Features Used to configure Cylinx Gas Low Power Advanced CMOS NOR Flash Process Lasts 20,000 Program/Erase Cycles Operates Over Industrial Temperature Range (-40°C to +85°C)
IEEE Std 1149.1 /1532 Boundary Scan (JTAG) support for programming, prototyping and testing The jtag command for standard fpga enables cascading storage of longer or multiple bit streams Dedicated boundary scan (JTAG) I/O power supply (VCCJ )
I/O pins are compatible with the following voltage levels 1.5V to 3.3V using Xilinx Alliance ISE and base ISE series software packages
XCF01S /XCF02S/XCF04S
-3.3V supply voltage
- Serial FPGA configuration interface (up to 33 MHz)
-Small VO20 and VOG20 available
Package.
XCF08P/XCF16P/XCF32P
-1.8V supply voltage
- Serial or parallel FPGA configuration interface (up to 33 MHz)
- Available in small VO48, VOG48, FS48, and fsg48 packs
- Built-in data decompressor compatible with Xilinx Advanced compression technology

illustrate
xilinx introduces the programmable configuration proms in the platform flash series system. Available in 1 to 32 megabit (mbit) densities, these proms provide an easy-to-use, cost-effective, and reprogrammable method for storing large Xilinx FPGA configuration bitstreams. This platform Flash PROM family includes 3.3V and xcfxs prom and 1.8v xcfxp prom. The xcfxs version includes 4-Mbit, 2-Mbit, and 1-Mbit PROMs that support serial master and slave serial fpga configuration modes. The XCFxxP version includes 32mbit, 16mbit and 8mbit prom supporting master serial, slave serial, master select map and slave select map fpga configuration modes. The members of the platform flash prom series and the supported functions are shown in Table 1.

xcfxs platform flash prom block diagram

xcfxp platform flash prom block diagram

When the fpga is in master serial mode, it generates a configuration clock that drives the PROM cf high, a short access time after aCE and OE are enabled, and the data is available on the PROM data (D0) pin connected to the DIN pin of the FPGA New data is briefly accessible after each rising clock edge. The fpga generates the appropriate number of clock pulses to complete the configuration.
When the FPGA is in slave serial mode, both the PROM and the fpga are clocked by an external clock source, or alternatively, for the xcfxxp prom only, the prom can be the configuration clock used to drive the fpga. The xcfxxp version of the platform flash prom also supports master select map and slave select map (or slave parallel) FPGA configuration modes. When the FPGA is in the master select mapping mode, the FPGA generates the configuration clock that drives the PROM. When the FPGA is in the slave state and selects the mapping mode, the external oscillator will generate the configuration clock that drives the prom and can optionally use the fpga or xcfxxp prom to drive the fpga. Busy with cf high, after ce and oe are enabled, data is available on the PROMs data (D0-D7) pins for a short access time after each rising clock edge. Data is presented on the following rising edge of CCLK. A free-running oscillator can be used in parallel/slave SelecMAP mode on the slave.
Additional advanced features are available in the XCFxxP version of the platform Flash PROM. A built-in data decompressor supports the use of compressed prom files, and design revisions allow multiple design revisions to be stored in a single prom or across multiple proms. For design revisions, external pins or internal control bits are used to select the active design version.
Multi-platform Flash PROM devices can be cascaded to support larger profiles required when targeting larger fpga devices or targeting multiple fpgas daisies Locked together when using advanced features xcfxxp platform flash prom such as design modification, cross-stage Linked prom programming files can only contain xcfxp proms only. If the advanced xcfxp feature is not enabled, the cascade chain can include xcfxxp and xcfxs proms.

Programming In-system programming In-system programmable proms individually, or two or more can be daisy-chained together and programmed in-system via the standard 4-pin JTAG protocol as shown in Figure 3. In-system programming provides fast and efficient design iterations and eliminates unnecessary packaging handling or device docking. This programming data sequence is transferred to the device using xilinx impact software and xilinx download cable, a third-party JTAG development system, a JTAG-compatible board tester, or a simple microprocessor interface to emulate the JTAG instruction sequence. This impact software also outputs serial vector format (SVF) file for use with any tool that accepts the svf format, including automated test equipment. During the system programming process, the CEO's output was pushed up. All other outputs are kept in a high-impedance state or programmed within the system during in-system programming fully within the recommended operating voltage and temperature ranges.
1/2/4mbitxcfxs platform Flash PROMs programming algorithm in runexp/reset system caused internal device reset resulting in runexp/reset pulse low.
Externally programmed xilinx reprogrammable proms are also available through the xilinx multiprocessor desktop tool or third-party device programmers. This provides additional flexibility of use.
Options for future enhancements and design changes with pre-programmed devices programmable within the system.
Reliability and Endurance Xilinx in-system programmable products guarantee an in-system program/erase endurance level of 20,000 cycles and a minimum 20-year data retention period. Each device meets all functional, performance and data retention specifications within this endurance limit.
Design Security Xilinx System Programmable Platform Flash PROM devices integrate advanced data security features to prevent unauthorized FPGA programming data from being read via JTAG. xcfxp proms can also be pro programmed to prevent accidental writes via jtag.
Read Protection The user can set the read protect security bit to prevent the internal programming mode from being read or copied via JTAG. Read protection does not block write operations. For xcfxs prom, the read-protect security bit will be set for the entire device, and resetting the read-protect security bit requires erasing the entire device. For xcfxxp prom the read protection security bit can be set for individual design revisions, and resetting the read protection bit requires removal of the specific design revision.

IEEE1149.1 Boundary Scan (JTAG) Platform The Flash PROM family is compatible with IEEE Standard 1532 in-system programming and is fully compatible with IEEE Standard 1149.1 Boundary Scan, also known as JTAG, which is a subset of IEEE Standard 1532 Boundary Scan.
Test Access Ports (TAPs) and registers are provided to support all required boundary scan instructions, as well as many optional instructions specified by the IEEE standard. 1149.1. In addition, the JTAG interface is used to implement in-system programming (ISP) to facilitate configure, erase and verify operations on the platform flash programmable read-only memory device Table 6 lists the required and optional platform flash supported boundary scan Instruction dance. Refer to IEEE Standard 1149.1 for specification of boundary scan architecture and required and optional descriptions.
The instruction register (ir) of the instruction register platform flash prom connects the TDI and TDO scan order during the instruction. In preparation for the instruction scan sequence, the instruction register is loaded in parallel with a fixed instruction capture pattern. This mode is changed to go to TDO (LSB first) while moving the instruction to the instruction register from TDI. xcfxs Instruction Register (8-bit wide) The instruction register (IR) of the xcfxs PROM is 8-bits wide, during the instruction scan sequence. The detailed composition of this instruction to capture mode out of the xcfxs device includes IR [7:0]. IR[7:5] are reserved bits, set to logic "0". The isc status field ir[4] contains logic "1" if the device is currently in system configuration (ISC) mode; otherwise, it contains logic "0". The security domain, ir[3], contains a logic "1" if the device has been programmed with the security option turned on; otherwise, it contains a logic "0" IR[2] is not used and is set to "0" for the remainder as per IEEE As defined by standard 1149.1, IR[1:0] is set to "01". xcfxp instruction register (16 bits wide) The instruction register (ir) of the xcfxxp prom is 16 bits wide and is connected between tdi and tdo in the instruction scan sequence.
Command capture mode from xcfxp out of the device includes IR[15:0]. ir[15:9] are reserved bits and are set to logic "0". The ISC error field IR[8:7] contains "10" when the ISC operation was successful; otherwise the In-System Configuration (ISC) operation failed. The erase/program (er/prog) error field, ir[6:5], contains "10" when the erase or program operation is successful; oth when the erase or program operation fails, enter "01" this erase/ The program(er/prog) status field ir[4] contains when the device is busy performing an erase or program operation; otherwise, it contains a logic "0". If the device is currently in System Configuration (ISC) mode; otherwise, it contains a logic "0". The done field ir[2] contains logic "1" if the sample design revision was successfully programmed; otherwise, logic "0" indicates incomplete programming. The remaining bits ir[1:0] are set to '01' as defined by IEEE Standard 1149.1 Boundary scan registers are used to control and observe the state of device pins during EXTEST, SAMPLE/PRELOAD and CLAMP instructions Flash on each output pin platform The prom has two register stages participating in boundary scan registers, while each input pin has only one register stage. Bidirectional pins have a total of three registration stages for boundary scan registers. For each output pin, the stage closest to TDI controls and observes the output state, and the second stage closest to the time difference controls and observes the high-Z enable state of the output pin. For each input pin, one register level controls and observes Enter the status of the pin. Bidirectional pins combine three bits, first the input stage bit, then the output stage bit and finally the output enable stage bit. The output enable stage bit is closest to tdo.

See the XCFXS//XCFXP PIN names and descriptionsTables in the Pinouts and Pin descriptions section for the boundary-scan bit order for all connected devices, or See the appropriate BSDL file for the complete boundary-scan bit order description under the attribute" in the BSDL file The boundary of the `U register' section". Bits assigned to Boundary Scan Cell 0" are the LSB of the Boundary Scan register, and are register bits closed to TDO. The Identification Register IDCode RegisterIDCODE is a fixed, vendor-specified value to be used.
Electrically identifying the manufacturer and type of device as the address IDCode register is 32 bits broad. The IDCODE register can be shifted out for examination by using the IDCODE instruction. IDCODE can be provided by any other system component via JTAG. Table 7 Lists the IDCOD Register Values for the Platform Flash Proms. The IDCODE register has the following binary format: Where Template Version Number Prom Family Code Special Platform Flash Product Identification c=The Xilinx Manufacturer'“IDCODE register’s always read as logic”As defined by IEEE STD.1149.1.
User register user instructions provide access to a 32-bit user programmable scratch pad typeically used to supply information about the device's programmed contents. Using user instructions, a user-programmable identifier can be removed for inspection. This code is loaded during programming to user registers in Lightning Platform If the device is bronk or not bronk is loaded during programming, user registers pack ffffffffh.
Customer Code Register For XCFXP platform flash, added to the user code, a 32-byte user code can be a PROM set for each design review.
User code is set during programming and is often used to provide information about design revisions.
Contents. A private JTAG command is required to read the client code if the promotion is blank, or if the code for the client selective design revision is not loaded during loading. Programming, or customer code if special design revisions will be included for all.
Platform Flash Features Flash platform programming and IEEE 1149.1 boundary scan (JTAG) testing in the system via a single 4-Wire Test Access Port ("TAP"). Simplify system design and configure standard automatic test equipment to achieve two functions. The AC characteristics of the front cone of a platform flash are described below.
Taper Timing These timing characteristics are the same for both sides.
Boundary scan and ISP operation.

Additional Features of the xcfxp Internal Oscillator 8/16/32 mbit The xcfxp platform flash proms includes an optional internal oscillator that can be used to drive the clock and data pins on the configuration interface.
The internal oscillator can be enabled during device programming and can be set to the default frequency or at a lower frequency (AC characteristic under operating conditions when cascaded).
Corcort 8/16/32 mbit xcfxp platform flash proms include a programmable option to enable the CLKOUT signal which allows the prom to provide a synchronous source clock aligned with the data on the configuration interface This clkout signal comes from one of two clock sources: CLK IN pin or the internal oscillator. The input clock selects the source sequence during PROM programming. The output data is located in Kercourt.
The clkout signal is enabled during programming and active when CE is low and OE/RESET is high. When disabled, the CLKOUT pin will go into a high impedance state and should be pulled high externally to provide a known state.
Enabled when using the clkout cascade platform flash proms, after completing the data transfer, the first prom disables the clkout and releases the ceo pin to enable the next prom in the prom chain. The next dance is about to begin. Once the prom is up, driving the clkout signal data is available for transmission.
In a high-speed parallel configuration without compression, the FPGA drives the busy signal interface on the configuration. When busy is asserted high, the proms internal address counter stops incrementing, and the current data value is saved on the data output. While busy, the prom will continue to the FPGA, recording the FPGA's configuration logic. When the fpga relieves asserts busy, it means that it is ready to receive additional configuration data, and the PROM will start driving new data on the configuration interface.

stress reliever
8/16/32 mbit xcfxp platform flash proms include built-in data decompressor compression technology compatible with Xilinx advanced. Compressed platform flash prom files are created from the target fpga bitstream using Impact software. Only Slave Serial and Slave Support SelectMap (Parallel) Configuration Mode The FPGA configuration compression ratio when using an XCFxxP PROM programmed with a compressed bitstream depends on several factors, including the target device family and target design content.
The unpack option enables programming sequence during PROM. Prom decompresses the configuration interface in driving clock and data to the FPGA. If decompression is enabled, the platform flash clock output pin (CLKOUT) must be used as the configuration clock signal interface to drive the configuration clock input pin (CCLK) of the target FPGA. The CLK input pin of the PROM or the internal oscillator must be selected as the source of CLKOUT. Any target FPGA connected to the prom must operate as a slave in the configuration chain with the configuration mode set to slave serial mode or slave select mapped (parallel) mode.
When decompression is enabled, the clkout signal becomes the maximum control clock output frequency. When the decompressed data is not ready, the clkout pin will go to a high-z state and must be pulled high to provide a known state from the outside.
When decompression is enabled, busy input is automatically disabled.
Design modification allows users to create up to four flash proms on a single PROM or stored in multiple cascaded prom8/16/32 mbit xcfxxp platforms. Design modification is supported in serial and parallel mode. Design modifications can be used with compressed prom files and CLKOUT feature enabled prom programming files are created with the Revision Information File (.cfi) using Impact software. The .cfi file is required to enable design revision programming in Impact. A single design revision consists of 1 to n 8-mbit memory blocks. If a single design revision contains more than 8mbits of data, the remaining space is filled and all together larger design revisions can span several 8-Mbit memory blocks, and the last 8-mbit memory block is fully filled.
• A 32mbit prom contains four 8mbit memory blocks, so up to four independent design revisions can be stored: one 32mbit design revision, two 16mbit design revisions, three 8mbit design revisions, four 8-mbit design revisions, So on and so forth.
• Because the 8-mbit minimum size requires each revision, a 16-mbit prom can only store up to two separate design revisions: one 16-mbit design revision, one 8-mbit design revision, or two 8-mbit design revisions .
• A single 8-mbit prom can store only one 8-mbit design revision.
Larger design modifications can be split into several cascading balls. For example, two 32mbit proms can store up to four separate design revisions: one 64mbit design revision, two 32mbit design revisions, three 16mbit design revisions, four 16mbit design revisions, etc. when cascading one 16mbit PROM and one With 8mbit PROM, there is 24mbit of free space, so up to three separate design revisions can be stored: one 24mbit design revision, two 8-Mbit design revisions, or three 8-Mbit design revisions.
See Figure 7 for some basic examples of how multiple revisions are stored. Design revision partitioning is handled automatically during the file generation process in impact. During prom file creation, each design revision is assigned a revision number: within a group of design revisions, a specific design revision can be either using the external rev_sel[1:0] pins or using the internal programmable design revision control bits. The en_ext_sel pin determines whether external pins or internal pinBITS are used to select design revisions. when? When en_ext_sel is low, control design revision selection via external revision selection pins, rev_sel[1:0]. when? en_ext_sel is high, design revision selection is controlled by the internally programmable revision selection control bits. Design modification select inputs (pins or control bits) are sampled internally during power-up. After power-up, when CE is asserted (low) the PROM input is enabled by design modification selection input on the rising edge of the cf pulse. Design modifications are presented from the selected and then on the Field Programmable Gate Array (FPGA) configuration interface.

Prom to FPGA Configuration Modes and Connection Summary The FPGA's I/Os, logic functions, and internal interconnects are loaded by the FPGA's bitstream The bitstream is loaded into the programmable gate array Starts automatically at power-up, or on command, depending on the FPGA The state of the mode pins of the Cylinkx platform flash prom is designed to be downloaded directly to the FPGA configuration interface. Field programmable gate array configuration The mode prom supported by the xcfxs platform flash includes: master serial and slave serial. The fpga configuration modes supported by the flash proms of the xcfxxp platform include: master serial, slave serial, master selection mapping and slave selection mapping. Below is a short overview of the supported FPGA configuration modes see the respective FPGA datasheets for device configuration details, including which configuration modes are supported by the target FPGA device.
Master Serial Mode In master serial mode, the FPGA automatically loads the bit-serial configuration bit stream from external memory, synchronized by a configuration clock (cclk) generated by the FPGA. At power up or reconfiguration, use the fpga's mode select pins to select the serial configuration mode of the master chip. The main serial mode provides a simple configuration interface. Only one serial data line clock line and two control lines (INIT and DONE) are required to configure an fpga. Data at the dance is read sequentially on a single data line (din), accessed through the PROM's internal address counter, which is incremented on every valid rising edge of CCLK. The serial bit stream data must be set on the DIN input pin a of the FPGA to generate the CCLK signal a short time before each rising edge inside the FPGA.

Usually, the cclk that can be generated internally for the fpga always starts at a slow default frequency. The FPGA's bitstream contains configuration bits that can switch CCLK to a higher frequency for the rest of the main serial configuration sequence. The desired cclk frequency is generated in the bitstream.
connect the fpga device to the config prom master serial config mode
The data output of the PROM drives leading FPGA devices.
The main fpga cclk output drives the clk input of the prom
The prom's ceo output drives the next dance to the daisy string (if any).
The OE/RESET pins of all proms are connected to the init_b pins of all fpga devices. This linkage ensures that the PROM address counter is at the beginning of any (re)configuration.
The PROM CE input can be driven by the DONE pin.
The CE input of the first (or only) PROM can be driven through the outputs of all target fpga devices, provided that DONE is not permanently grounded. The chief engineer can also be permanently pinned low, but this keeps the data output active and causes no Necessary ICC active supply current (DC characteristics over operating conditions).
The prom cf pins are usually connected to the fpga program inputs. For XCFxP only, the cf pin is a bidirectional pin. If the xcfxxp cf pin is a program (or program) input that is not connected to the FPGA, the pin should be tied high.
Slave-Serial Mode In slave-serial mode, the FPGA loads an externally-supplied clock-synchronized configuration bit stream from external memory in bit-serial form. After power-up or reconfiguration, the slave serial configuration mode is selected using the FPGA's mode select pins. Provides a simple configuration interface from serial mode. Only one serial data line, clock line, and two control lines (INIT and DONE) are necessary to configure an FPGA. Data is read sequentially from a programmable read-only memory (PROM) on a single data line, accessed via the PROM's internal address counter, incremented on each valid rising edge of cclk. Serial bit stream data must be set on the FPGA's DIN input pin A a short time before each rising edge supplied externally on CCLK.
Connect the FPGA device to the configuration PROM from serial configuration mode:
• PROM's data output drives leading fpga devices.
• prom clkout (xcfxp only) or an external clock source to drive the fpga's cclk input.
The prom's ceo output drives the next prom to be daisy chained (if any).
The OE/RESET pins of all proms are connected to the init_b (or init) pins of all fpga devices. This connection ensures that the PROM address counter is reset before any (re)configuration begins.
The PROM CE input can be driven by the DONE pin.
The CE input of the first (or only) PROM can be driven through the outputs of all target fpga devices, provided that DONE is not permanently grounded. The chief engineer can also be permanently pinned low, but this keeps the data output active and causes no Necessary ICC active supply current (DC characteristics over operating conditions).
The prom cf pins are usually connected to the fpga program input XCFxP only,
The cf pins are bidirectional pins. If the xcfxxp cf pin is a program (or program) input that is not connected to the FPGA, the pin should be tied high.
Daisy-chaining multiple FPGAs in series can be daisy-chained from a single source for serial configuration. After a specific FPGA configuration, the data for the next device is internally routed to the dual pins of the FPGA. Usually data on dout pin changes on the falling edge of CCLK, although for some settings the dout pin changes on the rising edge of cclk.
For details on a specific FPGA device, see the appropriate device datasheet. In order to time the daisy chain configuration, chain can be set to master serial, cclk is generated, and the rest of the devices are set to slave serial. Or all fpga devices can be set up from serial and externally generated clocks can be used to drive the fpga's configuration interface.
FPGA master select map (parallel) mode (1) In master selectmap mode, byte-range data is written to the fpga, usually with a busy flag to control the data, synchronized by the configuration clock (cclk) generated by the fpga. At power up or reconfiguration, use the fpga's mode select pins to select the master chip to select the mapping configuration mode. The configuration interface usually requires a parallel data bus, a clock line, and two control lines (INIT and DONE). In addition, the FPGA chip must properly control the select, write, and busy pins to enable SelectMAP to configure configuration data

The internally generated CCLK signal a short time before each rising edge of the fpga must hold the configuration data until it is too busy if it is asserted busy (high) through the FPGA. An external data source or external pull-down resistor must be used to enable the FPGA's active low chip select (CS or CS UB) and write (write or rdwr_b) signals that enable the FPGA's selectmap configuration process. The main SelectMAP configuration interface consists of the fpga's internal oscillator. In general, a wide range of frequencies can be selected for the internally generated CCLK. It always starts with a slow default frequency. The FPGA bitstream contains switchable configuration bits. For the rest of the master, higher CCLK frequencies are selected to map configuration. sequence. The desired cclk frequency is selected during bitstream generation. After configuration, the pins of the selectMap port can be used as additional user I/O. Alternatively, the port can be reserved using the persist option.
Connect the FPGA device to the configuration PROM master select map (parallel) configuration mode
The data output of the PROM drives the input of the [d0..d7] master fpga device.
The main fpga cclk output drives the clk input prom's ceo output drives the next prom which is daisy chained (if any).
The OE/RESET pins of all proms are connected to the init_b pins of all fpga devices. This linkage ensures that the PROM address counter is at the beginning of any (re)configuration.
The PROM CE input can be driven by the DONE pin.
The CE input of the first (or only) PROM can be driven through the outputs of all target fpga devices, provided that DONE is not permanently grounded. The chief engineer can also be permanently pinned low, but this keeps the data output active and causes no Necessary ICC active supply current (DC characteristics over operating conditions).
For high frequency parallel configuration, all PROM pins are connected to the FPGA's busy output. This connection ensures that the transition of the next data PROM is delayed until the FPGA is ready for the next configuration data byte.
The prom cf pins are usually connected to the fpga program inputs. For XCFxP only, the cf pin is a bidirectional pin. If the xcfxxp cf pin is a program (or program) input that is not connected to the FPGA, the pin should be tied high. FPGA slave SelectMAP (parallel) mode (1) In slave selectmap mode, byte-range data is written to the fpga, usually with a busy flag to control the data, and the configuration synchronization clock (CCLK) provided by the external. At power up or reconfiguration, use the FPGA's mode select pins to select the slave select map configuration mode. The configuration interface usually requires a parallel data bus, a clock line, and two control lines (INIT and DONE). In addition, the FPGA chip must properly control the select, write, and busy pins to enable SelectMAP to configure configuration data from pins [d0. The PROM on .d7] is read byte by byte, incremented on every valid rising edge of cclk via the PROM's internal address counter access. The bitstream data must be set at the supplied CCLK at the FPGA's [D0..D7] inputs. If the fpga asserts busy (high), it must hold the configuration data until busy goes low. The external one must enable the FPGA's active low chip select (CS or CS-B) using a data source or an external pull-down resistor and write (write or rdwr_b) signals to enable the FPGA's selectmap configuration process.
After configuration, the pins of the selectMap port can be used as additional user I/O. Alternatively, the port can be reserved using the persist option.
Connect the FPGA device to the configuration PROM from the selection map (parallel) configuration mode:
• The data output of the PROM drives the input of the [D0..D7] host FPGA device.
• Prom clkout (xcfxp only) or external clock source to drive FPGA's cclk input • PROM's ceo output to drive next prom is daisy chaining (if any).
• The OE/RESET pins of all proms are connected to the init_b pins of all fpga devices. This linkage ensures that the PROM address counter is at the beginning of any (re)configuration.
• The PROM CE input can be driven by the DONE pin. The CE input of the first (or only) PROM can be driven through the outputs of all target fpga devices, provided that DONE is not permanently grounded. The chief engineer can also be permanently pinned low, but this keeps the data output active and causes no Necessary ICC active supply current (DC characteristics over operating conditions).
For high frequency parallel configuration all the pins of the prom are connected to the busy output of the fpga. This connection ensures that the next

program input. For XCFxP only, the cf pin is a bidirectional pin. If the xcfxxp cf pin is a program (or program) input that is not connected to the FPGA, the pin should be tied high.
The fpga select map (parallel) device chain (1) can use select map mode and have it start simultaneously. To configure multiple devices this way, parallel cclk, done, init, data ([d0..d7]), write (write or rdwr_b) and the busy pins of all devices. If all devices are to be configured to the same bit stream, no readback is used, and the CCLK frequency is selected without the use of a busy signal, the CS\UB pins can be connected to a common line, so all devices are configured at the same time.
With additional control logic, each device can load the corresponding configuration data in turn by asserting the CS_B pin of each device.
The prom can also store each programmable gate array for SelectMAP configuration in separate design revisions. When using design revisions, additional control logic can be used to select all The desired bitstream is asserted, and the cs_b pin of the FPGA for which the bitstream is asserted.
For parallel configuration chain timing, the fpga in the first chain can be set to master selectmap, generating cclk, and the rest of the devices can be set to slaveSelectMAP, or all FPGA devices can be set to slave. Selectmap and externally generated clocks can be used to drive the configuration interface in the same way , each for details on a specific fpga device, including the configuration modes supported by the target fpga device, should refer to the device datasheet. Cascading configuration proms provides additional memory when configuring multiple FPGAs in a serial daisy chain, configuring multiple FPGAs in a selectmap parallel chain, or configuring a single FPGA that requires a larger configuration bitstream. The multi-platform flash prom can drive the ce input of downstream devices by using the ceo output. All clock signals and data output chains in the platform flash prom are interconnected. After reading the last data from the first PROM, the first prom claims that its ceo output is low and drives its output to a high impedance state. The second dance takes its CE input low and immediately enables its output.
After configuration, if the PROM OE/reset pin goes low or CE high.
When using the advanced features of the XCFxxP platform Flash PROM, including clock output (CLKOUT) options, decompression options, or design modifications, the programming file across cascaded prom devices only contains the xcfxp protocol. If advanced features are not used, then cascaded prom chains can contain xcfxp and XCFXS projects.
Start fpga configuration Options to start FPGA configuration through the platform Flash PROM include: auto-configure at boot time Apply external program pulses Apply jtag config instructions Follow the FPGA power-up sequence or assert in the PROG_B (or PROGRAM) pin, clear the FPGA's configuration memory, Select configuration mode and the fpga is ready to accept a new configuration bitstream. The Program B pin of the programmable gate array can be sourced from an external source, or the platform flash proms incorporate a cf pin Program B pin that can be bound to the fpga. By executing the config command JTAG outputs a low pulse to CF once for 300-500 nanoseconds to reset the field programmable gate array and start the configuration. Affected software can issue the jtag config command to initiate fpga configuration by setting the "load fpga" option.
When revisions are enabled when using the xcfxp platform Flash PROM in the design, the CF pin should always be connected to the PROG B (or program) pin on the FPGA to ensure that the current design revision selection is sampled when the FPGA is reset. The xcfxxp prom selects the current design revision externally on the REV_SEL pin or the internally programmable version selects the bit on the rising edge of cf. When executing the jtag config command, xcfxp will modify the order of the design before the new boot fpga configuration. When using the xcfxp platform flash prom if the cf pin is not connected to the FPGA PROG_B (or PROGRAM) pin, then the xcfxp CF pin should be tied high.

Configure the connection diagram of the prom to the fpga device interface

Reset and Power-On Reset Activation When powered on, the device requires the VCCINT power supply to rise monotonically to the VCCINT rise time specified by the rated operating voltage. If the power supply cannot meet this requirement, the device may not be able to perform a power-on reset properly. During power-up, OE/reset is held low by PROM once the required power supply has reached the respective port (power-on-reset) thresholds, the run-experience/reset release delay (minimum TOER) allows the power supply to have more headroom at startup Stable before configuration. The OE/reset pin is connected to an external 4.7KΩ pull-up resistor and to the initial pin of the target fpga. For systems using slow-rising power supplies, additional power supply monitoring circuitry can be used to delay target configuration until system power is pulled high by holding the OE/reset pin low while run-experience/reset is released, allowing the FPGA's init pin to be pulled high. The configuration sequence for the fpga begins. If the power falls below the power-down threshold (VCCPD), the PROM reset OE/RESET is held low again until the POR threshold is reached. The OE/reset polarity is not programmable.
For full power platform flash prom, reset occurs whenever oe/reset is asserted (low) or ce is deasserted (high). The address counter is reset, the CEO is driven high, and the remaining outputs are in a high impedance state.
Note: A xcfxs PROM only needs VCCINT above the POR threshold before releasing OE/RESET.
2. The xcfxxp prom requires both vccint to be above its por threshold and vcco to reach the recommended working voltage level before release/reset.

Input/Output Input Voltage Tolerance and Power Sequencing i/os on each reprogrammable platform flash prom is fully 3.3V tolerant. This allows 3V CMOS signals to be connected directly to the input without damage. Core power supply (VCCINT), JTAG pin supply (VCCJ), output supply (VCCO), and external 3V CMOS I/O signals can be applied in any order.
Also, for XCFXS PROM only, when VCCO is powered at 2.5V or 3.3V, and VCCINT is powered at 3.3V, the I/Os are 5V tolerant. This allows 5V CMOS signals to be directly connected to the power supply input of xCFxS PROM without damage . When supplying a 5V input signal may cause xcfxs devices.
Standby Mode Whenever CE is deasserted (high) in Standby state, after the address counter is reset, the CEO will be energized high and the remaining outputs are in a high impedance state regardless of the run/reset input. To keep the device in low power standby mode, the JTAG pins tms, tdi and TDO cannot be pulled low and TCK must be stopped (high or low). The pin is high when driving the PROM-CE with the FPGA completion signal, to reduce backup power after configuration, an external pull-up resistor should be used. Typically a pull-up resistor is used for 330Ω, but please refer to the corresponding FPGA-recommended datasheet for pull-up values for the completed pins. If the done circuit is connected to the LED to indicate that the FPGA configuration is complete, and also connected to the PROM CE pin to enable low power standby mode, then an external buffer should be used to drive the LED circuit to ensure a valid transition on the CE pin of the PROM. If the low power PROM does not require standby mode, then the CE pin should be grounded.

AC characteristics under operating conditions

AC characteristics under operating conditions when cascaded

XCFxP Lead Diagram