feature
5 ns end-to-end logic delay system frequency up to 178 MHz
72 macrocells, 1600 usable gates in small package
- 44-pin PLCC (34 user I/O pins)
- 44-pin VQFP (34 user I/O pins)
- 48-pin CSP (38 user I/O pins)
- 64-pin VQFP (52 user I/O pins)
- 100-pin TQFP (72 user I/O pins)
Optimized for high performance 3.3V systems
- low power operation
-5V tolerant I/O pins accept 5V, 3.3V and 2.5V signals
-3.3V or 2.5V output capability
- Advanced 0.35 micron feature size CMOSFastFLASH technology advanced system capabilities
- Programmable within the system
- Superior pin locking and routability FastConnect II 8482 ; switch matrix
- Extra wide 54 input function block
- Up to 90 product terms per macrocell Individual product term assignments
- Three global one local clock inversion product term clock
- Individual output enable for each output pin
- Input hysteresis input on all user and boundary scan pins
- Bus hold circuits on all user pin inputs
- Full IEEE Standard 1149.1 Boundary Scan (JTAG) Fast concurrent programming Slew rate control for a single output Enhanced data security features Superior quality and reliability
- Endurance over 10000 program/erase cycles
-20 years data retention
-ESD protection over 2000V
Pinout with 44-pin PLCC package and 100-pin TQFP package description
The XC9572XL is a 3.3V CPLD designed primarily for high-performance, low-voltage applications in high-end communications and computing systems. It consists of a four-part 54V18 function block that provides 1600 usable gates with a propagation delay of 5ns.
Overview.
power estimation
The power consumption of cpld varies greatly with system frequency, design application and output. load. To reduce power consumption, for each macrocell in the XC9500XL, the device can be configured in a low-power mode (from the default high-performance mode). In addition, the software automatically deactivates unused product terms and macrocells to further save power.
For a general estimate of ICC, the following equation can be used:
ICC (mA) = MCHP (0.5) + MCLP (0.3) + MC (0.0045 mA/MHz)
MCHP=macrocells in high performance (default) mode MCLP=macrocells in low power mode MC=total number of macrocells used F=clock frequency (MHz) This calculation is based on typical operating conditions using 16 in each function The mode of the bit up/down counter does not output the loaded block. Actual ICC values vary along with the design application and should work properly in the system.