feature:
Low power CMOS technology: maximum write current 5 mA 5.5V5.5V maximum read current 500 μA
- Standby current 100mA , typ. 5.5V
2-wire serial interface bus, I2C™ compatible Cascadable up to four devices Automatically timed erase/write cycle Provides 128-byte page write mode Up to 5 ms write cycle time Hardware write-protected output ramp control for entire array , eliminating ground bounce Schmitt trigger input for noise suppression
1,000,000 erase/write cycles ESD protection >4000V
Data retention period > 200 years
8-Pin PDIP, SOIC Package Temperature Range:
- Industrial (I): -40°C to +85°C
Description The Microchip Technology 24AA1025/24LC1025/24fc1025 (24xx1025*) are 128k x 8 (1024k-bit) serial electrically erasable programmable read-only memories capable of operating over a wide voltage range (1.8V to 5.5V). It has been developed for advanced, low-power applications such as personal communications or data acquisition.
This device has data byte write and page write capability up to 128 bytes. This device is capable of random and sequential reads. Reads may be in the sequence 0000h to ffffh 10000h to 1fffh in the address range. The functional address line allows up to four devices on the same data bus. This allows total system EEPROM memory up to 4 Mbytes. This device is available in a standard 8-pin plastic dip and SOIC package.

bus timing data

PIN description
The descriptions of the pins are listed in table 2-1.Table 2-1: PIN Function Table
A0, A1 Chip Address Inputs The A0, A1 Inputs are used by the 24xx1025 for multiple device operations. The levels of these inputs are compared to the corresponding bit address of the Slav. If the comparison is true, the chip is selected. Four devices can be connected to the same bus. Use different chip select bit combinations. For most applications, chip address inputs A0 and A1 are hard to logic ''0' or logic '' applied to these pines are controlled by a microcontroller or other programmable device, chip addresses must be directed to logic '0' before they are loose in normal OR logical" device operations can proceed.
A2 chip address input input is not configurable chip select. This loose must be positioned as VCC in the order in which this device operates.
Serial Data This is a bidirectional loose data input device used to transmit addresses, and a data output device. It is an open termination, so the SDA bus requires a pulse resistor to VCC ("typical 10kg x 100kHz, 2kg x 1 x 1 x 1 x 1 x 1 x 1 x 1 x 1 ×1×1×2×2400 KHZ and 1 MHZ for normal data transfer SDA is only allowed to make changes during SCL Low. Changes during SCL high temperature Reserved for indicating the start and stop conditions. Serial Clock This input is used to synchronize data transfer.
and equipment.
Write-Protect (("WP") This pin must be connected to another VSS or VCC. If Tied in VSS, a text operation is created. If tied to vcc, the text operation is inhibited, but the read operation is not affected Functional Description A device that supports the bidirectional 2-Wire Bus and data transfer protocol provides data. The bus is defined as a transmitter and a device receives data as a receiver. The bus must be controlled by a master device that generates the serial clock and controls the access to the bus. , as well as generating start and stop conditions 24x1025 works as a slave. Both masters and slaves can operate as transmitters or receivers, but the master device determines which modes are activated.

The bus characteristics define the following bus protocols:
8226 ; only when the bus is not busy.
• During data transfer, the data line must remain stable when the clock line is high. Changing the data line while the clock line is high will be interpreted as a start or stop condition. Hence, the following bus condition definitions.
Bus not busy (A)
Both the data and clock lines are held high.
A high-low transition (SCL) high on the sda line during the start of a data transfer (b) clock determines the start condition. All commands must be preceded by a start condition.
A low-to-high transition (SCL) high on the sda line during the stop data transfer (C) clock determines the stop condition. All operations must end with a stop condition.
Data is valid (D)
The state of the data line represents valid data for the duration of the high period of the data line for the clock signal after the start condition. The period of the data clock signal on the row must be changed during the low period. every clock pulse.
Each data transfer is terminated with a START condition and with a STOP condition. The number of data bytes transferred between start and stop conditions is determined by the master device.
Acknowledges that each receiving device, when addressed, must receive every byte. The master must generate additional clock pulse bits associated with this acknowledgement.
The acknowledging device must pull down the SDA line during the acknowledgment clock pulse on the SDA line at the clock pulse associated with the acknowledgment. Of course, the setup must take into account the waiting time. When reading, the master must signal the end of data to the slave without generating an acknowledgment bit on the last byte that has been clocked from the slave. In this case the slave (24xx1025) will hold the data line high to enable the master generating the stop condition.

The device addressing control byte is in the start condition from the master device. The control byte consists of a 4-bit control code; for 24xx1025, set to "1010" binary for read and write operations. The next bit of the control byte is the block select bit (b0). This bit is used as the A16 address bit used to access the entire array. The next two control bytes are the chip select bits (a1, a0). This chip select bit allows up to four 24xx1025 devices on the same bus to be used to select which device has been accessed. The bit bytes in the chip select controls must correspond to logic levels on the corresponding A1 and A0 pins for the device to respond. These bits are actually the word address.
The last bit of the control byte defines the operation to be performed. When set to 1, read operations are selected, when set to zero, write operations are selected. The next two bytes received define the address of the first data byte. The upper layer transmits the address bits first, and then transmits the less significant bits of the address bits.
According to the start condition, the 24xx1025 monitor is checking the sda bus transfer of the device type identifier. When the "1010" code and the appropriate device select bits are received, the slave device outputs an acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24xx1025 will select read or write operations.
This device has an internal addressing boundary divided into two segments of 512K bits. Block select bit 'b0' controls access to each segment.
Format Consecutive addressing of multiple devices Chip select bits a1, a0 can be used to extend the contiguous address space up to 4mbit There are four 24xx1025s in the same vehicle. In this case, software can use a0 of the control byte as address bit A16 and A1 as address bit A17. Sequential reads across device boundaries are not possible.
Every device has internal addressing boundary restrictions. This splits each part into two parts of 512K bits. Block select bit 'b0' controls for each 'half'.
Sequential read operations are limited to 512K blocks. To read four devices on the same bus, eight must give random read commands.

Write Operation Byte Write Control code (four bits), block select (one bit), chip select (two bits) and R/W bit (logic (low) are clocked onto the bus by the host transmitter according to the host's start condition .
This indicates to the addressed slave receiver that the high order byte of the address is generating the acknowledge bit within the ninth clock cycle. Therefore, the next byte sent by the host is the high order byte of the word address and will be written into the address pointer of the 24xx1025. The next byte is the least significant address byte. After receiving another acknowledgment signal from the 24XX1025, the master sends the data word to be written to the address memory location. This 24xx1025 confirms again that the host generates a stop condition. This will initiate an internal write cycle during which the 24xx1025 will not generate an acknowledge signal as long as the control byte is polled and used to initiate the write. If someone tries to write to the array with the wp pin held high, the device will acknowledge the command, but when no write cycle will occur, no data will be written and the device will accept new commands immediately. After byte write command, the internal address counter will point to the address location following the address just written.
Page write write control byte, word address and first data byte are transferred to 24xx1025 in the same way as byte write. But instead of stop, the host can transfer up to 127 additional bytes in this case, temporarily stored in an on-chip in-page buffer, and written to memory after the host has transmitted the stop condition. The seven lower address pointer bits are internally incremented by one upon receipt of the postword. If the master is to transmit more than 128 bytes before the stop condition is generated, the address counter will rollover and the previously received data will be overwritten. As with a byte write operation, once a stop condition is received, the internal write loop will begin. If an attempt is made to make it write to the array with the wp pin held high, the device will acknowledge the command, but no write will loop, no data will be written, and the device will accept new commands immediately.
Write protect wp pins allows the user to write protect the entire array (00000-1fff) when the pins are tied to VCC. If tied for vss or left floating, write protection is disabled.
Every time a write is made, the wp pin is in the stop bit. The sampling command in the stop bit has no effect on the execution of the write loop.

READ OPERATIONS A read operation is initiated in the same way as a write operation, but with the control byte set to 1. There are three basic types of read operations: current address read, random read, and sequential read.
Current Address Read 24xx1025 contains an address counter that internally maintains the address of the last word accessed incremented by 1. Therefore, if the address accessed by the previous read is n (n is any legal address). The next current address read operation will access data from address n+1. On receipt of a control byte with the r/w bit set to 1, the 24xx1025 issues an acknowledgment and sends an 8-bit data word. The master does not acknowledge but does generate a stop condition and 24xx1025 stops the transfer.
Read random read random read operations allow the host to access any location that is stored in a random fashion. To perform this type of read operation, first the word address must be ready. By sending the word address to the 24xx1025 as part of a write operation (r/w bit set to 0). After sending the word address, the master generates a start condition after confirmation. This terminates the write operation, but not before setting the internal address pointer. Then, the master issues the control byte again, but with the R/W bit set to 1.
The 24xx1025 will then send an acknowledgment to transmit the 8-bit data word. The master does not acknowledge the transmission but does generate the conditional gearbox that stops the 24xx1025 from running. After a random read command, the internal address counter will point to the address location following the address just read.
Sequential Read Sequential reads are started in the same way as random reads, except for the first data byte after the 24xx1025 transfer, the host issues an acknowledgment and the random read is used in the opposite stop condition. This acknowledgement instructs the 24xx1025 to send the next sequentially addressed 8-bit word. Upon transmission to the master, the master will not generate an acknowledgement, but will generate a stop condition. To provide sequential reads, the 24xx1025 contains an internal address pointer that increments by one each time the action is complete. This address pointer allows serial reading of memory contents in one operation. The sequential read address boundaries are 0000h to FFFFH and 10000H to 1FFFH. The internal address pointer will automatically roll over from address ffff if the host acknowledges that a byte is received from array address 1ffff. The internal address counter will automatically go from address 1fffh to address 10000h if the host acknowledges the bytes received from the array at address 1fffh.