feature

35mW maximum power consumption; slim 50W power-down mode; slim maximum 25s acquisition and conversion; maximum 1.5LSB entry; dnl: 16 bits, no missing codes; minimum SNR with 1kHz input is 86dB; ± 10V , 0V to +5V and 0V to +4V input range; single +5V supply operation; parallel serial data output; pin compatible with 12-bit ADS7806 ; use internal or external references; 0.3" DIP-28 and SO-28.

illustrate

The ADS7807 is a low-power 16-bit sampling analog-to-digital converter using state-of-the-art CMOS architecture. It contains a complete 16-bit, capacitance-based, successive approximation register (SAR) A/D converter with sample and hold, clock, reference, and microprocessor interface with parallel and serial output drivers.

The ADS7807 can acquire and convert 16 bits to within ±1.5LSB in 25 microseconds while consuming only 35mW maximum. Laser trimmed scaling resistors provide standard industry input ranges of ±10V and 0V to +5V. In addition, the 0V to +4V range allows the development of complete single-supply systems.

The ADS7807 is available in 0.3" DIP-28 and SO-28 models, both fully specified for operation over the industrial -40°C to +85°C temperature range.

Typical features

At ta=+25°C, fs=40kHz, vdig=vana=+5V, use internal reference and fixed resistors (see Figure 7b) unless otherwise specified.

Basic operation

Parallel output

Figure 1a shows the basic circuit for operating the ADS7807 with a ±10V input range and parallel output. Driving R/C (pin 22) down to at least 40ns (12µs max) will initiate a conversion. BUSY (pin 24) will go low and remain low until the conversion is complete and the output register is updated. If byte (pin 21) is low, the bits (msbs) will be active when busy is rising; if byte is high, the 8 least significant bits (lsbs) will be busy. The data will be output in binary 2's complement (btc) format. Busy high can be used to lock data. After the first byte is read, the bytes can be toggled to allow the remaining bytes to be read. All conversion COM-busy tasks will be ignored.

The ADS7807 will begin tracking the input signal at the end of the conversion. Allow 25 microseconds between transition commands to ensure accurate acquisition of new signals.

Offset and gain are adjusted internally to allow external trimming using a single supply. An external resistor compensates for this adjustment, which is negligible if the offset and gain are corrected in software (see the Calibration section).

Serial output

Figure 1b shows the basic circuit for operating the ADS7807 with a ±10V input range and serial output. Take R/C (pin 22) to output valid data from the previous conversion on SData (pin 19) and synchronize to the 16 clock pulses output on DataCLK (pin 18). BUSY (pin 24) will go low and remain low until the conversion is complete and serial data is transferred. Data will be output in btc format, msb first, and valid on both the rising and falling edges of the data clock. Busy high can be used to lock data. Convert All Commands will be ignored when busy.

The ADS7807 will start tracking the input signal transitions at the end. Allow 25 microseconds between transition commands to ensure accurate acquisition of new signals.

Offset and gain are adjusted internally to allow external trimming using a single supply. External resistors compensate for this adjustment, and can be ignored if offset and gain are corrected in software.

start conversion

The combination of CS (Pin 23) and R/C (Pin 22) for a minimum of 40ns puts the sample and hold of the ADS7807 in hold and starts converting "n". busy (pin 24) will go low and remain low until conversion "n" is complete and the internal output registers have been updated. Brand new scam - vertical commands on busy low will be ignored. CS and/or R/C must go high before Busy goes high, otherwise a new conversion will be initiated without enough time to acquire a new signal.

The ADS7807 will begin tracking the input signal at the end of the conversion. Allow 25 microseconds between transition commands to ensure accurate acquisition of new signals.

When conversion "n" is initiated low, serial data for conversion "n–1" will be output to SData (pin 19) after conversion "n" begins. See Internal Data Clock in the Read Data section.

To reduce the number of control pins, r/c can be used to control read and transition modes by placing the CS system in a lower position. This will not work when using the internal data clock in serial output mode. However, the parallel output and serial output (only when using an external data clock) will be affected whenever R/C goes high.

read data

The ADS7807 outputs serial or parallel data in direct binary (sb) or binary two's complement data output formats. If SB/BTC (pin 7) is high, the output is in SB format, if low, the output is in BTC format.

The parallel outputs can be read without affecting the internal output registers; however, reading data through the serial port will shift the internal output registers by one clock pulse per data. Therefore, data can be read on the parallel port until the same data on the serial port is read, but data cannot be read through the serial port until the same data on the parallel port is read.

Parallel output

To use the parallel output, connect Ext/Int (pin 8) to High and DataClk (pin 18) to Low. SData (pin 19) should be left unconnected. The parallel output will activate when R/C (Pin 22) is high and CS (Pin 23) is low. Any other combination of C and R/C will tri-state the outputs in parallel. Valid conversion data can be read in two 8-bit bytes on D7-d0 (pins 9-13 and 15-17). When the byte (pin 21) is low, the 8 most significant bits are valid for the msb on D7. When byte is high, the 8 least significant bits are valid for lsb on d0. Bytes can be switched to read two bytes in one conversion cycle.

On initial power-up, the parallel outputs will contain indeterminate data.

Parallel output (after conversion)

After conversion "n" is complete, the output register has been updated and busy (pin 24) will go high. Valid data for transition 'n' will be at D7-d0. Busy high can be used to lock data.

Parallel output (during conversion)

After starting conversion "n", valid data in conversion "n–1" can be read and valid for 12 microseconds after conversion "n" begins. Do not attempt to read data more than 12 microseconds after transition "n" begins until busy (pin 24) goes high; this may result in invalid data being read.

Serial output

Data can be clocked using the internal data clock or an external data clock. When using serial outputs, be careful with parallel outputs D7-d0 (pins 9-13 and 15-17) as shown below When CS (pin 23) is low, the pins will come out of the HI-Z state R/C ( pin 22) high. Serial outputs cannot be tri-stated and are always active. See the Application Information section for specific serial interfaces.

Internal data clock (during conversion)

To use the internal data clock, drive Ext/Int (pin 8) low. This combination of R/C (Pin 22) and CS (Pin 23) low will initiate conversion 'N' and activate the internal data clock (typically 900kHz clock rate). The ADS7807 will first output 16 bits of valid data (msb) from transition 'n-1' on SData (pin 19), synchronized to the 16 clock pulses output on dataclk (pin 18). Data will be clocked on the internal data clock. The rising edge of busy (pin 24) can be used to lock data. After the 16th clock pulse, dataclk will remain low until the next conversion begins, and sdata will go to whatever logic level was input on the tag (pin 20) during the first clock pulse.

External data clock

To use an external data clock, connect Ext/Int (pin 8) high. The external data clock is not a conversion clock and can only be used as a data clock. To enable the output mode of the ADS7807, CS (pin 23) must be low and R/C (pin 22) must be high. dataclk must be up to 20% to 70% of the total data clock period; the clock frequency can be between dc and 10mhz. Serial data from transition 'n' can be output on sdata (pin 19) after transition 'n' is complete or during transition 'n+1'.

An obvious way to simplify converter control is to cs low and use r/c to start the conversion.

While this is perfectly acceptable, problems can arise when using an external data clock. at an uncertain point

From 12 microseconds after the start of conversion "n" to the busy rise, internal logic converts the result of conversion "n" to the output register. If CS is low and R/C is high, the external clock is high at this time, and the data will be lost. Therefore, with cs low, r/c and/or dataclk must be low during this period to avoid loss of valid data.

External data clock (after conversion)

After conversion "n" is complete, the output register has been updated and busy (pin 24) will go high. Using CS low and r/c high, valid data for transition 'n' will be output on sdata (pin 19), synchronized to the external data clock input on dataclk (pin 18). msb is valid on the first falling edge and second rising edge of the external data clock. The LSB is valid on the 16th falling edge and the 17th rising edge of the data clock. The tag (pin 20) will input one bit of data per external clock pulse. The first bit input on the label is valid on the 17th falling edge and 18th rising edge of sdata of dataclk; the second input bit is valid on the 18th falling edge and 19th rising edge, etc. Using a continuous data clock, the tag data will be output on sdata until the internal output registers are updated based on the result of the next conversion.

External data clock (during conversion)

After starting conversion "n", valid data in conversion "n–1" can be read and valid for 12 microseconds after conversion "n" begins. Do not attempt to time out data rising from 12 microseconds after transition "n" begins to busy (pin 24); this will result in data loss. Note: For best performance when using an external data clock, data should not be clocked during conversion. Switching noise from asynchronous data clocks can cause digital feedthrough and degrade converter performance.

Mark function

Tag (pin 20) input serial data synchronized to external or internal data clock. When using an external data clock, the serial bitstream input on the tag will follow the lsb output on sdata until the internal output register is updated with the new conversion result.

The logic level input on the label of the first rising edge of the internal data clock is valid on sdata after all 16 bits of valid data have been output.

input range

The ADS7807 offers three input ranges: standard ±10V and 0V-5V, and a 0V-4V range for complete single-supply systems. See Figures 7a and 7b for the circuit connections required to implement each input range and optional offset and gain adjustment circuits. Test offset and full-scale error (1) specifications with fixed resistors, see Figure 7b. Adjustments for offset and gain are described in the calibration section of this data sheet.

Offset and gain are adjusted internally to allow external trimming using a single supply. An external resistor compensates for this adjustment, which is negligible if the offset and gain are corrected in software (see the Calibration section).

The input impedances summarized in Table II are a combination of the internal resistor network (see the front page of this product data sheet) and the external resistors used for each input range (see Figure 8). The input resistor divider network provides inherent overvoltage protection of at least ±5.5v and ±12v for r2in and r1in.

An analog input above or below the expected range will produce a positive full-scale or negative full-scale digital output, respectively. For analog inputs beyond the nominal range, no wrapping or folding occurs.

Notes: (1) Full-scale error includes offset and gain errors measured at +fs and -fs.

calibration

hardware calibration

To calibrate the offset and gain of the ADS7807 in hardware, install the resistors shown in Figure 7A. Table VI lists the hardware trim ranges for each input range relative to the input.

software calibration

To calibrate offset and gain in software, no external resistors are required. However, to obtain the datasheet specifications for offset and gain, the resistors shown in Figure 7b are necessary. See the No Calibration section for more details on external resistors. Refer to Table 8 for offset and gain error ranges with and without external resistors.

No calibration

Figure 7b shows the circuit connections. Note that the actual voltage drop across the external resistor is at least two orders of magnitude lower than the voltage across the internal resistor divider network. This should be taken into account when choosing the accuracy and drift specifications of the external resistors. In most applications, a 1% metal film resistor is sufficient.

In some applications, external resistors may not be required (see Figure 7b). These resistors provide compensated internally trimmed offset and gain, allowing calibration with a single power supply. Not using external resistors will result in offset and gain errors, as well as the errors listed in the Electrical Characteristics section. Offset is the equivalent voltage of the digital output when the input is grounded. Positive gain error occurs when the equivalent output voltage of the digital output is greater than the analog input. Refer to Table 7 for the nominal ranges of gain and offset errors with or without external resistors. See Figure 8 for a typical change in transfer function when the external resistor is removed.

To further analyze the effect of removing any combination of external resistors, consider Figure 9. The combination of external and internal resistors form a voltage divider that reduces the input signal to an input range of 0.3125v to 2.8125v at the capacitor digital-to-analog converter (cdac). Internal resistors are laser trimmed to high relative accuracy to meet full-scale specifications. However, due to process variations, the actual input impedance of the internal resistor network (look at pin 1 or pin 3) is only accurate to ±20%. This should be taken into account when determining the effect of removing external resistors.

refer to

The ADS7807 can operate with its internal 2.5V reference or with an external reference. By applying an external reference to pin 5, the internal reference can be bypassed; tying the RFD (pin 26) to a high will power to the internal reference reduces the total power dissipation of the ADS7807 by about 5MW.

The internal reference has about 8ppm/°C drift (typical), which accounts for about 20% of the full-scale error (FSE = ±0.5% for low grades, ±0.25% for high grades).

The ADS7807 also has an internal reference voltage buffer. Figure 10 shows the characteristic impedance of the buffer input and output for all power-down and reference power-down combinations.

REF

REF (Pin 5) is the input for the external reference or the output for the internal 2.5V reference. The 2.2µf tantalum capacitor should be placed as close to the reference pin from ground as possible. This capacitor and ref's output resistance create a low-pass filter to limit noise on the reference. Using a smaller capacitor value will introduce more noise to the reference signal, reducing the SNR and SNR. The reference pins should not be used to drive external AC or DC loads, as shown in Figure 10.

The external reference is in the range of 2.3V to 2.7V and determines the actual LSB size. Increasing the reference voltage can increase the full-scale range and lsb size of the converter, thereby improving the signal-to-noise ratio.

CAP

CAP (pin 4) is the output of the internal reference buffer. The 2.2µf tantalum capacitor should be placed as close as possible to the grounded cap pin to provide the best switching current for the cdac throughout the conversion cycle. This capacitor also provides compensation for the output of the buffer. Using a capacitor smaller than 1µF can cause the output buffer to oscillate and there may not be enough charge available for the cdac. Capacitance values greater than 2.2µf have little effect on improving performance. See Figures 10 and 11.

The output of the buffer is capable of driving up to 1 mA into a DC load. Using an external buffer will allow the internal reference to be used for larger DC and AC loads. Do not attempt to directly drive an AC load whose output voltage is capped. This will result in reduced converter performance.

layout

that power

For best performance, connect the analog and digital power pins to the same +5V supply, and connect the analog and digital grounds together. As described in the electrical characteristics:

Reference and power outages

The ADS7807 has analog power-down and reference power-down functions via PWRD (pin 25) and REFD (pin 26), respectively. pwrd and refd high will shut down all analog circuits holding previously converted data in internal registers, provided the data has not been shifted out through the serial port. Typical power consumption in this mode is 50 microwatts. With a 2.2 microF capacitor connected to the capacitor, power recovery is typically 1 ms. Figure 11 shows the power-up recovery time relative to the capacitor capacitance value. When +5V is applied to VDIG, the digital circuitry of the ADS7807 remains active regardless of PWRD and REFD states.

pressurized water reactor

PWRD high will turn off all analog circuits except the reference. The previously converted data will be kept in the internal registers and can still be read. For pwrd high, the convert command produces meaningless data.

references

REFD high will turn off the internal 2.5V reference voltage. All other analog circuits, including the reference buffer, will be activated. When using an external reference, refd should be high to minimize power consumption and loading effects on the external reference. The characteristic impedance (high and low) of the reference buffer input is shown in Figure 10. The internal reference consumes about 5MW.

90% of the power of the ADS7807 is used in the analog circuits. The ADS7807 should be considered an analog component.

The +5V supply for the A/D converter should be separate from the +5V supply for the system's digital logic. Connecting vdig (pin 28) directly to the digital supply can degrade converter performance due to switching noise from the digital logic. For best performance, the +5V supply can be generated from any analog supply used for analog signal conditioning. A simple +5V regulator can be used if a +12V or +15V supply is present. While it is not recommended to use a digital power supply to power the converter, make sure the power supply is properly filtered. Whether using a filtered digital supply or a regulated analog supply, VDIG and VANA should be connected to the same +5V supply.

ground

There are three ground pins on the ADS7807. DGND is the digital power ground. agnd2 is the analog power ground. agnd1 is the ground reference for all analog signals inside the A/D converter. agnd1 is more susceptible to current induced voltage drops and must have a minimal resistive path back to the power supply.

All ground pins of the A/D converter should be tied to the analog ground plane and separated from the system's digital logic ground for best performance. Both analog and digital ground planes should be connected to the "system" ground as close to the power supply as possible. This helps prevent dynamic digital ground currents from modulating analog ground to power ground through the common impedance.

signal conditioning

In many cmos a/d converters, the fet switch used for sample and hold releases a large amount of charge injection, which causes the drive op amp to oscillate. The amount of charge injected due to the sampling FET switches on a similar A/D converter is approximately 5% x 10% of the structure of the charge conversion digital-to-analog converter (DAC). There is also a resistive front end that attenuates any charge released. The end result is the minimum requirement for the drive capability of the signal conditioning before the A/D converter. Any op amp enough signal in an application will be sufficient to drive the ADS7807.

The resistive front end of the ADS7807 also provides specified ±25V overvoltage protection. In most cases, this eliminates the need for an external overvoltage protection circuit.

middle latch

The parallel port of the ADS7807 has three-state outputs, but if the bus is active during conversions, an intermediate latch should be used. The tri-state output can be used to isolate the A/D converter from other peripherals on the same bus if the bus is not active during conversion.

The intermediate latch is good for any monolithic a/d converter. The internal LSB size of the ADS7807 is 38µV. Even when the A/D converter is tri-stated, transients from fast switching signals on the parallel port can couple through the substrate to the analog circuitry, resulting in degraded converter performance.

application information

transition noise

A DC input is applied to the ADS7807 and 1000 conversions are initiated. The digital output of the converter will vary in the output code due to the internal noise of the ADS7807. All 16-bit sar converters are like this. The Transition Noise Specification in the Electrical Characteristics section is a statistic that represents the one-sigma limit or rms value of these output codes.

Using the histogram to plot the output code, the distribution should be bell-shaped, with the peak of the bell-shaped curve representing the nominal output code for the input voltage value. The ±1σ, ±2σ and ±3σ distributions will represent 68.3%, 95.5% and 99.7% of all codes. Multiplying tn by 6 will give a ±3σ distribution or 99.7% of all codes. Statistically, when performing 1000 conversions, up to 3 codes may not be within the 5 code distribution. The ADS7807 has a TN of 0.8LSB and can generate 5 output codes with a distribution of ±3σ. Figures 12 and 13 show the 1000 and 10000 transformation histogram results.

average value

Converter noise can be compensated by averaging the digital codes. By averaging the transformation results, the tran-position noise will be reduced by a factor of 1/√Hz, where n is the mean. For example, averaging four conversion results will reduce tn by 1/2 to 0.4lsb. Average can only be used for input signals with frequencies close to DC.

For AC signals, a digital filter can be used for low-pass filtering and decimation of the output code. It works similarly to averaging: for every 2 decimations, the signal-to-noise ratio will increase by 3 dB.

Qspi™ interface

Figure 14 shows a simple interface between the ADS7807 and any Qspi-equipped microcontroller. This interface assumes that the conversion pulses do not come from the microcontroller and that the ADS7807 is the only serial peripheral.

Before enabling the QSPI interface, the microcontroller must be configured to monitor the slave select line. A low-to-high transition occurs when the slave is selected (SS) Starting from busy (indicating the end of the current transition), the port can be enabled. If this is not done, the microcontroller and A/D converter may be "out of sync".

Figure 15 shows another interface between the ADS7807 and a Qspi-equipped microcontroller that allows the microcontroller to issue conversion pulses while also allowing multiple peripherals to be connected to the serial bus. This interface and the following discussion assume that the master clock of the QSPI interface is 16.78MHz. Note that the serial data input of the microcontroller is connected to the msb (d7) of the ADS7807, not the serial output (sdata). Using D7 in place of the serial port provides tri-state functionality, allowing other peripherals to be connected to the MISO pin. When communication with these peripherals is required, pcs0 and pcs1 should be held high; this will hold the D7 tri state.

In this configuration, the QSPI interface is actually set up to perform two different serial transfers. The first, an 8-bit transfer, causes pcs0(r/c) and pcs1(cs) to go low, starting the inverter-zion. The second is a 16-bit transfer that only causes pcs1 (cs) to go low. Valid data will be transmitted at this time.

For both transfers, the dt register (post-transfer delay) is used to cause a delay of 19 microseconds. The interface is also set to wrap to the beginning of the queue. In this way, QSPI is a state machine that generates proper timing for the ads7807. Therefore, the timing is locked to the crystal-based timing of the microcontroller, rather than the interrupt drive. Therefore, the interface is suitable for both AC and DC measurements.

For fastest conversion rate, baud rate should be set to 2 (4.19MHz SCK), dt to 10, first serial transfer to 8 bits, second to 16 bits, dsck disabled (in command control bytes). This will allow a maximum conversion rate of 23 kHz. For slower rates, dt should be increased.

Do not slow down SCK, as this may increase the effect of the conversion result or accidentally start a second conversion during the first 8-bit transfer.

Also, cpol and cpha should be set to zero (sck is usually low and data is captured on the rising edge). The command-control byte for 8-bit transfers should be set to 20 hours, and the command-control byte for 16-bit transfers should be set to 61 hours.

SPI™ interface

The spi interface is usually only capable of 8-bit data transfer. For some microcontrollers with a spi interface, data may be received in a similar way, as shown in Figure 14 for the qspi interface. The microcontroller needs to fetch the 8 most significant bits before the content is overwritten by the least significant bits.

A modified version of the QSPI interface shown in Figure 15 may be possible. For most microcontrollers with a spi interface, automatic generation of transition pulses is not possible and must be done in software. This will limit the interface for "DC" applications due to insufficient jitter performance of the switching pulse itself.

DSP56000 interface

The DSP56000 serial interface has an SPI compatible mode and some enhancements. Figure 16 shows the interface between the ADS7807 and the DSP56000, very similar to the Qspi interface shown in Figure 14. As mentioned in the QSPI section, the dsp56000 must be programmed to enable the interface when a low-to-high transition on SC1 is observed (busy high at the end of the transition).

The DSP56000 can also provide switching pulses by including a monostable multivibrator, as shown in Figure 17. The receive and transmit parts of the interface are separated (asynchronous mode), and the transmit part is set to generate word-length frame sync every other transmit frame (frame rate allocator set to 2). The prescaler modulus should be set to 3.

The monostable multivibrator in this circuit will provide different pulse widths for the conversion pulses. The pulse width will be determined by the external R and C values used by the multivibrator. The 74HCT123N datasheet says the pulse width is (0.7)rc. Choosing a pulse width close to the minimum specified in this data sheet will provide the best performance. See the "Starting Conversion" section of this datasheet for more information on the conversion pulse width.

The maximum conversion rate of the 20.48 MHz DSP56000 is exactly 40kHz. Note that this is not the case with the ADS7806. See the ADS7806 data sheet (SBAS021B) for details.