Features

8-channel programmable differential or single-ended multiplexer; programmable acquisition time and user-controllable throughput; programmable data bus width (8/13 bits); built-in sample and hold; programmable auto-calibration and auto-zero cycles; low-power standby mode; no missing code.

application

Medical devices; process control systems; test equipment; data logging; inertial guidance.

Main Specifications

(fclk=12 MHz); resolution: 12 bits + sign; 13 bits conversion time: 3.6 μs, max; 13 bits throughput: 216 ksamples/s, min; integral linearity error (Ile): ±1 LSB, max; Single Supply: +5 V ±10%; VIN Range: Ground to VA+ 8226 ; Power Consumption – Normal Operation: 34 mW max – Standby Mode: 75 μW max.

illustrate

Operating on a 5V supply, the ADC12048 is a 12-bit + sign, parallel I/O, self-calibrating, sampling analog-to-digital converter (ADC) eight-input fully differential analog multiplexer. The maximum sampling rate is 216 kHz. On request, the ADC undergoes a self-calibration process to adjust for linearity, zero, and full-scale errors. The ADC12048's 8-channel multiplexer is software programmable to operate in single-ended differential or pseudo-differential mode in various combinations. The fully differential mux and 12-bit + sign ADC allow the difference between the two signals to be digitized.

The ADC12048 can be configured to work with many popular microprocessors/microcontrollers and DSPs including TL's HPC series, Intel386 and 8051, tms320c25, Motorola mc68hc11/16, Hitachi 64180 as well as analog devices ADSP21XX.

Function description

The ADC12048 is programmed through a digital interface supporting an 8-bit or 16-bit data bus. The digital interface consists of a 13-bit data input/output bus (D12–d0), digital control signals, and two internal registers: a write-only 13-bit configuration register and a read-only 13-bit data register.

The configuration registers program the functionality of the ADC12048. The 13 bits of the configuration register are divided into 7 fields. Each field controls a specific function of the ADC12048: multiplexer channel selection, acquisition time, synchronous or asynchronous conversion, mode of operation, and data bus size.

Features and Operating Modes

Optional bus width

The ADC12048 can be programmed to interface with an 8-bit or 16-bit data bus. The BW bit (B12) in the configuration register controls the bus size. If the bw bit is cleared, the bus width is set to 8 bits (d7–d0 are active, d12–d8 are tri-stated); if the bw bit is set, the bus width is set to 13 bits (d12–d0 are active) . At power up, the bus width defaults to 8 bits and any initial programming of the ADC12048 should take this into account.

In 8-bit mode, the configuration registers are byte-accessible. The hb bit in the lower byte of the configuration register is used to access the upper byte. If the hb bit is set to write to the low byte, the next byte written to the ADC will be placed in the high byte of the configuration register. After data is written to the upper byte of the configuration register, the hb bit is automatically cleared, causing the next byte written to adc to go to the next byte of the configuration register. When reading the ADC in 8-bit mode, the first read cycle places the next byte of the data register on the data bus, followed by a byte in the next read cycle.

In 13-bit mode, the HB bit is a don't care condition and all bits of the data and configuration registers can be accessed with a single read or write cycle. Since the bus width of the ADC12048 defaults to 8 bits after power-on, the first operation when 13-bit mode is required must be set to a bus width of 13 bits.

W mode

The wmode pin is used to determine the active edge of the write pulse. The state of this pin determines which edge of the wr signal will cause the ADC to lock the data. It depends on the processor. If the processor has valid data on the bus during the falling edge of the wr signal, the wmode pin must be tied to vd+. This will cause the ADC to latch data on the falling edge of the wr signal. If the data is valid on the rising edge of the wr signal, the wmode pin must be tied to dgnd so that the ADC latches onto the data on the rising edge of the wr signal.

input multiplexer

The ADC12048 features an eight-channel input multiplexer whose COM inputs can be used in single-ended, pseudo-differential, or fully differential mode. The mux select bits (b3–b0) in the configuration register determine which channels appear at the muxout+ and muxout multiplexer output pins. Analog signal conditioning with fixed gain amplifiers, programmable gain amplifiers, filters, and other processing circuits can be used at the output of the multiplexer before being applied to the ADC input. ADCIN+ and ADCIN- are the fully differential non-inverting (positive) and inverting (negative) inputs to the ADC12048's analog-to-digital converter (ADC). If the signal output of the multiplexer does not require external signal conditioning, muxout+ should be connected to adcin+ and muxout- should be connected to adcin-.

The analog input multiplexer can be set to operate in one of eight differential or eight single-ended (COM input as zero reference) modes. In differential mode, the analog inputs are paired as follows: ch0 with ch1, ch2 with ch3, ch4 with ch5, ch6 with ch7. Input channel pairs can be connected to the muxout+ and muxout- pins in any order. In single-ended mode, one input channel ch0 to ch7 can be assigned to muxout+, while muxout- is always assigned to the com input.

Standby mode

ADC12048 has a low power mode (75μW@5V). This mode is entered when an alternate command is written in the command field of the configuration register. A logic low on the stdby output pin indicates that the ADC12048 is in standby mode. Any command other than an alternate command written to the configuration register will take the ADC12048 out of alternate mode. Once the ADC12048 is requested to exit standby mode, the STDBY pin will switch to logic "1" immediately. When the ADC actually comes out of standby mode and is ready for normal operation, the RDY pin will be asserted low. The ADC12048 defaults to standby mode after hardware power-up. This can be verified by checking the logic low state of the stdby pin.

Synchronous/Asynchronous Mode

The ADC12048 can be programmed to operate in synchronous (sync-in) or asynchronous (sync-out) mode. To enter sync mode, the sync bit in the configuration register must be set. After the hardware is powered up, the ADC12048 is in synchronous mode. In this mode, the sync pins are programmed as inputs and transitions are synchronized to the rising edge of the signal applied to the sync pins. In sync mode, the acquisition time can also be controlled by a sync signal. See Figures 14 and 18. When the sync bit is cleared, the ADC is in asynchronous mode and the sync pins are programmed as outputs. In asynchronous mode, the signal at the synchronous pin indicates the state of the converter. This pin is high when the converter is performing a conversion. See Figures 17 and 15.

Selectable acquisition time

The internal sample/hold circuit of the ADC120 48 samples the input voltage by connecting the input to an internal sampling capacitor (approximately 70 pF), which has an effective resistance equal to the multiplexer "on" resistance (300Ωmax) plus the analog switch at the sample/hold "on" resistor at the input of the circuit (2500Ω typical). and the effective output resistance of the power supply. For the conversion result to be accurate, the period during which the sampling capacitor is connected to the power supply ("acquisition time") must be long enough to charge the capacitor to within a fraction of the input voltage lsb. The acquisition time of 750ns is sufficient when the external power supply resistance is less than 1kΩ and any active or reactive power supply circuit settles to 12 bits in less than 500ns. When source resistance or source settling time exceeds these limits, acquisition time must also be increased to maintain accuracy.

In asynchronous (synchronous) mode, the acquisition time is controlled by an internal counter. The minimum capture period is 9 clock cycles, corresponding to a nominal value of 750ns at a clock frequency of 12mhz. Bits b4 and b5 of the configuration register are used to select the acquisition time from four possible values (9, 15, 47 or 79 clock cycles). Since the acquisition time in asynchronous mode is based on the count of clock cycles, it is also inversely proportional to the clock frequency:

Note that the actual acquisition time will be longer than tacq because acquisition starts when the multiplexer channel changes or when rdy goes low, if the multiplexer channel has not changed. After the read is performed, RDY goes high, starting the TACQ counter (see Figure 13).

In synchronous (sync-in) mode, bits b4 and b5 are ignored and the acquisition time depends on the sync signal applied on the sync pin. If a new mux channel is selected at the start of a conversion, the acquisition period begins with the active edge of the wr signal locked in the new mux channel. If no new mux channel is selected, the acquisition cycle begins with the falling edge of rdy, which occurs at the end of the previous conversion (or at the end of the autozero or autocalibration process). When sync goes high, the acquisition cycle ends.

To estimate the acquisition time required for an accurate conversion when the source resistance is greater than 1kΩ, use the following expression:

Where: Rs is the source resistance; rm is the mux "on" resistance; RS/H is the sample/hold "on" resistance.

If the settling time of the source is greater than 500ns, the acquisition time should be about 300ns longer than the settling time for "good" smooth settling characteristics.

full calibration cycle

The ADC's linearity and offset errors are compensated for throughout the calibration cycle. The converter's DC specification can only be specified after a full calibration. The entire calibration cycle is initiated by writing a fulcal command to the ADC12048. During a full calibration, the offset error is measured eight times, averaged, and a correction factor created. The offset correction coefficients are stored in internal offset correction registers.

The overall linearity correction is achieved by correcting the capacitance mismatch of the internal DACs. Compare each capacitor 8 times with all remaining smaller value capacitors. The errors are averaged and correction coefficients are generated.

Once the converter is calibrated, the arithmetic logic unit (ALU) uses the offset and linearity correction coefficients to reduce the conversion offset and linearity error to within specified ranges.

Auto-zero cycle

During an auto-zero cycle, the offset is measured only once, and a correction factor is created and stored in the internal offset register. The auto-zero cycle is initiated by writing an auto-zero command to the ADC12048.

digital interface

The digital control signals are cs, rd, wr, rdy and stdby. Certain timing relationships are associated with the interaction of these signals. See the digital timing diagram for detailed timing specifications. An active low rdy signal indicates when an event begins and ends. It is recommended to access the ADC12048 only when the RDY signal is low. It is in this state that the ADC12048 is ready to accept new commands. This will minimize the effect of switching the data bus on the noise generated by the ADC. The only exception is when the ADC12048 is in standby mode, when RDY is high and the STDBY signal is low. The ADC12048 is in standby mode when powered up or when a standby command is issued. A ful cal, auto zero, reset or start command will bring the ADC12048 out of standby mode. This can be observed by monitoring the state of the rdy and stdby signals. When the ADC12048 leaves standby mode, the RDY signal will go low and the STDBY signal will go high.

The following describes the state of the digital control signals for each programming event in 8-bit and 13-bit modes. Before issuing each command, RDY should be low unless the device is in standby mode.

ful-cal or auto-zero command

8-bit mode: The first write to the ADC12048 will place the data in the low byte of the configuration register. This byte must have the hb bit (b7) set in order to access the upper byte of the configuration register on the next write cycle. During the second write cycle, a ful cal or auto zero command must be issued. The edge of the second write pulse on the wr pin will force the rdy signal high. At this point, the converter begins a full calibration or autozero cycle. The RDY signal will automatically go low when a full calibration or auto-zero cycle is complete.

13-bit mode: In a single write cycle, a ful cal or auto zero command must be written to the ADC12048. The edge of the wr signal will force rdy high. At this point, the converter begins a full calibration or autozero cycle. The RDY signal will automatically go low when a full calibration or auto-zero cycle is complete.

Boot conversion: start command

To fully describe the events associated with the start command, both sync-out and sync-in modes must be considered.

Synchronous Asynchronous

8-bit mode: The first byte written to the ADC12048 should set the MUX channel, acquisition time and the HB bit. The second byte should clear the sync bit, write the start command and clear the bw bit. To initiate a conversion, two reads from the ADC12048 must be performed. The rising edge of the second read pulse will force the RDY pin high and begin the programmed acquisition time selected by bits B5 and B4 of the configuration register. The sync pin will go high to indicate that the conversion sequence has started after the acquisition cycle has ended. After the conversion is complete, the RDY and sync signals will be low. At this point, new information, such as the new mux channel, acquisition time, and operation commands, can be written to the configuration registers, or it can remain unchanged. Assuming the start command is in the configuration register, the previous conversion can be read. The first read places the low-order byte of the conversion result contained in the data register on the data bus. The second read will store the upper byte of the conversion result in the data register on the data bus. The rising edge of the second read pulse will start another sequence of conversions and raise the rdy and sync signals appropriately.

13-bit mode: The multiplexer channel and acquisition time should be set, the sync bit should be cleared, and a start command should be issued on a single write to the ADC12048. In order to initiate a conversion, a read from the ADC12048 must be performed. A rising edge of the read signal will force the rdy signal high and begin the programmed acquisition time selected by bits b5 and b4 of the configuration register. The sync pin will go high to indicate that the conversion sequence has started after the acquisition cycle has ended. After the conversion is complete, the RDY and sync signals will be low. At this point, new information, such as the new mux channel, acquisition time, and operation commands, can be written to the configuration registers, or it can remain unchanged. Using the START command in the configuration register, the data read from the ADC12048 will place the entire 13-bit conversion result stored in the data register on the data bus on the data bus. The rising edge of the read pulse will immediately force the RDY output high. Then, as the acquisition time programmed in configuration register bits b5 and b4 elapses, sync will go high.

sync/sync

For the sync-in case, assume a series of sync pulses at the desired sample rate are applied at the sync pin of the ADC12048.

8-bit mode: The first byte written to the ADC12048 should set the MUX channel and the HB bit. The second byte should set the sync bit, write the start command and clear the bw bit.

A rising edge on the sync pin or the second rising edge of two consecutive reads from the ADC12048 will force the RDY signal high. It is recommended to use the action read from the ADC12048 (rather than the rising edge of the sync signal) to boost the RDY signal. In sync mode, only the rising edge of the sync signal will start the conversion cycle. The rising edge of synchronization also ends the acquisition cycle. The acquisition cycle begins after the write cycle containing the mux channel information. The selected mux channel is sampled after the rising edge of the wr signal until the rising edge of the sync pulse, at which point the signal is held and conversion begins. After the conversion is complete, the RDY signal will go low. If desired, new mux channels and/or operation commands can be written to the configuration registers at this point. Retrieving the entire 13-bit conversion result from the ADC12048's data register requires two consecutive read cycles. The first read will place the next byte of the conversion result contained in the data register on the data bus on the data bus. The second read will store the upper byte of the conversion result in the data register on the data bus. Using the START command in the configuration register, the rising edge of the second read pulse will raise the RDY signal and start the conversion cycle after the rising edge of the sync pin.

13-bit mode: The MUX channel should be selected, the sync bit should be set, and a start command should be issued on a single write to the ADC12048. A rising edge on the sync or RD pin will force the RDY signal high. It is recommended to use the action read from the ADC12048 (rather than the rising edge of the sync signal) to boost the RDY signal. This will ensure that the conversion result is read during the acquisition of the next conversion cycle, thus eliminating the read of it when the ADC12048 performs the conversion. Noise from accessing the adc12048 while it is converting may degrade the conversion result. In sync mode, only the rising edge of the sync signal will start the conversion cycle. At the end of the conversion cycle, the RDY signal will go low. The acquisition time is controlled by the synchronization signal. The acquisition cycle begins after the write cycle containing the mux channel information. The selected mux channel is sampled after the rising edge of the wr signal until the rising edge of the sync pulse, at which point the signal is held and conversion begins. If desired, new mux channels and/or operation commands can be written to the configuration registers at this point. Using the START command in the configuration register, a read from the ADC12048 will place the entire conversion result stored in the data register on the data bus, and the rising edge of the read pulse will force the RDY signal high. The selected mux channel will be sampled until a rising edge occurs on the sync pin, at which point the sampled signal will be held and the conversion cycle will begin.

Alternate command

8-bit mode: The first byte written to the ADC12048 should set the HB bit in the configuration register (bit B7). The second byte must issue an alternate command (bits b11, b10, b9 = 0, 0, 0).

13-bit mode: Alternate commands must be issued to the ADC12048 in a single write (bits b11, b10, b9 = 0, 0, 0).

reset

The reset command puts the ADC12048 into a ready state and forces the RDY signal low. The reset command can be used to interrupt the ADC12048 while the ADC12048 is performing a conversion, full calibration, or auto-zero cycle. It can also be used to bring the ADC12048 out of standby mode.

Simulation Application Information

reference voltage

The ADC12048 has two reference inputs, VREF+ and VREF-. They define the zero-to-full-scale range of the analog input signal, where 4095 positive and 4096 negative codes exist. The reference inputs can be connected to the entire supply voltage range (VREF-=AgNd, VREF+=VA+), or they can be connected to different voltages when other input ranges are required. The reference input of the ADC12048 has an instantaneous capacitive switch current. The voltage sources driving VREF+ and VREF- must have very low output impedance and noise, and must be adequately bypassed. The circuit in Figure 48 is an example of a very stable reference source.

The ADC12048 can be used for ratiometric measurements or absolute reference applications. In a ratiometric measurement system, the analog input voltage is proportional to the analog-to-digital converter reference voltage. This technique relaxes the system reference requirement as the analog input voltage varies with the ADC reference. The system power supply can be used as a reference voltage by connecting the VREF+ pin to VA+ and the VREF- pin to AGND. For absolute accuracy, a time and temperature stable voltage source can be connected to the reference input when the analog input voltage varies between very specific voltage limits. Typically, the magnitude of the reference voltage requires an initial adjustment for the full-scale error due to a zero reference voltage.

The reference voltage input is not fully differential. If (VREF+–(VREF-) is below 1V, the ADC12048 will not generate correct conversions. Figure 47 shows the allowable relationship between VREF+ and VREF-).

Output digital code and analog input voltage

The fully differential 12-bit + sign ADC of the ADC12048 produces a 2's complement output, which is found by using the equation shown below:

Round the result to the nearest integer value between -4096 and 4095.

Input Current

At the beginning of the acquisition window (tacqsynout), charging current (due to capacitive switching) flows through the analog input pins (ch0–ch7, adcin+ and adcin-, and com). The peak value of this input current will depend on the amplitude and frequency of the applied input voltage, source impedance and input on-resistance. When MUXOUT+ is connected to ADCIN+ and MUXOUT- is connected to ADCIN-, the power-on resistance is typically 2800Ω. Bypassing the MUX and using only the ADCIN+ and ADCIN- inputs, the power-on resistance is typically 2500Ω.

For low-impedance voltage sources (less than 1000Ω at 12 MHz operation), the input charge current will decay to a value that will not produce any conversion error before the end of the default sample-and-hold (s/h) acquisition time (9 clock cycles). For higher source impedances (greater than 1000Ω when operating at 12MHz), the S/H acquisition time should be increased to stabilize the charging current within the specified range. In asynchronous mode, the acquisition time can be increased to 15, 47 or 79 clock cycles. If a different acquisition time is required, the synchronization mode can be used to fully control the acquisition time.

Input Bypass Capacitor

External capacitors (0.01µf–0.1µf) can be connected between the analog input pins (CH0–CH7) and analog ground to filter any noise caused by non-conductive pickup associated with long leads.

Power Considerations

Power supply decoupling and bypassing of high-resolution ADCs is an important design task. Noise peaks on VA+ (analog power) or VD+ (digital power) can cause conversion errors. The analog comparators used in ADCs will respond to power supply noise and will make wrong conversion decisions. ADCs are particularly sensitive to power supply spikes that occur during auto-zero or linear calibration cycles.

The ADC12048 is designed to operate on a single +5V supply. Separate power and ground pins for the analog and digital portions of the circuit allow separate external bypassing. To minimize power supply noise and ripple, adequate bypass capacitors should be placed directly between the power supply pins and their associated grounds. Both power pins should be connected to the same power supply. In systems with separate analog and digital supplies, the ADC should be powered from the analog supply. A minimum of 10µf tantalum electrolytic capacitors and 0.1µf monolithic ceramic capacitors are recommended in parallel to bypass each supply. A key consideration for these capacitors is to have low series resistance and inductance. Capacitors should be placed as close as possible to the power and ground pins, and smaller capacitors should be placed closer to the device. Capacitors should also have the shortest possible leads to minimize series lead inductance. Surface mount chip capacitors are optimal in this regard and should be used whenever possible.

Sufficient bypassing (high value electrolytic capacitors) should be placed at the power entry point when the power regulator is off-board. The value of the capacitor depends on the total supply current to the circuit on the PC board. All supply current should be supplied by the capacitor, not drawn from the external supply line, and the external supply should charge the capacitor at a steady rate.

ADC has two vd+ and dgnd pins. It is recommended to bypass each of these vd+ pins individually to dgnd with a 0.1µf plus 10µf capacitor. The layout diagram in Figure 49 shows the suggested location of the power supply bypass capacitors.

PC Board Layout and Grounding Considerations

To get the best performance from the ADC12048, the printed circuit board should have separate analog and digital ground planes. The reason for using two ground planes is to prevent digital and analog ground currents from sharing the same path until they reach a very low impedance power point. This will prevent the injection of noisy digital switch currents into the analog ground.

Figure 49 illustrates a good layout for ground, power and reference input bypass capacitors. It shows the layout using the 44-pin PLCC socket and through-hole components. The pqfp package should also use a similar approach.

The analog ground plane should include the area under the analog pins and any other analog components such as reference circuits, input amplifiers, signal conditioning circuits, and analog signal traces.

The digital ground plane should include the digital circuitry and the area under the ADC12048's digital input/output pins. It is very important to have a continuous digital subsurface data and clock trace. This reduces overshoot/overshoot and high frequency ringing on these lines that can capacitively couple to analog circuit sections through stray capacitance.

agnd and dgnd in ADC12048 are not connected together internally. They should be connected together on the chip's PC board. This will provide the shortest return path for the signals exchanged between the analog and digital sections inside the ADC.

It is also a good design practice to have power plane layers on the pc board. This will improve power bypass (effective distributed capacitance between the power and ground plane layers) and voltage drops on the power lines. However, powered aircraft do not have the same satisfactory performance as ground-based aircraft. If a power plane is used, it should be split into two planes, and the zones and connections should follow the same guidelines as the ground plane. Each power plane should be laid out on its associated ground plane, avoiding any overlap between power planes and different types of ground planes. When not using a power strip, it is recommended to use separate power wires for the VA+ and VD+ pins from a low impedance power point (regulator output or power entry point from a PC board). This will help ensure that noisy digital supplies do not damage analog supplies.

When measuring AC input signals, any crosstalk between the analog input/output lines and the reference lines (CH0–CH7, muxout±, ADC in±, vref±) should be minimized. Crosstalk is minimized by reducing stray capacitance between lines. This can be achieved by increasing the gap between tracks, keeping tracks as short as possible, by placing tracks on different sides of the agnd plane or running agnd tracks between them.

Figure 49 also shows the reference input bypass capacitor. The reference input here is considered differential. Performance is improved by having a 0.1µf capacitor between vref+ and vref-, and by bypassing in a similar manner to the power pins described. When using a single-ended reference, VREF- is connected to AGND and only two capacitors (0.1µf + 10µf) are used between VREF+ and VREF-. It is recommended to connect the agnd side of these capacitors directly to the vref- instead of connecting the vref- and the ground sides of the capacitors to the ground plane separately. This provides a significantly lower pedal connection when using surface mount technology.