Features

Logically 16kbit Ferroelectric Random Access Memory (F-RAM) organized by 2K×8 High Endurance 100 Trillion (1014) Read/Write 151 Years Data Retention Period (see Data Retention and Endurance Table) nodelay 8482 ; Write Advanced High Reliability Ferroelectric Process Fast 2-Wire Serial Interface (I2C) Direct Hardware Replacement of Serial (I2C) EEPROM Supports 100 kHz and 400 kHz Traditional Timing Low Power 100 μA Active Power at 100 kHz Current 3μA (typ) Standby Current Voltage Operation: VDD=2.7 V to 3.65 V Industrial Temperature: –40°C to +85°C Package 8-pin Small Outline Integrated Circuit (SOIC) Package 8-pin Dual Flat No-lead (DFN) Package compliant with Restriction of Hazardous Substances (RoHS)

Function description

fm24cl16b is a 16kbit non-volatile memory using advanced ferroelectric technology. Ferroelectric random access memory or f-ram is non-volatile and performs read and write operations. Like it provides 151 years of reliable data retention while eliminating the complexity, overhead and reliability issues caused by non-volatility such as eeprom at the system level. Unlike eeprom, fm24cl16b is at bus speed. No write delays are incurred. Data is successfully written to the device after each byte of the memory array is transferred to the device. The next bus cycle can start without data polling. In addition, the product offers memory with considerable write persistence compared to other non-volatiles. In addition, f-rams exhibit lower power consumption during write operations because the write operation does not require an increase in the supply voltage of the internal write circuit. The FM24CL16 B is capable of supporting 1014 read/write cycles, or 100 million times more write cycles than the eeprom. These features make the FM24CL16B ideal for non-volatile memory applications requiring frequent or fast writes. Examples include data logging, where for places where industrial control is required, cycles can be critical. Long write times to EEPROM can result in data loss. This combination of features allows more frequent data writes to reduce system overhead. The FM24CL16B offers substantial benefits to serial users (I2C) EEPROM as a hardware replacement. The unit is guaranteed to have a specified temperature range of -40°C to +85°C over the industrial temperature range.

Overview: The FM24CL16B is a serial F-RAM memory. The memory array is logically organized as 2048 x 8 bits and uses the industry standard I2C interface. The functional operation of F-RAM is similar to a serial (I2C) EEPROM. The main difference between the FM24CL16B and the serial (I2C) EEPROM with the same pinout is f-ram's superior write performance, high endurance, and low power consumption. Memory Structure When accessing the FM24CL16B, the user address is 2K locations of 8 data bits each. These eight data shift bits go in and out continuously. Use the I2C access address protocol, including a slave address (used to distinguish other non-memory devices), row address, and segment address. The row address consists of 8 bits, specifying 256 rows. The 3-bit segment address specifies one of the 8 segments in each row. The 11-bit full address specifies that each byte address is unique. Access times for memory operations are essentially zero, exceeding those required by serial protocols. That is, the memory is read or written at the speed of the I2C bus. Unlike serial (I2C) EEPROMs, there is no need to poll the device ready status because writes occur at bus speed. By the time a new bus transaction can be transferred to the device, the write operation is complete. This is in the interface section. Note that the FM24CL16B does not contain power management circuitry other than a simple internal power-on reset. It is the user's responsibility to ensure that VDD is within the data sheet tolerance to prevent erroneous operation. I2C Interface The FM24CL16B uses a bidirectional I2C bus protocol with very little pin or board space. The figure shows a typical system based on the fm24cl16b configuration system of the microcontroller. The industry standard I2C bus is familiar to many users but is described in this section. By convention, any device that sends data to the bus is a transmitter when the target device for this data is a receiver. The device that controls the bus is the master device. Mainly responsible for generating clock signals for all operations. Any controlled device on the bus is a slave. This FM24CL16B is always a slave device. The bus protocol consists of sda and SCL signals. There are four conditions including start, stop, data bit or acknowledgment.

Stop Condition (P) Indicates a stop state when the bus master drives the sda. From low to high when the SCL signal is high. All operations using the FM24CL16B should end in a stopped state. If the operation is in progress it will be aborted when the assertion stops. To assert a stop condition. START CONDITION When the bus master drives SDA, a START condition is indicated when the SCL signal goes high to low. All commands should be preceded by a start condition. The surgical procedure can be passed at any time. Aborting the operation with the start condition will prepare the FM24CL16B for new operation. If during operation, the supply falls below the specified VDD minimum, the system should be doing another.

Data/Address Transfers All data transfers (including addresses) have the SCL signal high. Except in the above two cases, the SDA signal should not change when SCL is high. Confirmed/Unconfirmed Confirmation occurs when the 8th data bit is transferred in any transaction. In this state, the transmitter should release the SDA bus to allow the receiver to drive it. This receiver drives the SDA signal low to acknowledge receipt of the byte. If the receiver does not drive SDA low, a NO is acknowledged and the operation is aborted. The recipient will deny it for two different reasons. The first is the byte transfer failure. In this case, no acknowledgement stops the current operation so that the device can speak again. This allows in the event of communication errors. Second, and most commonly, the recipient does not admit to intentionally ending the procedure. For example, when operating during a read, the FM24CL16B will continue to put data on the bus as long as the receiver sends an acknowledgment (and clock). When the read operation is complete and no more data is needed, the receiver cannot acknowledge the last byte. If the receiver acknowledges the last byte, this will cause the FM24CL16B to try to drive the bus on the next clock while the master is sending a new command like stop.

The slave address fm24cl16b expects the first byte condition after boot is the slave address. As shown, the slave address contains the device type, whether the memory page is accessed, and whether a specified transaction is a read or a letter. Bits 7-4 are the device type, for the FM24CL16B. These bits allow other function types to reside on the I2C bus in the same address range. Bits 3-1 are page selection. It specifies a memory block of 256 bytes, i.e. for the current operation. Bit 0 is the read/write bit (turn right). R/W='1' means read operation, R/W='0' means write operation.

Addressing Overview (Word Address) After the FM24CL16B (as a receiver) acknowledges the slave address, the master can place a write operation on the bus. The word address is the address in combination with the 3-bit page selection specifying exactly the byte to be written. The full 11-bit address is locked internally. The word address is not present for read operations, although the 3-bit page select is locked internally. Always read using the lower 8 bits inside the address latch. That is, reads always start at the address following the previous address. A random read address can be loaded by performing a write operation as described below. After each data byte is transferred, just on acknowledgment, the FM24CL16B increments the internal address latch. This allows the use of no additional addresses. When arriving after the last address (7ffh), the address latch will roll over to 000 hours. There is no limit to the number of bytes that can be accessed by a read or write operations. Data transfer After the address byte has been transferred, the data transfer can begin between the bus master and the FM24CL16B. For a read operation the FM24CL16B will place 8 data bits on the bus and wait for an acknowledgment. If confirmed, the FM24CL16B will transmit the next sequential byte. If no acknowledgment is sent, the FM24CL16B will end the read operation. For write operations, the FM24CL16B will accept 8 data bits from the host and then transmit. All data transfers occur msb (most significant bit) first. Memory Operation The FM24CL16B is designed to operate very similarly to other I2C interface memory products. The main difference is due to the higher performance write capability of F-RAM technology. These improvements have resulted in some differences when writing between the FM24CL16B and a similarly configured EEPROM. Complete operations for writing and reading.

There are two basic types of read operations. They are the latest address read and the selective address read. To read in the current address, the FM24CL16B uses the internal address latch to provide the lower 8 address bits. In a selective read, the user performs the process of setting these lower address bits to specific values. Current Address and Sequential Read As mentioned above, the FM24CL16B uses internal latches to provide the lower 8-bit address for read operations. A current address read uses the existing value in the address latch as the starting location for the read operation. The system starts from the address immediately following the last operation. To perform a current address read, the bus master provides the slave address with the LSB set to "1". This represents a read request operation. The three-page select bit address in the slave specifies the memory block for read operations. After receiving the complete slave address, the FM24CL16B will begin to shift out data from the current address for the next clock. The current address is the slave's 3-bit address combined with the internal 8-bit address latch. The bus master can read any number of bytes starting at the current address. So a sequential read is just a current read address through a multibyte transfer. The internal address counter will increment after each byte. Note that each time the bus master acknowledges a byte indicates that the FM24CL16B should be in the next sequential byte. There are four ways to properly terminate a read operation. If the read is not properly terminated, it is likely that a bus will be created when the FM24CL16B tries to read additional data onto the bus. The four valid methods are: 1. The bus master issues a disable response at 9 o'clock to cycle and stop in the 10th clock cycle. As shown in the chart below. This is the first choice. 2. The bus master issues an inhibit response at 9 o'clock to start the cycle on the 10th. 3. The bus master issues a stop command in the ninth clock cycle. 4. The bus master issues a start on the 9th clock cycle. If the internal address reaches 7ffh, it wraps around to 000h on the next read cycle. The figure below shows the correct operation of the current address read.

Selective (random) read There is a simple technique that allows the user to randomly select an address location as the starting point for a read operation. This consists of using the first two bytes of a write operation to set the internal address followed by a subsequent read operation. To perform a selective read, the bus master sends the address with the slave LSB (R/W) set to 0. Specifies the write operation. According to the write protocol, the bus master sends loads into the internal address latches. After the FM24CL16B acknowledges the word address, the bus master issues a start condition. This will also abort the write operation and allow the read command issued with the slave address lsb set to '1'. The operation is now to read the current address.

The Endurance FM24C16B operates internally with a read and restore function mechanism. Therefore, endurance cycles apply to read or write cycles. The memory structure is based on an array of rows and columns. Every read or write access results in an entire row of endurance cycles. In FM24C16B, a line is 64 a bit wide. Every 8-byte boundary marks a new row. By frequently ensuring that the data being accessed is in a different row. Anyway, Fram at 1MHz I2C, read and write endurance is practically unlimited speed. Even with 3000 accesses to the same row per second, 1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.