feature

Fast 12-bit adc with 220 ksps throughput; 8-lead SOIC; single 5 V supply operation; high speed, flexible, serial interface; allows interfacing with 3V processors; on-chip track/hold amplifier; selection of input ranges; AD7898- 10 is 10 V; AD7898-3 is 2.5 V; high input impedance; low power: 22.5 mW max.

General Instructions

The AD7898 is a fast 12-bit ADC that operates from a 5V supply and is packaged in a small 8-lead SOIC package. This section contains the successive approximation A/D converter, on-chip track/hold amplifier, on-chip clock and high-speed serial interface.

The AD7898 offers two modes of operation. In Mode 0, the conversion is controlled by the convst input and the conversion initiation process is controlled by the internal clock oscillator. In this mode, the serial interface consists of three wires, and the AD7898 can achieve a throughput of 220 ksps. In Mode 1, the conversion process is controlled by an externally applied SCLK to access data from the part during conversion. In this mode, the serial interface consists of three wires and the AD7898 has a throughput of up to 220 ksps.

In addition to traditional dc accuracy specifications, such as linearity, full scale, and offset error, the AD7898 dynamic performance parameters are specified, including harmonic distortion and signal-to-noise ratio. The part accepts an analog input range of ±10 V (AD7898-10) and ±2.5 V (AD7898-3), is powered by a single 5 V supply, and consumes only 22.5 megawatts of maximum power. This part is available in an 8-lead Small Outline Integrated Circuit (SOIC).

Product Highlights

1. Fast 12-bit ADC in 8-wire package

The AD7898 contains a 220 ksps ADC, a track/hold amplifier, control logic, and a high-speed serial interface, all in an 8-lead package. This saves a lot of space for other solutions.

2. Low power, single power supply operation

The AD7898 is powered by a 5-volt supply and consumes only 22.5 megawatts. The VDrive function allows a direct interface to a 3V or 5V processor in a VDD-independent system.

3. Flexible, high-speed serial interface

This part provides a flexible, high-speed serial interface. There are two different modes of operation. Mode 0 provides a three-wire interface that can be accessed from the AD7898 when data conversion is complete. Mode 1 provides a three-wire interface to the data accessed during conversion.

4. Power off mode

The AD7898 provides a proprietary power-down function when operating in Mode 1, making the part ideal for portable or handheld applications.

term signal-to-noise ratio

This is the signal-to-noise ratio (noise + distortion) measured at the output of the A/D converter. The signal is the rms amplitude of the fundamental wave. Noise is the rms sum of all non-fundamental signals up to half the sampling frequency (fs/2), except DC. The ratio depends on the number of quantization levels in the digitization process; the more levels, the less quantization noise. The theoretical signal-to-noise ratio of an ideal n-bit converter with a sine wave input is:

So for a 12-bit converter, that's 74 db.

total harmonic distortion

Total Harmonic Distortion (thd) is the ratio of the root mean square sum of harmonics to the fundamental. For the AD7898, it is defined as:

where v1 is the rms amplitude of the fundamental and v2, v3, v4, v5 and v6 are the rms amplitudes of the second to sixth harmonics.

Peak harmonics or spurious noise

Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component (up to fs/2, excluding dc) in the ADC output spectrum to the rms value of the fundamental. Typically, the value of this specification is determined by the largest harmonic in the spectrum, but for the part of the harmonic buried in the noise floor, it will be the noise peak.

Intermodulation Distortion

When the input consists of two sine waves of frequencies fa and fb, any active device with nonlinearity will produce distortion products at the sum and difference frequencies of mfa±nfb, where m, n = 0, 1, 2, 3 Wait. An intermodulation term is a term for which neither m nor n is equal to zero. For example, second-order terms include (fa+fb) and (fa-fb), and third-order terms include (2fa+fb), (2fa-fb), (fa+2fb), and (fa-2fb).

The AD7898 is tested using the CCIF standard, where two input frequencies are used. In this case, the meanings of the second- and third-order terms are different. The second-order term is usually farther away in frequency from the original sine wave, while the third-order term is usually at a frequency close to the input frequency. Therefore, the second-order and third-order terms are specified separately. Intermodulation distortion is calculated according to the thd specification, where it is the ratio of the rms sum of a single distortion product to the rms amplitude of the fundamental in dbs.

Relative accuracy

Relative accuracy or endpoint nonlinearity is the maximum deviation from a straight line through the endpoints of the ADC transfer function.

Differential nonlinearity

This is the difference between the measured value and the ideal 1 LSB change between any two adjacent codes in the ADC.

Positive Full-Scale Error (AD7898-10)

This is the deviation of the last code transition (01). ...110-01. ...111) After adjusting the bipolar zero error, start from the ideal value (4 × VREF – 3/2 LSB).

Positive Full-Scale Error (AD7898-3)

This is the deviation of the last code transition (01). ...110 to 01....111) After adjusting the bipolar zero error, start from the ideal value (VREF – 3/2 LSB).

Bipolar Zero Error (AD7898-10, AD7898-3)

This is the deviation of the mesoscale transformation (all 0s to all 1s) from ideal agnd – 1/2 lsb.

Negative Full-Scale Error (AD7898-10)

This is the deviation of the first code transition (10). ... 000 to 10. ...001) After adjusting the bipolar zero error, start from the ideal value (–4 × VREF + 1/2 LSB).

Negative Full-Scale Error (AD7898-3)

This is the deviation of the first code transition (10). ... 000 to 10. ...001) After adjusting the bipolar zero error, start with the ideal value (–vref+1/2 lsb).

Track/Hold Acquisition Time

Track/Hold capture time is the time it takes for the output of the track/hold amplifier to reach its final value (within ±1/2 lsb) after the conversion ends (the point at which the track/hold returns to track mode). It also applies when there is a step input change in the input voltage on the VIN input of the AD7898. This means that the user must wait for the duration of the track/hold acquisition time after the transition ends or after the step input is changed to vin before starting another transition to ensure the part is running to specification.

Power supply rejection

Changes in the power supply will affect the full-scale conversion, but will not affect the linearity of the converter. Power supply rejection is the maximum change in the full-scale transition point due to a change in supply voltage from nominal.

Typical Performance Characteristics - AD7898

performance curve

TPC 1 shows a typical FFT plot of the AD7898 at 220 ksps sample rate and 30 kHz input frequency when operating in Mode 0.

TPC 2 shows a typical FFT plot of the AD7898 at 220 ksps sample rate and 30 kHz input frequency when operating in Mode 1.

TPC 3 shows the power supply rejection ratio of the AD7898 as a function of supply frequency. The power supply rejection ratio is defined as the ratio of the power output by the ADC at full scale frequency f to the power of the 100 mv sine wave applied to the ADC-VDD supply at frequency fs.

phenolic = power at frequency f in ADC output, pfs = power at frequency fs coupled to ADC VDD supply input. Here a 100 mV peak-to-peak sine wave is coupled to the VDD supply. The power supply is decoupled with 100nf.

tpc 4 shows a plot of effective bits versus input frequency at 220ksps sampling.

The effective number of bits of a device can be calculated from its measured signal-to-noise ratio (noise + distortion) (see Terminology section). tpc 4 shows a typical plot of effective bits versus frequency for the AD7898 from dc to fsample/2. The sampling frequency is 220 ksps.

The formula for calculating the signal-to-noise ratio is related to the resolution or number of bits of the converter. Rewrite the formula below to give a performance measure in significant digits (n):

where snr is the signal-to-noise ratio.

tpc 5 shows a graph of signal-to-noise ratio (noise + distortion) versus input frequency for different supply voltages when sampled at 220ksps. On-chip track and hold can accommodate frequencies up to 4.7 MHz for the AD7898-3 and up to 3.6 MHz for the AD7898-10, making the AD7898 ideal for subsampling applications.

noise

In a/d converters, noise manifests itself as code uncertainty in DC applications and as a noise floor (eg in fft) in AC applications. In a sampling A/D converter like the AD7898, all information about the analog input is present in baseband, from DC to half the sampling frequency. The input bandwidth of track/hold exceeds the Nyquist bandwidth, so in applications where such a signal is present, an antialiasing filter should be used to remove unwanted signals above FS/2 in the input signal.

TPC 6 shows a histogram of 8192 dc input transitions using the AD7898. The analog input is set at the center of the transcoding. As can be seen, almost all the codes appear in one output bin, which shows that the ADC has very good noise performance.

Converter Details

The AD7898 is a fast 12-bit single-supply A/D converter. It provides users with signal scaling, track/hold, a/d converter and serial interface logic functions on a microcontroller. The A/D converter part of the AD7898 consists of a traditional successive approximation converter based on an R2R ladder structure. The signal scaling on the AD7898-10 and AD7898-3 allows the part to handle ±10 V and ±2.5 V input signals, respectively, while operating from a single 5 V supply. This part requires an external 2.5 V reference. The reference input to the part is buffered on-chip. AD7898 has two operating modes, one is the internal clock mode using the on-chip oscillator, and the other is the external clock mode using SCLK as the main clock. The latter mode has a power-down mechanism. These modes are discussed in more detail in the "Modes of Operation" section.

A major advantage of the AD7898 is that it provides all of the above features in an 8-lead SOIC package. This offers the user a considerable spacing saving advantage compared to other solutions. The AD7898 consumes only 22.5 megawatts of maximum power, making it ideal for battery-powered applications.

In Mode 0 operation, conversions are initiated on the AD7898 by pulsing the convst input. On the falling edge of convst, the on-chip track/hold switches from track to hold mode, starting the conversion sequence. The conversion clock for this part is generated internally using a laser trimmed clock oscillator circuit. The AD7898 has a conversion time of 3.3 microseconds and a quiet time of 0.1 microseconds. To get the best performance from the part in Mode 0, no read operations should take place during transitions.

In Mode 1 operation, a conversion is initiated on the AD7898 by the falling edge of CS. It takes 16 sclk cycles to complete the conversion and access the conversion result, after which time cs may go high. In this mode, the internal oscillator is not used as the conversion clock, but as SCLK. In Mode 1, the maximum SCLK frequency is 3.7 MHz, providing a minimum conversion time of 4.33 μs. In Mode 0, another conversion should not be started during the quiet time following the end of a conversion.

Both modes of operation allow the part to operate at throughputs up to 220 kHz and meet data sheet specifications.

Circuit Description Analog Input Section

The AD7898 is divided into two types: AD7898-10, which handles a ±10 V input voltage range, and AD7898-3, which handles a ±2.5 V input voltage range.

Figure 2 shows the analog input section of the AD7898-10 and AD7898-3. The analog input range of the AD7898-10 is ±10 V, and the input resistance is typically 30 kΩ. The analog input range of the AD7898-3 is ±2.5 V, and the input resistance is typically 6 kΩ. This input is benign, with no dynamic charging current because the resistive stage is followed by the high input impedance stage of the track/hold amplifier. For the AD7898-10, r1=30 kΩ, r2=7.5 kΩ, and r3=10 kΩ. For AD7898-3, r1=r2=6.5 kΩ, r3 is open.

For AD7898-10 and AD7898-3, the designed transcoding occurs in the middle between consecutive lsb values (i.e. 1/2 lsb, 3/2 lsb, 5/2 lsb). …). The output encoding is 2's complement binary, lsb=fs/4096. For AD7898-10 1 LSB=20/4096=4.88 mV. For the AD7898-3, 1 LSB=5/4096=1.22 mV.

Figure 3 shows a plot of THD versus source impedance for different analog input frequencies when using a supply voltage of 5 V, a voltage of 5 V, and a sampling rate of 220 ksps. The source impedance has little effect on thd because the input section of the ADC uses a resistor ladder structure. Figure 4 shows a plot of thd versus analog input frequency for different supply voltages when sampled at 220 ksps.

Supply voltage

Acquisition time

The track-and-hold amplifier enters its tracking mode on the falling 14th sclk edge after the falling edge of cs for Mode 1 operation. The time required for the track-and-hold amplifier to acquire the input signal depends on how fast the 9.1pf sampling capacitor charges. With zero source impedance at the analog input, two SCLK cycles plus TQUIET is always sufficient to acquire the signal to a 12-bit level. When the sclk frequency is 3.7mhz, the acquisition time is 2×(270ns)+tquiet.

Calculate the required acquisition time using the formula: tACQ = 10 × (RC)

where r is the resistance that the track-and-hold amplifier sees looking back at the input, for example, r = 3.75 kΩ for the AD7898-10 and r = 3.25 kΩ for the AD7898-3. The value of the sampling capacitor is 9.1 pf. The theoretical acquisition time is 340 nanoseconds for the AD7898-10 and 295 nanoseconds for the AD7898-3. These theoretical values do not include the tquiet or trace propagation delay in the section, which is typically 520 ns for the AD7898-10 and 450 ns for the AD7898-3.

Typical Wiring Diagram

Figure 5 shows a typical connection diagram for the AD7898. The ground pin is connected to the analog ground plane of the system. The ref-in is connected to a 2.5v supply separate from the reference source ad780. This provides a mock reference for the part. The AD7898 is connected to 5V of VDD and the serial interface is connected to a 3V microprocessor. The VDrive pin of the AD7898 is connected to the same 3V supply as the microprocessor to allow a 3V logic interface. The conversion result from the AD7898 is output as a 16-bit word with four leading zeros followed by the msb of the 12-bit result. For applications involving power consumption, power down mode should be used between transitions or pulses of multiple transitions to improve power supply performance. See the Operating Modes section.

V drive function

AD7898 has VDrive function. VDrive controls the voltage at which the serial interface operates. VDrive allows easy connection of ADCs to 3 V and 5 V processors. For example, if the VDD of the AD7898 is 5 V, and the VDrive pin can be powered by a 3 V supply. The AD7898 has good dynamic performance with a VDD of 5V, while still being able to interface with 3V digital parts. Care should be taken to ensure that VDRIVE does not exceed VDD by more than 0.3 V (see the Absolute Maximum Ratings section).

track/hold segment

A track/hold amplifier on the analog input of the AD7898 allows the ADC to accurately convert an input sine wave of full-scale amplitude to 12-bit accuracy. Even when the ADC is at its maximum throughput rate of 220 kSPS (that is, the track/hold can handle input frequencies in excess of 112 kHz), the input bandwidth of the track/hold is greater than the ADC's Nyquist rate. The track/hold amplifier acquires an input signal with 12-bit precision in less than 0.5 microseconds.

The operation of tracking/holding is basically transparent to the user. When in operating mode 0, the track/hold amplifier goes from its track mode to its hold mode at the start of a conversion (ie, the falling edge of convst). The aperture time for track/hold (i.e. the delay time between the external convst signal and the actual track/hold entering the hold) is typically 15ns. At the end of the transition (after a maximum of 3.3 microseconds), the part returns to its tracking mode. The acquisition time of the track/hold amplifier starts at this point.

When operating in mode 1, the falling edge of CS puts the track and hold into hold mode. On the 14th SCLK falling edge after the CS falling edge, track and hold will return to track (see the Serial Interface section). The acquisition time of the track/hold amplifier starts at this point.

reference input

The reference input to the AD7898 is buffered on-chip with a maximum reference input current of 1µA. This section is specified with a 2.5 V reference input voltage. Errors in the reference source will cause gain errors in the AD7898 transfer function and will add to the full-scale errors specified on the part. Reference sources suitable for the AD7898 include the AD780 and AD680 reference sources that are accurate to 2.5V.

serial interface

The serial interface to the AD7898 consists of only three wires: serial clock input (SCLK), serial data output (SData), and CS/CONVST input, depending on the mode of operation.

This enables an easy-to-use interface to most microcontrollers, DSPs and shift registers. There is also a VDrive pin that allows the serial interface to connect directly to a 3V or 5V processor system independent of VDD. Serial interface operation differs in Mode 0 and Mode 1 operation, depending on the mode selected. After power up, the default operating mode is Mode 0. To select Mode 1 operation, see the Mode Selection section. Serial interface operation in Mode 0 and Mode 1 is detailed in the Operating Modes section.

Operation Mode Mode 0 Operation

The timing diagram in Figure 6 shows the AD7898 operating in Mode 0, where the falling edge of convst initiates the conversion and places the track/hold amplifier in its hold mode. After the falling edge of convst, the conversion completes a maximum of 3.3 microseconds, and new data from this conversion is available in the output registers of the AD7898. Read operations access this data. This read operation consists of 16 clock cycles, the length of this read operation will depend on the serial clock frequency. For the fastest throughput rate (serial clock at 15 MHz, 5 V operation), a read operation will take 1.066 microseconds. Once the read operation is complete, the required quiet time should be allowed before the next falling edge of convst in order to optimize the track/hold amplifier settings before the next conversion begins. Serial clocks smaller than 15mhz can be used, but this will in turn mean that throughput times will increase.

The read operation consists of 16 serial clock pulses to the output shift register of the AD7898. After 16 serial clock pulses, the shift register is reset and the sdata line is asserted three times. If there are more serial clock pulses after the 16th clock, the shift register will move after its reset state. However, the shift register will reset again on the falling edge of the convst signal to ensure that the part returns to a known state after each conversion cycle. Therefore, the read operation of the output register should not cross the falling edge of convst, because the output shift register will be reset in the middle of the read operation, and the data returned to the microprocessor will appear invalid.

Figure 7 shows the timing diagram for a read operation to the AD7898 in Mode 0. The serial clock input (SCLK) provides the clock source for the serial interface. Serial data is clocked from the sdata line on the falling edge of this clock and is valid on the rising and falling edges of sclk depending on the sclk frequency used. The advantage of having data validity on the rising and falling edges of SCLK is that it gives the user more flexibility in connecting to components and allows to accommodate a wider range of microprocessor and microcontroller interfaces. This also explains the two timing numbers t4 and t5 referenced in the figure.

Time t4 specifies how long after the falling edge of sclk the next data bit becomes valid, while time t5 specifies how long after the falling edge of sclk the current data bit is valid. The first leading zero is clocked on the first rising edge of SCLK. Note that the first leading zero is valid on the first falling edge of sclk even though data access times are specified for other bits at t4 (see timing specification). The reason the first bit is clocked faster than the other bits is the internal structure of the part. 16 clock pulses must be given to the part to get the full conversion result. The AD7898 provides four leading zeros followed by a 12-bit conversion result starting with msb (db11). The last data bit to clock on the fifteenth falling clock edge is lsb (db0). On the 16th falling edge of sclk, lsb(db0) will be valid for the specified time to allow bits to be read on the falling edge of sclk, then the sdata line is disabled (three states). After the last bit has been clocked, the SCLK input should return low and remain low until the next serial data read operation. If there is an additional clock pulse after the 16th clock, the AD7898 will restart, output data from its output registers, and the data bus is no longer 3-state even if the clocks are stopped. If the serial clock has stopped before the next falling edge of convst, the AD7898 will continue normal operation and reset the output shift register on the falling edge of convst. However, when convst goes low, the sclk line must be low in order to properly reset the output shift register.

During serial read operations, the 16 serial clock inputs do not have to be continuous. 16-bit data (4 leading zeros and 12-bit conversion result) can be read in bytes from the ad7898.

The AD7898 counts the serial clock edges to know which bit in the output register should be placed on the SData output. To ensure the part does not lose synchronization, the serial clock counter will reset on the falling edge of the convst input as long as the SCLK line is low. The user should ensure that the SCLK line is held low until the end of the conversion. After the conversion is complete, the output register is loaded with the new conversion result and can be read from the ADC for 16 clock cycles of SCLK.

Mode 1 operation

The timing diagram in Figure 8 shows the AD7898 operating in Mode 1. The serial clock provides the conversion clock and controls the transfer of information from the AD7898 during conversion.

CS initiates the data transfer and conversion process. The falling edge of CS puts the track and hold into hold mode, taking the bus out of the three states, at which point the analog input is sampled. The conversion also starts at this time and takes 16 SCLK cycles to complete. On the 14th SCLK falling edge, the track and hold will return to the track. On the falling edge of SCLK #16, the SData line will return to tri-state. If the rising edge of CS occurs before the 16th SCLK has passed, the conversion will terminate and the SData line will return to the three states, otherwise SData will return to the three states on the 16th SCLK falling edge, as shown in Figure 8.

16 serial clock cycles are required to perform the conversion process and access data from the AD7898. cs going low provides the first leading zero, read in by the microcontroller or dsp. The remaining data is then clocked out by subsequent falling edges of sclk starting with the second leading zero, so the first falling edge on the serial clock has the first leading zero provided, and the second leading zero is also clocked out. The last bit in the data transfer is valid on the 16th falling edge and clocked on the previous (15th) falling edge. Data on each rising edge of sclk can also be read in, although the first leading zero must still be read on the first falling edge of sclk after the falling edge of cs. So if the application requires data to be read on every rising edge, the first rising edge of sclk after the falling edge of cs will provide the second leading zero and the 15th rising edge will provide db0.

Mode selection

After power-up, the default operating mode of the AD7898 is Mode 0. The part will continue to operate in Mode 0 as outlined in the Mode 0 Operation section, provided that the sclk edge is not applied to the AD7898 during the transition time and when convst is low. If the SCLK edge is applied to the AD7898 during a conversion and is low during the conversion

In Mode 0, the part will switch to Mode 1 for operation, as shown in Figure 9. The serial interface will now operate as described in the Mode 1 Operation section. The AD7898 will return from Mode 1 to Mode 0 operation if CS is low, and then return high without providing any SCLK edges when CS is low (see Figure 10). If in mode 1 any sclk edge is applied to the device while cs is low, the part will remain in mode 1 and may or may not enter a power down mode determined by the number of sclks applied, see Power Down Mode section.

If the part is operating in mode 0 and the SCLK line fails while convst is low, the part will enter mode 1 and the conversion initiated by convst low will terminate. The part will now operate in mode 1, but mode 0 signals will still be applied from the processor. When CS goes low and SCLK is not applied, the part will revert to Mode 0 operation. This avoids accidental mode changes due to glitches on the SCLK line.

Power down mode

Power-down mode can only be entered when Mode 1 is running. This mode is used in applications that require lower throughput rates; between each conversion, the adc is powered down, or a series of conversions can be performed at high throughput rates, and between bursts of these multiple conversions, The duration of the adc power outage is relatively long. When the AD7898 is powered down, all analog circuits are powered down.

Once CS is brought high during this window of SCLK, the part will enter a power-down state, the conversion initiated by the falling edge of CS will terminate, and SData will return to three states.

To exit this mode of operation and power up the AD7898 again, a dummy conversion is performed. On the falling edge of cs, the device will start to power up and will continue to power up as long as cs is held low until after the falling edge of the 11th sclk. Once 16 SCLKs have passed, the device will be fully powered up and the next conversion will result in valid data, as shown in Figure 12. If CS goes high before the 11th falling edge of SCLK, the AD7898 will power down again. This avoids accidental power-up due to CS line failure or unexpected bursts of 8 SCLK cycles when CS is low. So while the device may start powering up on the falling edge of cs, it will power down again on the rising edge of cs as long as that happens before the 11th sclk falling edge.

Power-on time

The power-on time of the AD7898 is typically 4.33 microseconds, which means that one dummy cycle will always be sufficient to power up the device when SCLK is at any frequency up to 3.7 MHz. Once the dummy cycle is complete, the ADC will be fully powered up and will get the input signal correctly. Quiet time tquiet must still be allowed from the point where the bus returns to three states after a virtual transition to the next falling cs edge.

When powered from power down mode at any SCLK frequency, the dummy cycle is sufficient to power up the device and fully acquire the VIN; it does not necessarily mean that a full dummy cycle of 16 SCLKs must always go through to power up the device and fully acquire the VIN. 4.33 microseconds is enough to start the device and fully acquire the VIN. For example, if a 1 mhz sclk frequency is applied to the adc, the cycle time will be 16 microseconds.

In a 16-microsecond dummy loop, the component will power up and fully acquire the VIN. However, after 4.33 microseconds, when using a 1 MHz SCLK, only 4 SCLK cycles will have elapsed. At this stage, the ADC will be fully powered up and pick up the signal. So in this case cs can go high after the 11th sclk falling edge and cs can go low again after tquiet to start a new conversion.

Microprocessor/Microcontroller Interface for Mode 0 Operation

The AD7898 provides a 3-wire serial interface that can be used to connect to the serial ports of DSP processors and microcontrollers. Figures 13 through 16 show the AD7898 interfacing with many different microcontrollers and digital signal processors. The AD7898 accepts an external serial clock, so in all the interfaces shown here, the processor/controller is configured as the master, providing the serial clock, and the AD7898 is configured as the slave in the system. The AD7898 does not have a busy signal, so the read operation should be timed to 3.3 microseconds after convst goes low.

8x51/l51 to ad7898 interface

Figure 13 shows the AD7898 and the 8x51/l51 microcontroller. The 8x51/l51 is configured in its Mode 0 serial interface mode. The diagram shows the simplest form of the interface, where the AD7898 is the only part connected to the 8X51/L51 serial port, so serial read operations do not need to be decoded.

To chip select the AD7898 in a system where multiple devices are connected to the 8x51/l51 serial port, the serial clock to the AD7898 can be turned on or off using a port bit configured as an output of one of the 8x51/l51 parallel ports. A simple sum function on this port bit and a serial clock from 8x51/L51 will provide this functionality. The port bit should be high to select the AD7898, and low when not selected.

During a read operation, the AD7898 outputs msb first, while the 8xl51 outputs lsb first. Therefore, the data read into the serial buffer needs to be rearranged before the correct data format for the AD7898 appears in the accumulator.

The serial clock frequency from the 8x51/l51 is limited to significantly lower than the allowable input serial clock frequency that the AD7898 can work with. Therefore, the time to read data from the component is actually longer than the transition time of the component. This means that the AD7898 cannot run at its maximum throughput when used with the 8x51/L51.

68HC11/L11 to AD7898 interface

The interface circuit between the AD7898 and the 68HC11/L11 microcontroller is shown in Figure 14. For the interface shown, the 68L11 SPI port is used and the 68L11 is configured in its microcontroller mode. The 68L11 is configured in master mode with its cpol bit set to logic zero and its cpha bit set to logic one. As with the previous interface, this diagram shows the simplest form of the interface, where the AD7898 is the only part connected to the serial port of the 68l11, so serial read operations do not need to be decoded.

Again, to chip select the AD7898 in a system where multiple devices are connected to the 68HC11 serial port, the serial clock to the AD7898 can be turned on or off using a port bit configured as an output of one of the 68HC11 parallel ports. A simple sum function on this port bit and the 68L11's serial clock will provide this functionality. The port bit should be high to select the AD7898, and low when not selected.

The serial clock rate of the 68HC11/L11 is limited to significantly less than the allowable input serial clock frequency at which the AD7898 can operate. Therefore, the time to read data from the component is actually longer than the transition time of the component. This means that the AD7898 cannot operate at its maximum throughput rate when used with the 68 HC11/L11.

ADSP-2103/ADSP-2105 to AD7898 interface

The interface circuit between AD7898 and ADSP-2103/ADSP-2105 digital signal processor is shown in Figure 15. In the interface shown, RFS1 output from the SPORT1 serial port of the ADSP-2103/ADSP-2105 is used to clock the serial clock (SCLK1) of the ADSP-2103/ADSP-2105 before it is applied to the SCLK input of the AD7898 strobe. The RFS1 output is configured to run high. This interface ensures that the clock of the AD7898 serial clock input is discontinuous, only 16 serial clock pulses are provided, and the serial clock line of the AD7898 remains low between data transfers. After convst goes low, read operations should be timed in 3.3 microseconds. The SData line from the AD7898 is connected to the DR1 line of the ADSP-2103/ADSP-2105 serial port.

The timing relationship between the sclk1 and rfs1 outputs of the adsp-2103/adsp-2105 results in a delay of up to 30ns between the rising edge of sclk1 and the rising edge of active high RFs1. It is also required to set the data 10 ns before the falling edge of SCLK1 for the ADSP-2103/ADSP-2105 to read correctly. The data access time for the AD7898 is t4 (5V) from the rising edge of its SCLK input. Assuming a propagation delay of 10ns through the external and gate, the high time of the sclk1 output of the adsp-2105 must be ≥(30+60+10+10)ns, which is ≥110ns.

This means that the serial clock frequency at which the interface of Figure 15 can work is limited to 4.5mhz. However, there is an alternative that allows the adsp-2105sclk1 to run at 5mhz (the maximum serial clock frequency output by the sclk1). This arrangement occurs when the first leading zero of the data stream from the AD7898 cannot be guaranteed to be clocked to the ADSP-2105 due to the combined delay of the RFS signal and the AD7898's data access time. In most cases this is acceptable as there are still three leading zeros followed by 12 data bits.

Another alternative is to configure the adsp-2103/adsp-2105 to accept an external non-continuous serial clock. In this case, an external discontinuous serial clock is provided to drive the serial clock input of the adsp2103/adsp-2105 and ad7898. In this scheme, the serial clock frequency is limited to 15mhz by the ad7898.

DSP56002/L002 to AD7898 interface

Figure 16 shows the interface circuit between the AD7898 and the DSP56002/L002 DSP processor. The DSP56002/L002 is configured for normal mode asynchronous operation with gated clocks. It is also set to a 16-bit word with SCK output as a gated clock. In this mode, the DSP56002/L002 provides 16 serial clock pulses to the AD7898 in a serial read operation. Since the DSP56002/L002 assumes valid data on the first falling edge of SCK, the interface is only 2-wire, as shown in Figure 16.

Mode 1 Microprocessor Interface

The serial interface on the AD7898 in Mode 1 allows the part to be directly connected to many different microprocessors. This section shows how to interface the AD7898 with some of the more common microcontrollers and DSP serial interface protocols used for Mode 1 operation.

tms320c5x/c54x to ad7898 interface

The serial interface on the tms320c5x/c54x uses continuous serial clock and frame sync signals to synchronize data transfer operations with peripherals such as the AD7898. The cs input allows easy interfacing between the tms320c5x/c54x and the ad7898 without any glue logic. The serial port of the tms320c5x/c54x is set up to work in burst mode with the internal clkx (tx serial clock) and fsx (tx frame sync). The serial port control register (spc) must have the following settings: fo=0, fsm=1, mcm=1, and txm=1. To implement power-down mode on the AD7898, the format bit fo can be set to 1 to set the word length to 8 bits.

The connection diagram is shown in Figure 17. Note that for signal processing applications, the frame sync signal from the tms320c5x/c54x must provide equidistant sampling. The VDrive pin of the AD7898 uses the same supply voltage as the tms320c5x/c54x. This allows the ADC to operate at higher voltages than the serial interface (ie tms320c5x/c54x if necessary).

AD7898 to ADSP-21xx interface

The ADSP-21xx family of DSPs does not require any glue logic to interface directly to the AD7898. The VDrive pin of the AD7898 uses the same supply voltage as the ADSP-21xx. This allows the ADC to operate (if necessary) at higher voltages than the serial interface (like the adsp-21xx).

The settings of the motion control registers are as follows:

tfsw=rfsw=1, alternate frames

invrfs=invtfs=1, valid low frame signal

dtype=00, right-aligned data

slen=1111, 16-bit data word

ISCLK=1, internal serial clock

tfsr=rfsr=1, irfs=0 per word frame, itfs=1.

To implement power-down mode, slen should be set to 1001 to issue 8-bit sclk bursts.

The connection diagram is shown in Figure 18. The ADSP-21XX connects the motion's TFS and RFS together, with TFS set as output and RFS set as input. The dsp operates in alternate frame mode, and the motion control registers are set as described. The frame sync signal generated on tfs is connected to cs, and for all signal processing applications, equidistant sampling is necessary. However, in this example, the timer interrupt is used to control the sampling rate of the ADC, and in some cases equidistant sampling may not be possible.

Timer registers etc. are loaded with a value that will provide an interrupt at the desired sampling interval. When an interrupt is received, send a value with tfs/dt (adc control word). tfs is used to control rfs and thus read data. The frequency of the serial clock is set in the SCLKDIV register. Check the status of sclk when an instruction to transfer with tfs is given (ie ax0=tx0). The dsp will wait for sclk to go high, low and high before starting a transfer. If the timer and sclk values are chosen such that the instruction to be sent occurs on or near the rising edge of sclk, the data can be sent, or it can wait until the next clock edge.

For example, the adsp-2111 has a master clock frequency of 16 MHz. If the SCLKDIV register is loaded with a value of 3, you get a 2 MHz SCLK, and every 1 SCLK cycle will elapse for 8 master clock cycles. If the timer register is loaded with the value 803, then 100.5 sclk will occur between interrupts and then between sending instructions. This condition will result in non-equidistant sampling when the send command occurs on the edge of SCLK. If the number of sclks between interrupts is an integer of n, equidistant sampling is implemented by the dsp.

AD7898 to DSP56XXX interface

The connection diagram in Figure 19 shows how the AD7898 connects to the SSI (Synchronous Serial Interface) of the Motorola DSP56xxx family of DSPs. ssi operates in sync mode (syn bit = 1 in crb), internally generated 1-bit clock cycle frame synchronization of tx and rx (fsl1 = 1 and fsl0 = 0 in crb). Set the word length to 16 by setting bits WL1=1 and WL0=0 in the CRA. To implement power-down mode on the AD7898, the word length can be changed to 8 bits by setting bits WL1=0 and WL0=0 in the CRA. It should be noted that for signal processing applications, the frame sync signal from the dsp56xxx must provide equidistant sampling. The VDrive pin of the AD7898 uses the same supply voltage as the DSP56XXX. This allows the ADC to operate (if necessary) at higher voltages than the serial interface (like the dsp56xxx).

AD7898 to MC68HC16 interface

The Serial Peripheral Interface (SPI) on the MC68HC16 is configured in master mode (MSTR=1), clock polarity bit (CPOL)=1 and clock phase bit (CPHA)=0. The SPI is configured by writing to the SPI Control Register (SPCR) (see 68HC16 User Manual). When the SIZE bit in the SPCR register is set to SIZE=1, the serial transfer will proceed as a 16-bit operation. to implement a power-down mode with an 8-bit transfer set size of 0. The connection diagram is shown in Figure 20. The VDrive pin of the AD7898 uses the same supply voltage as the MC68HC16. This allows the ADC to operate at higher voltages than the serial interface (i.e. the mc68hc16) if necessary.